AArch64-esr_el1.xml [plain text]
<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>
<register_page>
<registers>
<register execution_state="AArch64" is_register="True" is_internal="True" is_banked="False" is_optional="False" is_stub_entry="False">
<reg_short_name>ESR_EL1</reg_short_name>
<reg_long_name>Exception Syndrome Register (EL1)</reg_long_name>
<reg_reset_value></reg_reset_value>
<reg_mappings>
<reg_mapping>
<mapped_name filename="AArch32-dfsr.xml">DFSR</mapped_name>
<mapped_type>Architectural</mapped_type>
<mapped_execution_state>AArch32</mapped_execution_state>
<mapped_from_startbit>31</mapped_from_startbit>
<mapped_from_endbit>0</mapped_from_endbit>
<mapped_to_startbit>31</mapped_to_startbit>
<mapped_to_endbit>0</mapped_to_endbit>
</reg_mapping>
</reg_mappings>
<reg_purpose>
<purpose_text>
<para>Holds syndrome information for an exception taken to EL1.</para>
</purpose_text>
</reg_purpose>
<reg_groups>
<reg_group>Exception and fault handling registers</reg_group>
</reg_groups>
<reg_usage_constraints>
</reg_usage_constraints>
<reg_configuration>
</reg_configuration>
<reg_attributes>
<attributes_text>
<para>ESR_EL1 is a 64-bit register.</para>
</attributes_text>
</reg_attributes>
<reg_fieldsets>
<fields length="64">
<text_before_fields>
<para>ESR_EL1 is made <arm-defined-word>UNKNOWN</arm-defined-word> as a result of an exception return from EL1.</para>
<para>When an <arm-defined-word>UNPREDICTABLE</arm-defined-word> instruction is treated as <arm-defined-word>UNDEFINED</arm-defined-word>, and the exception is taken to EL1, the value of ESR_EL1 is <arm-defined-word>UNKNOWN</arm-defined-word>. The value written to ESR_EL1 must be consistent with a value that could be created as a result of an exception from the same Exception level that generated the exception as a result of a situation that is not <arm-defined-word>UNPREDICTABLE</arm-defined-word> at that Exception level, in order to avoid the possibility of a privilege violation.</para>
</text_before_fields>
<field
id="0_63_32"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>63</field_msb>
<field_lsb>32</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="EC_31_26"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="True"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>EC</field_name>
<field_msb>31</field_msb>
<field_lsb>26</field_lsb>
<field_description order="before">
<para>Exception Class. Indicates the reason for the exception that this register holds information about.</para>
<para>For each EC value, the table references a subsection that gives information about:</para>
<list type="unordered">
<listitem><content>The cause of the exception, for example the configuration required to enable the trap.</content>
</listitem><listitem><content>The encoding of the associated ISS.</content>
</listitem></list>
<para>Possible values of the EC field are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b000000</field_value>
<field_value_description>
<para>Unknown reason.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exceptions with an unknown reason"/>
</field_value_instance>
<field_value_instance>
<field_value>0b000001</field_value>
<field_value_description>
<para>Trapped WFI or WFE instruction execution.</para>
<para>Conditional WFE and WFI instructions that fail their condition code check do not cause an exception.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a WFI or WFE instruction"/>
</field_value_instance>
<field_value_instance>
<field_value>0b000011</field_value>
<field_value_description>
<para>Trapped MCR or MRC access with (coproc==<binarynumber>0b1111</binarynumber>) that is not reported using EC <binarynumber>0b000000</binarynumber>.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an MCR or MRC access"/>
</field_value_instance>
<field_value_instance>
<field_value>0b000100</field_value>
<field_value_description>
<para>Trapped MCRR or MRRC access with (coproc==<binarynumber>0b1111</binarynumber>) that is not reported using EC <binarynumber>0b000000</binarynumber>.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an MCRR or MRRC access"/>
</field_value_instance>
<field_value_instance>
<field_value>0b000101</field_value>
<field_value_description>
<para>Trapped MCR or MRC access with (coproc==<binarynumber>0b1110</binarynumber>).</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an MCR or MRC access"/>
</field_value_instance>
<field_value_instance>
<field_value>0b000110</field_value>
<field_value_description>
<para>Trapped LDC or STC access.</para>
<para>The only architected uses of these instruction are:</para>
<list type="unordered">
<listitem><content>An STC to write data to memory from <register_link state="AArch32" id="AArch32-dbgdtrrxint.xml">DBGDTRRXint</register_link>.</content>
</listitem><listitem><content>An LDC to read data from memory to <register_link state="AArch32" id="AArch32-dbgdtrtxint.xml">DBGDTRTXint</register_link>.</content>
</listitem></list>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an LDC or STC instruction"/>
</field_value_instance>
<field_value_instance>
<field_value>0b000111</field_value>
<field_value_description>
<para>Access to SVE, Advanced SIMD, or floating-point functionality trapped by <register_link state="AArch64" id="AArch64-cpacr_el1.xml">CPACR_EL1</register_link>.FPEN, <register_link state="AArch64" id="AArch64-cptr_el2.xml">CPTR_EL2</register_link>.FPEN, <register_link state="AArch64" id="AArch64-cptr_el2.xml">CPTR_EL2</register_link>.TFP, or <register_link state="AArch64" id="AArch64-cptr_el3.xml">CPTR_EL3</register_link>.TFP control.</para>
<para>Excludes exceptions resulting from <register_link state="AArch64" id="AArch64-cpacr_el1.xml">CPACR_EL1</register_link> when the value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1, or because SVE or Advanced SIMD and floating-point are not implemented. These are reported with EC value <binarynumber>0b000000</binarynumber> as described in <xref linkend="CHDJCBHE" browsertext="'EC encodings when routing exceptions to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.10.4" filename="D_the_aarch64_system_level_programmers_model"/>.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an access to SVE, Advanced SIMD or floating-point functionality, resulting from CPACR_EL1.FPEN, CPTR_EL2.FPEN or CPTR_ELx.TFP"/>
</field_value_instance>
<field_value_instance>
<field_value>0b001100</field_value>
<field_value_description>
<para>Trapped MRRC access with (coproc==<binarynumber>0b1110</binarynumber>).</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an MCRR or MRRC access"/>
</field_value_instance>
<field_value_instance>
<field_value>0b001101</field_value>
<field_value_description>
<para>Branch Target Exception.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from Branch Target Identification instruction"/>
<field_value_condition>When ARMv8.5-BTI is implemented</field_value_condition>
</field_value_instance>
<field_value_instance>
<field_value>0b001110</field_value>
<field_value_description>
<para>Illegal Execution state.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an Illegal Execution state, or a PC or SP alignment fault"/>
</field_value_instance>
<field_value_instance>
<field_value>0b010001</field_value>
<field_value_description>
<para>SVC instruction execution in AArch32 state.</para>
<para>This is reported in ESR_EL2 only when the exception is generated because the value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from HVC or SVC instruction execution"/>
</field_value_instance>
<field_value_instance>
<field_value>0b010101</field_value>
<field_value_description>
<para>SVC instruction execution in AArch64 state.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from HVC or SVC instruction execution"/>
</field_value_instance>
<field_value_instance>
<field_value>0b011000</field_value>
<field_value_description>
<para>Trapped MSR, MRS or System instruction execution in AArch64 state, that is not reported using EC <binarynumber>0b000000</binarynumber>, <binarynumber>0b000001</binarynumber> or <binarynumber>0b000111</binarynumber>.</para>
<para>If <xref browsertext="ARMv8.4-IDST" filename="A_introduction_to_the_armv8_architecture.fm" linkend="v8.4.IDST"></xref> is implemented, also exceptions generated on a read of an ID register.</para>
<para>If <xref browsertext="ARMv8.0-CSV2" filename="A_introduction_to_the_armv8_architecture.fm" linkend="v8.0.CSV2"></xref> is implemented, also Cache Speculation Variant exceptions.</para>
<para>This includes all instructions that cause exceptions that are part of the encoding space defined in <xref linkend="BEIJIEIE" browsertext="'System instruction class encoding overview' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section C5.2.2" filename="C_the_a64_system_instruction_class"/>, except for those exceptions reported using EC values <binarynumber>0b000000</binarynumber>, <binarynumber>0b000001</binarynumber>, or <binarynumber>0b000111</binarynumber>.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from MSR, MRS, or System instruction execution in AArch64 state"/>
</field_value_instance>
<field_value_instance>
<field_value>0b011001</field_value>
<field_value_description>
<para>Access to SVE functionality trapped as a result of <register_link state="AArch64" id="AArch64-cpacr_el1.xml">CPACR_EL1</register_link>.ZEN, <register_link state="AArch64" id="AArch64-cptr_el2.xml">CPTR_EL2</register_link>.ZEN, <register_link state="AArch64" id="AArch64-cptr_el2.xml">CPTR_EL2</register_link>.TZ, or <register_link state="AArch64" id="AArch64-cptr_el3.xml">CPTR_EL3</register_link>.EZ, that is not reported using EC <binarynumber>0b000000</binarynumber>.</para>
<para>This EC is defined only if <xref linkend="SVE" browsertext="SVE" filename="A_introduction_to_the_armv8_architecture.fm"/> is implemented.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an access to SVE functionality, resulting from CPACR_EL1.ZEN, CPTR_EL2.ZEN, CPTR_EL2.TZ, or CPTR_EL3.EZ"/>
</field_value_instance>
<field_value_instance>
<field_value>0b100000</field_value>
<field_value_description>
<para>Instruction Abort from a lower Exception level, that might be using AArch32 or AArch64.</para>
<para>Used for MMU faults generated by instruction accesses and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug related exceptions.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an Instruction Abort"/>
</field_value_instance>
<field_value_instance>
<field_value>0b100001</field_value>
<field_value_description>
<para>Instruction Abort taken without a change in Exception level.</para>
<para>Used for MMU faults generated by instruction accesses and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug related exceptions.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an Instruction Abort"/>
</field_value_instance>
<field_value_instance>
<field_value>0b100010</field_value>
<field_value_description>
<para>PC alignment fault exception.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an Illegal Execution state, or a PC or SP alignment fault"/>
</field_value_instance>
<field_value_instance>
<field_value>0b100100</field_value>
<field_value_description>
<para>Data Abort from a lower Exception level, that might be using AArch32 or AArch64.</para>
<para>Used for MMU faults generated by data accesses, alignment faults other than those caused by Stack Pointer misalignment, and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug related exceptions.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Data Abort"/>
</field_value_instance>
<field_value_instance>
<field_value>0b100101</field_value>
<field_value_description>
<para>Data Abort taken without a change in Exception level.</para>
<para>Used for MMU faults generated by data accesses, alignment faults other than those caused by Stack Pointer misalignment, and synchronous External aborts, including synchronous parity or ECC errors. Not used for debug related exceptions.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Data Abort"/>
</field_value_instance>
<field_value_instance>
<field_value>0b100110</field_value>
<field_value_description>
<para>SP alignment fault exception.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from an Illegal Execution state, or a PC or SP alignment fault"/>
</field_value_instance>
<field_value_instance>
<field_value>0b101000</field_value>
<field_value_description>
<para>Trapped floating-point exception taken from AArch32 state.</para>
<para>This EC value is valid if the implementation supports trapping of floating-point exceptions, otherwise it is reserved. Whether a floating-point implementation supports trapping of floating-point exceptions is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a trapped floating-point exception"/>
</field_value_instance>
<field_value_instance>
<field_value>0b101100</field_value>
<field_value_description>
<para>Trapped floating-point exception taken from AArch64 state.</para>
<para>This EC value is valid if the implementation supports trapping of floating-point exceptions, otherwise it is reserved. Whether a floating-point implementation supports trapping of floating-point exceptions is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a trapped floating-point exception"/>
</field_value_instance>
<field_value_instance>
<field_value>0b101111</field_value>
<field_value_description>
<para>SError interrupt.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="SError interrupt"/>
</field_value_instance>
<field_value_instance>
<field_value>0b110000</field_value>
<field_value_description>
<para>Breakpoint exception from a lower Exception level, that might be using AArch32 or AArch64.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Breakpoint or Vector Catch debug exception"/>
</field_value_instance>
<field_value_instance>
<field_value>0b110001</field_value>
<field_value_description>
<para>Breakpoint exception taken without a change in Exception level.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Breakpoint or Vector Catch debug exception"/>
</field_value_instance>
<field_value_instance>
<field_value>0b110010</field_value>
<field_value_description>
<para>Software Step exception from a lower Exception level, that might be using AArch32 or AArch64.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Software Step exception"/>
</field_value_instance>
<field_value_instance>
<field_value>0b110011</field_value>
<field_value_description>
<para>Software Step exception taken without a change in Exception level.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Software Step exception"/>
</field_value_instance>
<field_value_instance>
<field_value>0b110100</field_value>
<field_value_description>
<para>Watchpoint exception from a lower Exception level, that might be using AArch32 or AArch64.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Watchpoint exception"/>
</field_value_instance>
<field_value_instance>
<field_value>0b110101</field_value>
<field_value_description>
<para>Watchpoint exception taken without a change in Exception level.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from a Watchpoint exception"/>
</field_value_instance>
<field_value_instance>
<field_value>0b111000</field_value>
<field_value_description>
<para>BKPT instruction execution in AArch32 state.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from execution of a Breakpoint instruction"/>
</field_value_instance>
<field_value_instance>
<field_value>0b111100</field_value>
<field_value_description>
<para>BRK instruction execution in AArch64 state.</para>
<para>This is reported in <register_link state="AArch64" id="AArch64-esr_el3.xml">ESR_EL3</register_link> only if a BRK instruction is executed.</para>
</field_value_description>
<field_value_links_to linked_field_name="ISS" linked_field_condition="Exception from execution of a Breakpoint instruction"/>
</field_value_instance>
</field_values>
<field_description order="after">
<para>All other EC values are reserved by Arm, and:</para>
<list type="unordered">
<listitem><content>Unused values in the range <binarynumber>0b000000</binarynumber> - <binarynumber>0b101100</binarynumber> (<hexnumber>0x00</hexnumber> - <hexnumber>0x2C</hexnumber>) are reserved for future use for synchronous exceptions.</content>
</listitem><listitem><content>Unused values in the range <binarynumber>0b101101</binarynumber> - <binarynumber>0b111111</binarynumber> (<hexnumber>0x2D</hexnumber> - <hexnumber>0x3F</hexnumber>) are reserved for future use, and might be used for synchronous or asynchronous exceptions.</content>
</listitem></list>
<para>The effect of programming this field to a reserved value is that behavior is <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word>, as described in <xref linkend="CEGHGHJI" browsertext="'Reserved values in System and memory-mapped registers and translation table entries' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section K1.1.11"/>.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="IL_25_25"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>IL</field_name>
<field_msb>25</field_msb>
<field_lsb>25</field_lsb>
<field_description order="before">
<para>Instruction Length for synchronous exceptions. Possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>16-bit instruction trapped.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<list type="unordered">
<listitem><content>
<para>An SError interrupt.</para>
</content>
</listitem><listitem><content>
<para>An Instruction Abort exception.</para>
</content>
</listitem><listitem><content>
<para>A PC alignment fault exception.</para>
</content>
</listitem><listitem><content>
<para>An SP alignment fault exception.</para>
</content>
</listitem><listitem><content>
<para>A Data Abort exception for which the value of the ISV bit is 0.</para>
</content>
</listitem><listitem><content>
<para>An Illegal Execution state exception.</para>
</content>
</listitem><listitem><content>
<para>Any debug exception except for Breakpoint instruction exceptions. For Breakpoint instruction exceptions, this bit has its standard meaning:</para>
<list type="unordered">
<listitem><content>
<para><binarynumber>0b0</binarynumber>: 16-bit T32 BKPT instruction.</para>
</content>
</listitem><listitem><content>
<para><binarynumber>0b1</binarynumber>: 32-bit A32 BKPT instruction or A64 BRK instruction.</para>
</content>
</listitem></list>
</content>
</listitem><listitem><content>
<para>An exception reported using EC value <binarynumber>0b000000</binarynumber>.</para>
</content>
</listitem></list>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="ISS_24_0"
is_variable_length="False"
has_partial_fieldset="True"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>ISS</field_name>
<field_msb>24</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Instruction Specific Syndrome. Architecturally, this field can be defined independently for each defined Exception class. However, in practice, some ISS encodings are used for more than one Exception class.</para>
<para>Typically, an ISS encoding has a number of subfields. When an ISS subfield holds a register number, the value returned in that field is the AArch64 view of the register number. For an exception taken from AArch32 state, <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1,"/> defines this view of the specified AArch32 register. If the AArch32 register descriptor is <binarynumber>0b1111</binarynumber>, then:</para>
<list type="unordered">
<listitem><content>If the instruction that generated the exception was not <arm-defined-word>UNPREDICTABLE</arm-defined-word>, the field takes the value <binarynumber>0b11111</binarynumber>.</content>
</listitem><listitem><content>If the instruction that generated the exception was <arm-defined-word>UNPREDICTABLE</arm-defined-word>, the field takes an <arm-defined-word>UNKNOWN</arm-defined-word> value that must be either:<list type="unordered">
<listitem><content>The AArch64 view of the register number of a register that might have been used at the Exception level from which the exception was taken.</content>
</listitem><listitem><content>The value <binarynumber>0b11111</binarynumber>.</content>
</listitem></list>
</content>
</listitem></list>
<para>When the EC field is <binarynumber>0b000000</binarynumber>, indicating an exception with an unknown reason, the ISS field is not valid, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
<field_value_name>I</field_value_name>
</field_values>
<field_resets>
</field_resets>
<partial_fieldset>
<fields length="25">
<fields_instance>Exceptions with an unknown reason</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<text_after_fields>
<para>When an exception is reported using this EC code the IL field is set to 1.</para>
<para>This EC code is used for all exceptions that are not covered by any other EC value. This includes exceptions that are generated in the following situations:</para>
<list type="unordered">
<listitem><content>The attempted execution of an instruction bit pattern that has no allocated instruction at the current Exception level and Security state, including:<list type="unordered">
<listitem><content>A read access using a System register pattern that is not allocated for reads at the current Exception level and Security state.</content>
</listitem><listitem><content>A write access using a System register pattern that is not allocated for writes at the current Exception level and Security state.</content>
</listitem><listitem><content>Instruction encodings for instructions not implemented in the implementation.</content>
</listitem></list>
</content>
</listitem><listitem><content>In Debug state, the attempted execution of an instruction bit pattern that is unallocated in Debug state.</content>
</listitem><listitem><content>In Non-debug state, the attempted execution of an instruction bit pattern that is unallocated in Non-debug state.</content>
</listitem><listitem><content>In AArch32 state, attempted execution of a short vector floating-point instruction.</content>
</listitem><listitem><content>In an implementation that does not include Advanced SIMD and floating-point functionality, an attempted access to Advanced SIMD or floating-point functionality under conditions where that access would be permitted if that functionality was present. This includes the attempted execution of an Advanced SIMD or floating-point instruction, and attempted accesses to Advanced SIMD and floating-point System registers.</content>
</listitem><listitem><content>An exception generated because of the value of one of the <register_link state="AArch64" id="AArch64-sctlr_el1.xml">SCTLR_EL1</register_link>.{ITD, SED, CP15BEN} control bits.</content>
</listitem><listitem><content>Attempted execution of:<list type="unordered">
<listitem><content>An HVC instruction when disabled by <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.HCD or <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.HCE.</content>
</listitem><listitem><content>An SMC instruction when disabled by <register_link state="AArch64" id="AArch64-scr_el3.xml">SCR_EL3</register_link>.SMD.</content>
</listitem><listitem><content>An HLT instruction when disabled by <register_link state="ext" id="ext-edscr.xml">EDSCR</register_link>.HDE.</content>
</listitem></list>
</content>
</listitem><listitem><content>Attempted execution of an MSR or MRS instruction to access <register_link state="AArch64" id="AArch64-sp_el0.xml">SP_EL0</register_link> when the value of <register_link state="AArch64" id="AArch64-spsel.xml">SPSel</register_link>.SP is 0.</content>
</listitem><listitem><content>Attempted execution, in Debug state, of:<list type="unordered">
<listitem><content>A DCPS1 instruction when the value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1 and EL2 is disabled or not implemented in the current Security state.</content>
</listitem><listitem><content>A DCPS2 instruction from EL1 or EL0 when EL2 is disabled or not implemented in the current Security state.</content>
</listitem><listitem><content>A DCPS3 instruction when the value of <register_link state="ext" id="ext-edscr.xml">EDSCR</register_link>.SDD is 1, or when EL3 is not implemented.</content>
</listitem></list>
</content>
</listitem><listitem><content>When EL3 is using AArch64, attempted execution from Secure EL1 of an SRS instruction using R13_mon. See <xref linkend="CHDJIEBG" browsertext="'Traps to EL3 of monitor functionality from Secure EL1 using AArch32' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content>In Debug state when the value of <register_link state="ext" id="ext-edscr.xml">EDSCR</register_link>.SDD is 1, the attempted execution at EL2, EL1, or EL0 of an instruction that is configured to trap to EL3.</content>
</listitem><listitem><content>In AArch32 state, the attempted execution of an MRS (banked register) or an MSR (banked register) instruction to SPSR_mon, SP_mon, or LR_mon.</content>
</listitem><listitem><content>An exception that is taken to EL2 because the value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE is 1 that, if the value of <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TGE was 0 would have been reported with an ESR_ELx.EC value of <binarynumber>0b000111</binarynumber>.</content>
</listitem><listitem><content>When SVE is not implemented, attempted execution of:<list type="unordered">
<listitem><content>An SVE instruction.</content>
</listitem><listitem><content>An MSR or MRS instruction to access <register_link state="AArch64" id="AArch64-zcr_el1.xml">ZCR_EL1</register_link>, <register_link state="AArch64" id="AArch64-zcr_el2.xml">ZCR_EL2</register_link>, or <register_link state="AArch64" id="AArch64-zcr_el3.xml">ZCR_EL3</register_link>.</content>
</listitem></list>
</content>
</listitem></list>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_0" msb="24" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from a WFI or WFE instruction</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="CV_24_24"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CV</field_name>
<field_msb>24</field_msb>
<field_lsb>24</field_lsb>
<field_description order="before">
<para>Condition code valid. Possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The COND field is not valid.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The COND field is valid.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>For exceptions taken from AArch64, CV is set to 1.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content>
</listitem></list>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="COND_23_20"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>COND</field_name>
<field_msb>23</field_msb>
<field_lsb>20</field_lsb>
<field_description order="before">
<para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para>
<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered">
<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content>
</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content>
</listitem></list>
</content>
</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered">
<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content>
</listitem><listitem><content>With the COND value held in the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered">
<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content>
</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content>
</listitem></list>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_19_1"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>19</field_msb>
<field_lsb>1</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="TI_0_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>TI</field_name>
<field_msb>0</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Trapped instruction. Possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>WFI trapped.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>WFE trapped.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>The following sections describe configuration settings for generating this exception:</para>
<list type="unordered">
<listitem><content><xref linkend="D1CHDJGAIC" browsertext="'Controls for exceptions taken to EL1 using AArch64' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIBHJCJ" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 execution of WFE and WFI instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDEGCIJ" browsertext="'Traps to EL3 of EL2, EL1, and EL0 execution of WFE and WFI instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem></list>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="CV_24_24" msb="24" lsb="24"/>
<fieldat id="COND_23_20" msb="23" lsb="20"/>
<fieldat id="0_19_1" msb="19" lsb="1"/>
<fieldat id="TI_0_0" msb="0" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from an MCR or MRC access</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="CV_24_24"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CV</field_name>
<field_msb>24</field_msb>
<field_lsb>24</field_lsb>
<field_description order="before">
<para>Condition code valid. Possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The COND field is not valid.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The COND field is valid.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>For exceptions taken from AArch64, CV is set to 1.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content>
</listitem></list>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="COND_23_20"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>COND</field_name>
<field_msb>23</field_msb>
<field_lsb>20</field_lsb>
<field_description order="before">
<para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para>
<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered">
<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content>
</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content>
</listitem></list>
</content>
</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered">
<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content>
</listitem><listitem><content>With the COND value held in the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered">
<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content>
</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content>
</listitem></list>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Opc2_19_17"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Opc2</field_name>
<field_msb>19</field_msb>
<field_lsb>17</field_lsb>
<field_description order="before">
<para>The Opc2 value from the issued instruction.</para>
<para>For a trapped VMRS access, holds the value <binarynumber>0b000</binarynumber>.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Opc1_16_14"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Opc1</field_name>
<field_msb>16</field_msb>
<field_lsb>14</field_lsb>
<field_description order="before">
<para>The Opc1 value from the issued instruction.</para>
<para>For a trapped VMRS access, holds the value <binarynumber>0b111</binarynumber>.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="CRn_13_10"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CRn</field_name>
<field_msb>13</field_msb>
<field_lsb>10</field_lsb>
<field_description order="before">
<para>The CRn value from the issued instruction.</para>
<para>For a trapped VMRS access, holds the reg field from the VMRS instruction encoding.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Rt_9_5"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Rt</field_name>
<field_msb>9</field_msb>
<field_lsb>5</field_lsb>
<field_description order="before">
<para>The Rt value from the issued instruction, the general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1"/>.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="CRm_4_1"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CRm</field_name>
<field_msb>4</field_msb>
<field_lsb>1</field_lsb>
<field_description order="before">
<para>The CRm value from the issued instruction.</para>
<para>For a trapped VMRS access, holds the value <binarynumber>0b0000</binarynumber>.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Direction_0_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Direction</field_name>
<field_msb>0</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Indicates the direction of the trapped instruction. The possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Write to System register space. MCR instruction.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Read from System register space. MRC or VMRS instruction.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>The following sections describe configuration settings for generating exceptions that are reported using EC value <binarynumber>0b000011</binarynumber>:</para>
<list type="unordered">
<listitem><content><xref linkend="CHDJFHAI" browsertext="'Traps to EL1 of EL0 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDGDIEA" browsertext="'Traps to EL1 of EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="BEICGACA" browsertext="'Traps to EL1 of EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIGHBDF" browsertext="'Traps to EL2 of Non-secure EL1 accesses to virtual memory control registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEICAEBH" browsertext="'Traps to EL2 of Non-secure EL1 execution of TLB maintenance instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEICHIHA" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 execution of cache maintenance instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIFCHFF" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to the Auxiliary Control Register' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="BEIDHFBB" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to lockdown, DMA, and TCM operations' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIEEJIA" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to the ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIFFJII" browsertext="'Trapping to EL2 of Non-secure EL1 accesses to the CPACR_EL1 or CPACR' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIDJJAH" browsertext="'Generic trapping to EL2 of Non-secure EL1 and EL0 accesses to System registers, from AArch32 state only' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/></content>
</listitem><listitem><content><xref linkend="CHDFFCIB" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/></content>
</listitem><listitem><content><xref linkend="D1BEICIHGI" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="BEIGCEGJ" browsertext="'Traps to EL2 of EL1 and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="CHDJIEBG" browsertext="'Traps to EL3 of Secure monitor functionality from Secure EL1 using AArch32' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDJACCE" browsertext="'Trapping to EL3 of EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDGGBGH" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="BEIHHEIC" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem></list>
<para>The following sections describe configuration settings for generating exceptions that are reported using EC value <binarynumber>0b000101</binarynumber>:</para>
<list type="unordered">
<listitem><content><xref linkend="D1CHDBAICA" browsertext="'Traps to EL1 of EL0 and EL1 System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDIGAJA" browsertext="'Traps to EL1 of EL0 accesses to the Debug Communications Channel (DCC) registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIEEJIA" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to the ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>, for trapped accesses to the JIDR.</content>
</listitem><listitem><content><xref linkend="D1BEIIHJHA" browsertext="'Traps to EL2 of Non-secure system register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIHBBIC" browsertext="'Trapping System register accesses to Debug ROM registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIECEGJ" browsertext="'Trapping System register accesses to OS-related debug registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEICAABI" browsertext="'Trapping general System register accesses to debug registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDJICAB" browsertext="'Traps to EL3 of all System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDDHIIA" browsertext="'Trapping System register accesses to OS-related debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDCBEHG" browsertext="'Trapping general System register accesses to debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem></list>
<para><xref linkend="D1BEIEEJIA" browsertext="'Traps to EL2 of Non-secure EL1 and EL0 accesses to the ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1," filename="D_the_aarch64_system_level_programmers_model"/> describes configuration settings for generating exceptions that are reported using EC value <binarynumber>0b001000</binarynumber>.</para>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="CV_24_24" msb="24" lsb="24"/>
<fieldat id="COND_23_20" msb="23" lsb="20"/>
<fieldat id="Opc2_19_17" msb="19" lsb="17"/>
<fieldat id="Opc1_16_14" msb="16" lsb="14"/>
<fieldat id="CRn_13_10" msb="13" lsb="10"/>
<fieldat id="Rt_9_5" msb="9" lsb="5"/>
<fieldat id="CRm_4_1" msb="4" lsb="1"/>
<fieldat id="Direction_0_0" msb="0" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from an MCRR or MRRC access</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="CV_24_24"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CV</field_name>
<field_msb>24</field_msb>
<field_lsb>24</field_lsb>
<field_description order="before">
<para>Condition code valid. Possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The COND field is not valid.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The COND field is valid.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>For exceptions taken from AArch64, CV is set to 1.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content>
</listitem></list>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="COND_23_20"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>COND</field_name>
<field_msb>23</field_msb>
<field_lsb>20</field_lsb>
<field_description order="before">
<para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para>
<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered">
<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content>
</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content>
</listitem></list>
</content>
</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered">
<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content>
</listitem><listitem><content>With the COND value held in the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered">
<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content>
</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content>
</listitem></list>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Opc1_19_16"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Opc1</field_name>
<field_msb>19</field_msb>
<field_lsb>16</field_lsb>
<field_description order="before">
<para>The Opc1 value from the issued instruction.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_15_15"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>15</field_msb>
<field_lsb>15</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="Rt2_14_10"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Rt2</field_name>
<field_msb>14</field_msb>
<field_lsb>10</field_lsb>
<field_description order="before">
<para>The Rt2 value from the issued instruction, the second general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1"/>.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Rt_9_5"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Rt</field_name>
<field_msb>9</field_msb>
<field_lsb>5</field_lsb>
<field_description order="before">
<para>The Rt value from the issued instruction, the first general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1"/>.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="CRm_4_1"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CRm</field_name>
<field_msb>4</field_msb>
<field_lsb>1</field_lsb>
<field_description order="before">
<para>The CRm value from the issued instruction.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Direction_0_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Direction</field_name>
<field_msb>0</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Indicates the direction of the trapped instruction. The possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Write to System register space. MCRR instruction.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Read from System register space. MRRC instruction.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>The following sections describe configuration settings for generating exceptions that are reported using EC value <binarynumber>0b000100</binarynumber>:</para>
<list type="unordered">
<listitem><content><xref linkend="CHDJFHAI" browsertext="'Traps to EL1 of EL0 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDGDIEA" browsertext="'Traps to EL1 of EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="BEICGACA" browsertext="'Traps to EL1 of EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIGHBDF" browsertext="'Traps to EL2 of Non-secure EL1 accesses to virtual memory control registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIDJJAH" browsertext="'General trapping to EL2 of Non-secure EL0 and EL1 accesses to System registers, from AArch32 state only' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="CHDFFCIB" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEICIHGI" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="BEIGCEGJ" browsertext="'Traps to EL2 of EL1 and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDGGBGH" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="BEIHHEIC" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem></list>
<para>The following sections describe configuration settings for generating exceptions that are reported using EC value <binarynumber>0b001100</binarynumber>:</para>
<list type="unordered">
<listitem><content><xref linkend="D1CHDBAICA" browsertext="'Traps to EL1 of EL0 and EL1 System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDIGAJA" browsertext="'Traps to EL1 of EL0 accesses to the Debug Communications Channel (DCC) registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIIHJHA" browsertext="'Traps to EL2 of Non-secure system register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIHBBIC" browsertext="'Trapping System register accesses to Debug ROM registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDJICAB" browsertext="'Traps to EL3 of all System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDDHIIA" browsertext="'Trapping System register accesses to powerdown debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDCBEHG" browsertext="'Trapping general System register accesses to debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem></list>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="CV_24_24" msb="24" lsb="24"/>
<fieldat id="COND_23_20" msb="23" lsb="20"/>
<fieldat id="Opc1_19_16" msb="19" lsb="16"/>
<fieldat id="0_15_15" msb="15" lsb="15"/>
<fieldat id="Rt2_14_10" msb="14" lsb="10"/>
<fieldat id="Rt_9_5" msb="9" lsb="5"/>
<fieldat id="CRm_4_1" msb="4" lsb="1"/>
<fieldat id="Direction_0_0" msb="0" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from an LDC or STC instruction</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="CV_24_24"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CV</field_name>
<field_msb>24</field_msb>
<field_lsb>24</field_lsb>
<field_description order="before">
<para>Condition code valid. Possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The COND field is not valid.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The COND field is valid.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>For exceptions taken from AArch64, CV is set to 1.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content>
</listitem></list>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="COND_23_20"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>COND</field_name>
<field_msb>23</field_msb>
<field_lsb>20</field_lsb>
<field_description order="before">
<para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para>
<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered">
<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content>
</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content>
</listitem></list>
</content>
</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered">
<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content>
</listitem><listitem><content>With the COND value held in the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered">
<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content>
</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content>
</listitem></list>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="imm8_19_12"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>imm8</field_name>
<field_msb>19</field_msb>
<field_lsb>12</field_lsb>
<field_description order="before">
<para>The immediate value from the issued instruction.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_11_10"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>11</field_msb>
<field_lsb>10</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="Rn_9_5"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Rn</field_name>
<field_msb>9</field_msb>
<field_lsb>5</field_lsb>
<field_description order="before">
<para>The Rn value from the issued instruction, the general-purpose register used for the transfer. The reported value gives the AArch64 view of the register. See <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1"/>.</para>
<para>This field is valid only when AM[2] is 0, indicating an immediate form of the LDC or STC instruction. When AM[2] is 1, indicating a literal form of the LDC or STC instruction, this field is <arm-defined-word>UNKNOWN</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Offset_4_4"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Offset</field_name>
<field_msb>4</field_msb>
<field_lsb>4</field_lsb>
<field_description order="before">
<para>Indicates whether the offset is added or subtracted:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Subtract offset.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Add offset.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>This bit corresponds to the U bit in the instruction encoding.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="AM_3_1"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>AM</field_name>
<field_msb>3</field_msb>
<field_lsb>1</field_lsb>
<field_description order="before">
<para>Addressing mode. The permitted values of this field are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b000</field_value>
<field_value_description>
<para>Immediate unindexed.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001</field_value>
<field_value_description>
<para>Immediate post-indexed.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010</field_value>
<field_value_description>
<para>Immediate offset.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011</field_value>
<field_value_description>
<para>Immediate pre-indexed.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b100</field_value>
<field_value_description>
<para>For a trapped STC instruction or a trapped T32 LDC instruction this encoding is reserved.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b110</field_value>
<field_value_description>
<para>For a trapped STC instruction, this encoding is reserved.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>The values <binarynumber>0b101</binarynumber> and <binarynumber>0b111</binarynumber> are reserved. The effect of programming this field to a reserved value is that behavior is <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word>, as described in <xref linkend="CEGFJDFD" browsertext="'Reserved values in AArch64 System registers and translation table entries' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section K1.2.2"/>.</para>
<para>Bit [2] in this subfield indicates the instruction form, immediate or literal.</para>
<para>Bits [1:0] in this subfield correspond to the bits {P, W} in the instruction encoding.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Direction_0_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Direction</field_name>
<field_msb>0</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Indicates the direction of the trapped instruction. The possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Write to memory. STC instruction.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Read from memory. LDC instruction.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>The following sections describe the configuration settings for the traps that are reported using EC value <binarynumber>0b000110</binarynumber>:</para>
<list type="unordered">
<listitem><content><xref linkend="D1CHDIGAJA" browsertext="'Traps to EL1 of EL0 accesses to the Debug Communications Channel (DCC) registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEICAABI" browsertext="'Trapping general System register accesses to debug registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDCBEHG" browsertext="'Trapping general System register accesses to debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem></list>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="CV_24_24" msb="24" lsb="24"/>
<fieldat id="COND_23_20" msb="23" lsb="20"/>
<fieldat id="imm8_19_12" msb="19" lsb="12"/>
<fieldat id="0_11_10" msb="11" lsb="10"/>
<fieldat id="Rn_9_5" msb="9" lsb="5"/>
<fieldat id="Offset_4_4" msb="4" lsb="4"/>
<fieldat id="AM_3_1" msb="3" lsb="1"/>
<fieldat id="Direction_0_0" msb="0" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from an access to SVE, Advanced SIMD or floating-point functionality, resulting from CPACR_EL1.FPEN, CPTR_EL2.FPEN or CPTR_ELx.TFP</fields_instance>
<text_before_fields>
<para>The accesses covered by this trap include:</para>
<list type="unordered">
<listitem><content>Execution of SVE or Advanced SIMD and floating-point instructions.</content>
</listitem><listitem><content>Accesses to the Advanced SIMD and floating-point System registers.</content>
</listitem></list>
<para>For an implementation that does not include either SVE or support for floating-point and Advanced SIMD, the exception is reported using the EC value <binarynumber>0b000000</binarynumber>.</para>
</text_before_fields>
<field
id="CV_24_24"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CV</field_name>
<field_msb>24</field_msb>
<field_lsb>24</field_lsb>
<field_description order="before">
<para>Condition code valid. Possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The COND field is not valid.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The COND field is valid.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>For exceptions taken from AArch64, CV is set to 1.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content>
</listitem></list>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="COND_23_20"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>COND</field_name>
<field_msb>23</field_msb>
<field_lsb>20</field_lsb>
<field_description order="before">
<para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para>
<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered">
<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content>
</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content>
</listitem></list>
</content>
</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered">
<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content>
</listitem><listitem><content>With the COND value held in the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered">
<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content>
</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content>
</listitem></list>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_19_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>19</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<text_after_fields>
<para>The following sections describe the configuration settings for the traps that are reported using EC value <binarynumber>0b000111</binarynumber>:</para>
<list type="unordered">
<listitem><content><xref linkend="D1CHDIAIGC" browsertext="'Traps to EL1 of EL0 and EL1 accesses to SIMD and floating-point functionality' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIBCFGC" browsertext="'General trapping to EL2 of Non-secure accesses to the SIMD and floating-point registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDDGEFI" browsertext="'Traps to EL3 of all accesses to the SIMD and floating-point registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/></content>
</listitem></list>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="CV_24_24" msb="24" lsb="24"/>
<fieldat id="COND_23_20" msb="23" lsb="20"/>
<fieldat id="0_19_0" msb="19" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from an access to SVE functionality, resulting from CPACR_EL1.ZEN, CPTR_EL2.ZEN, CPTR_EL2.TZ, or CPTR_EL3.EZ</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_0_1"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
<fields_condition>When SVE is implemented</fields_condition>
</field>
<field
id="0_24_0_2"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<text_after_fields>
<para>The accesses covered by this trap include:</para>
<list type="unordered">
<listitem><content>Execution of SVE instructions.</content>
</listitem><listitem><content>Accesses to the SVE system registers, ZCR_ELx and ID_AA64ZFR0_EL1.</content>
</listitem></list>
<para>For an implementation that does not include SVE, the exception is reported using the EC value <binarynumber>0b000000</binarynumber>.</para>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_0_1" msb="24" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from an Illegal Execution state, or a PC or SP alignment fault</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<text_after_fields>
<para>There are no configuration settings for generating Illegal Execution state exceptions and PC alignment fault exceptions. For more information about these exceptions see <xref linkend="CHDGFFFA" browsertext="'The Illegal Execution state exception' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/> and <xref linkend="BEIFHIFH" browsertext="'PC alignment checking' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</para>
<para><xref linkend="BEIHDCIE" browsertext="'Stack pointer alignment checking' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/> describes the configuration settings for generating SP alignment fault exceptions.</para>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_0" msb="24" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from HVC or SVC instruction execution</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_16"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>16</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="imm16_15_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>imm16</field_name>
<field_msb>15</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>The value of the immediate field from the HVC or SVC instruction.</para>
<para>For an HVC instruction, and for an A64 SVC instruction, this is the value of the imm16 field of the issued instruction.</para>
<para>For an A32 or T32 SVC instruction:</para>
<list type="unordered">
<listitem><content>If the instruction is unconditional, then:<list type="unordered">
<listitem><content>For the T32 instruction, this field is zero-extended from the imm8 field of the instruction.</content>
</listitem><listitem><content>For the A32 instruction, this field is the bottom 16 bits of the imm24 field of the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>If the instruction is conditional, this field is <arm-defined-word>UNKNOWN</arm-defined-word>.</content>
</listitem></list>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>In AArch32 state, the HVC instruction is unconditional, and a conditional SVC instruction generates an exception only if it passes its condition code check. Therefore, the syndrome information for these exceptions does not require conditionality information.</para>
<para>For T32 and A32 instructions, see <xref linkend="A32T32-base.instructions.SVC" browsertext="'SVC' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section F7 (T32 and A32 Base Instruction Set Instruction Descriptions)" filename="F_t32_a32_base_instruction_descriptions"/> and <xref linkend="A32T32-base.instructions.HVC" browsertext="'HVC' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section F7" filename="F_t32_a32_base_instruction_descriptions"/>.</para>
<para>For A64 instructions, see <xref linkend="A64.instructions.SVC" browsertext="'SVC' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section C5 (A64 Base Instruction Descriptions)," filename="C_a64_base_instruction_descriptions"/> and <xref linkend="A64.instructions.HVC" browsertext="'HVC' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section C5" filename="C_a64_base_instruction_descriptions"/>.</para>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_16" msb="24" lsb="16"/>
<fieldat id="imm16_15_0" msb="15" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from SMC instruction execution in AArch32 state</fields_instance>
<text_before_fields>
<para>For an SMC instruction that completes normally and generates an exception that is taken to EL3, the ISS encoding is <arm-defined-word>RES0</arm-defined-word>.</para>
<para>For an SMC instruction that is trapped to EL2 from EL1 because <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.TSC is 1, the ISS encoding is as shown in the diagram.</para>
</text_before_fields>
<field
id="CV_24_24"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CV</field_name>
<field_msb>24</field_msb>
<field_lsb>24</field_lsb>
<field_description order="before">
<para>Condition code valid. Possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The COND field is not valid.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The COND field is valid.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>For exceptions taken from AArch64, CV is set to 1.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1.</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether CV is set to 1 or set to 0. See the description of the COND field for more information.</content>
</listitem></list>
<para>This field is only valid if CCKNOWNPASS is 1, otherwise it is <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="COND_23_20"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>COND</field_name>
<field_msb>23</field_msb>
<field_lsb>20</field_lsb>
<field_description order="before">
<para>The condition code for the trapped instruction. This field is valid only for exceptions taken from AArch32, and only when the value of CV is 1.</para>
<para>For exceptions taken from AArch64, this field is set to <binarynumber>0b1110</binarynumber>.</para>
<para>For exceptions taken from AArch32:</para>
<list type="unordered">
<listitem><content>When an A32 instruction is trapped, CV is set to 1 and:<list type="unordered">
<listitem><content>If the instruction is conditional, COND is set to the condition code field value from the instruction.</content>
</listitem><listitem><content>If the instruction is unconditional, COND is set to <binarynumber>0b1110</binarynumber>.</content>
</listitem></list>
</content>
</listitem><listitem><content>A conditional A32 instruction that is known to pass its condition code check can be presented either:<list type="unordered">
<listitem><content>With COND set to <binarynumber>0b1110</binarynumber>, the value for unconditional.</content>
</listitem><listitem><content>With the COND value held in the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>When a T32 instruction is trapped, it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether:<list type="unordered">
<listitem><content>CV is set to 0 and COND is set to an <arm-defined-word>UNKNOWN</arm-defined-word> value. Software must examine the SPSR.IT field to determine the condition, if any, of the T32 instruction.</content>
</listitem><listitem><content>CV is set to 1 and COND is set to the condition code for the condition that applied to the instruction.</content>
</listitem></list>
</content>
</listitem><listitem><content>For an implementation that, for both A32 and T32 instructions, takes an exception on a trapped conditional instruction only if the instruction passes its condition code check, these definitions mean that when CV is set to 1 it is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether the COND field is set to <binarynumber>0b1110</binarynumber>, or to the value of any condition that applied to the instruction.</content>
</listitem></list>
<para>This field is only valid if CCKNOWNPASS is 1, otherwise it is <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="CCKNOWNPASS_19_19"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CCKNOWNPASS</field_name>
<field_msb>19</field_msb>
<field_lsb>19</field_lsb>
<field_description order="before">
<para>Indicates whether the instruction might have failed its condition code check.</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The instruction was unconditional, or was conditional and passed its condition code check.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The instruction was conditional, and might have failed its condition code check.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<note><para>In an implementation in which an SMC instruction that fails it code check is not trapped, this field can always return the value 0.</para></note>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_18_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>18</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<text_after_fields>
<para><xref linkend="BEIGGFEI" browsertext="'Traps to EL2 of Non-secure EL1 execution of SMC instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)," filename="D_the_aarch64_system_level_programmers_model"/> describes the configuration settings for trapping SMC instructions from EL1 modes, and <xref linkend="BEIBEAGE" browsertext="'System calls' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.16," filename="D_the_aarch64_system_level_programmers_model"/> describes the case where these exceptions are trapped to EL3.</para>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="CV_24_24" msb="24" lsb="24"/>
<fieldat id="COND_23_20" msb="23" lsb="20"/>
<fieldat id="CCKNOWNPASS_19_19" msb="19" lsb="19"/>
<fieldat id="0_18_0" msb="18" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from SMC instruction execution in AArch64 state</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_16"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>16</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="imm16_15_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>imm16</field_name>
<field_msb>15</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>The value of the immediate field from the issued SMC instruction.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>The value of ISS[24:0] described here is used both:</para>
<list type="unordered">
<listitem><content>When an SMC instruction is trapped from EL1 modes.</content>
</listitem><listitem><content>When an SMC instruction is not trapped, so completes normally and generates an exception that is taken to EL3.</content>
</listitem></list>
<para><xref linkend="BEIGGFEI" browsertext="'Traps to EL2 of Non-secure EL1 execution of SMC instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)," filename="D_the_aarch64_system_level_programmers_model"/> describes the configuration settings for trapping SMC instructions from Non-secure EL1 modes, and <xref linkend="BEIBEAGE" browsertext="'System calls' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.16," filename="D_the_aarch64_system_level_programmers_model"/> describes the case where these exceptions are trapped to EL3.</para>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_16" msb="24" lsb="16"/>
<fieldat id="imm16_15_0" msb="15" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from MSR, MRS, or System instruction execution in AArch64 state</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_22"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>22</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="Op0_21_20"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Op0</field_name>
<field_msb>21</field_msb>
<field_lsb>20</field_lsb>
<field_description order="before">
<para>The Op0 value from the issued instruction.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Op2_19_17"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Op2</field_name>
<field_msb>19</field_msb>
<field_lsb>17</field_lsb>
<field_description order="before">
<para>The Op2 value from the issued instruction.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Op1_16_14"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Op1</field_name>
<field_msb>16</field_msb>
<field_lsb>14</field_lsb>
<field_description order="before">
<para>The Op1 value from the issued instruction.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="CRn_13_10"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CRn</field_name>
<field_msb>13</field_msb>
<field_lsb>10</field_lsb>
<field_description order="before">
<para>The CRn value from the issued instruction.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Rt_9_5"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Rt</field_name>
<field_msb>9</field_msb>
<field_lsb>5</field_lsb>
<field_description order="before">
<para>The Rt value from the issued instruction, the general-purpose register used for the transfer.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="CRm_4_1"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CRm</field_name>
<field_msb>4</field_msb>
<field_lsb>1</field_lsb>
<field_description order="before">
<para>The CRm value from the issued instruction.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="Direction_0_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Direction</field_name>
<field_msb>0</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Indicates the direction of the trapped instruction. The possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Write access, including MSR instructions.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Read access, including MRS instructions.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>For exceptions caused by System instructions, see <xref linkend="A64.encoding_index.system" browsertext="the 'System' subsection of 'Branches, exception generating and System instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section C3 (A64 Instruction Set Encoding)," filename="C_a64_instruction_set_encoding"/> for the encoding values returned by an instruction.</para>
<para>The following sections describe configuration settings for generating the exception that is reported using EC value <binarynumber>0b011000</binarynumber>:</para>
<list type="unordered">
<listitem><content>In <xref linkend="D1BABDIIDI" browsertext="'EL1 configurable controls' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.<list type="unordered">
<listitem><content><xref linkend="CHDCDIIJ" browsertext="'Traps to EL1 of EL0 execution of cache maintenance instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDEIDGH" browsertext="'Traps to EL1 of EL0 accesses to the CTR_EL0' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDCDHJA" browsertext="'Traps to EL1 of EL0 execution of DC ZVA instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDHABAB" browsertext="'Traps to EL1 of EL0 accesses to the PSTATE.{D, A, I, F} interrupt masks' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1(The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDBAICA" browsertext="'Traps to EL1 of EL0 and EL1 System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDIGAJA" browsertext="'Traps to EL1 of EL0 accesses to the Debug Communications Channel (DCC) registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="CHDJFHAI" browsertext="'Traps to EL1 of EL0 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDGDIEA" browsertext="'Traps to EL1 of EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="BEICGACA" browsertext="'Traps to EL1 of EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem></list>
</content>
</listitem><listitem><content>In <xref linkend="D1BABBABAG" browsertext="'EL2 configurable controls' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.<list type="unordered">
<listitem><content><xref linkend="D1BEIGHBDF" browsertext="'Traps to EL2 of Non-secure EL1 accesses to virtual memory control registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="CHDEHBGG" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 execution of DC ZVA instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEICAEBH" browsertext="'Traps to EL2 of Non-secure EL1 execution of TLB maintenance instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEICHIHA" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 execution of cache maintenance instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIFCHFF" browsertext="'Traps to EL2 of Non-secure EL1 accesses to the Auxiliary Control Register' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="BEIDHFBB" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to lockdown, DMA, and TCM operations' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIEEJIA" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to the ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIFFJII" browsertext="'Trapping to EL2 of Non-secure EL1 accesses to the CPACR_EL1 or CPACR' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIIHJHA" browsertext="'Traps to EL2 of Non-secure system register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIHBBIC" browsertext="'Trapping System register accesses to Debug ROM registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEIECEGJ" browsertext="'Trapping System register accesses to OS-related debug registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="CHDFFCIB" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to the Generic Timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEICAABI" browsertext="'Trapping general System register accesses to debug registers to EL2' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1BEICIHGI" browsertext="'Traps to EL2 of Non-secure EL0 and EL1 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="BEIGCEGJ" browsertext="'Traps to EL2 of EL1 and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="CHDIAGCG" browsertext="'Trap to EL2 Non-secure EL1 accesses to Pointer authentication key registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="CHDCFJDF" browsertext="'Traps to EL2 for Nested virtualization' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="CHDIJFAH" browsertext="'Trap to EL2 Non-secure EL1 accesses to AT S1E* instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="CHDFBJDH" browsertext="'Trap to EL3 accesses to Pointer authentication key registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem></list>
</content>
</listitem><listitem><content>In <xref linkend="D1BABCFDGA" browsertext="'EL3 configurable controls' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.<list type="unordered">
<listitem><content><xref linkend="CHDHAJBA" browsertext="'Traps to EL3 of Secure EL1 accesses to the Counter-timer Physical Secure timer registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDJACCE" browsertext="'Trapping to EL3 of EL2 accesses to the CPTR_EL2 or HCPTR, and EL2 and EL1 accesses to the CPACR_EL1 or CPACR' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDJICAB" browsertext="'Traps to EL3 of all System register accesses to the trace registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDDHIIA" browsertext="'Trapping System register accesses to OS-related debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDCBEHG" browsertext="'Trapping general System register accesses to debug registers to EL3' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="D1CHDGGBGH" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Performance Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="BEIHHEIC" browsertext="'Traps to EL3 of EL2, EL1, and EL0 accesses to Activity Monitors registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1 (The AArch64 System Level Programmers' Model)" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem></list>
</content>
</listitem></list>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_22" msb="24" lsb="22"/>
<fieldat id="Op0_21_20" msb="21" lsb="20"/>
<fieldat id="Op2_19_17" msb="19" lsb="17"/>
<fieldat id="Op1_16_14" msb="16" lsb="14"/>
<fieldat id="CRn_13_10" msb="13" lsb="10"/>
<fieldat id="Rt_9_5" msb="9" lsb="5"/>
<fieldat id="CRm_4_1" msb="4" lsb="1"/>
<fieldat id="Direction_0_0" msb="0" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>IMPLEMENTATION DEFINED exception to EL3</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="IMPLEMENTATION DEFINED_24_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>IMPLEMENTATION DEFINED</field_name>
<field_msb>24</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para><arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para>
</field_description>
<field_values>
<field_value_name>I</field_value_name>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="IMPLEMENTATION DEFINED_24_0" msb="24" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from an Instruction Abort</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_13"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>13</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="SET_12_11"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>SET</field_name>
<field_msb>12</field_msb>
<field_lsb>11</field_lsb>
<field_description order="before">
<para>Synchronous Error Type. When the RAS Extension is implemented and IFSC is <binarynumber>0b010000</binarynumber>, describes the state of the PE after taking the Instruction Abort exception. The possible values of this field are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b00</field_value>
<field_value_description>
<para>Recoverable error (UER).</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b10</field_value>
<field_value_description>
<para>Uncontainable error (UC).</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b11</field_value>
<field_value_description>
<para>Restartable error (UEO) or Corrected error (CE).</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>All other values are reserved.</para>
<note><para>Software can use this information to determine what recovery might be possible. Taking a synchronous External Abort exception might result in an unrecoverable PE state.</para></note><para>This field is <arm-defined-word>RES0</arm-defined-word> if either:</para>
<list type="unordered">
<listitem><content>The RAS Extension is not implemented.</content>
</listitem><listitem><content>The value returned in the IFSC field is not <binarynumber>0b010000</binarynumber>.</content>
</listitem></list>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="FnV_10_10"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>FnV</field_name>
<field_msb>10</field_msb>
<field_lsb>10</field_lsb>
<field_description order="before">
<para>FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>FAR is valid.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>FAR is not valid, and holds an <arm-defined-word>UNKNOWN</arm-defined-word> value.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>This field is only valid if the IFSC code is <binarynumber>0b010000</binarynumber>. It is <arm-defined-word>RES0</arm-defined-word> for all other aborts.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="EA_9_9"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>EA</field_name>
<field_msb>9</field_msb>
<field_lsb>9</field_lsb>
<field_description order="before">
<para>External abort type. This bit can provide an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> classification of External aborts.</para>
<para>For any abort other than an External abort this bit returns a value of 0.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_8_8"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>8</field_msb>
<field_lsb>8</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="S1PTW_7_7"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>S1PTW</field_name>
<field_msb>7</field_msb>
<field_lsb>7</field_lsb>
<field_description order="before">
<para>For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1 translation table walk:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Fault not on a stage 2 translation for a stage 1 translation table walk.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Fault on the stage 2 translation of an access for a stage 1 translation table walk.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>For any abort other than a stage 2 fault this bit is <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_6_6"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>6</field_msb>
<field_lsb>6</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="IFSC_5_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>IFSC</field_name>
<field_msb>5</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Instruction Fault Status Code. Possible values of this field are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b000000</field_value>
<field_value_description>
<para>Address size fault, level 0 of translation or translation table base register</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000001</field_value>
<field_value_description>
<para>Address size fault, level 1</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000010</field_value>
<field_value_description>
<para>Address size fault, level 2</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000011</field_value>
<field_value_description>
<para>Address size fault, level 3</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000100</field_value>
<field_value_description>
<para>Translation fault, level 0</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000101</field_value>
<field_value_description>
<para>Translation fault, level 1</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000110</field_value>
<field_value_description>
<para>Translation fault, level 2</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000111</field_value>
<field_value_description>
<para>Translation fault, level 3</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001001</field_value>
<field_value_description>
<para>Access flag fault, level 1</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001010</field_value>
<field_value_description>
<para>Access flag fault, level 2</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001011</field_value>
<field_value_description>
<para>Access flag fault, level 3</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001101</field_value>
<field_value_description>
<para>Permission fault, level 1</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001110</field_value>
<field_value_description>
<para>Permission fault, level 2</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001111</field_value>
<field_value_description>
<para>Permission fault, level 3</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010000</field_value>
<field_value_description>
<para>Synchronous External abort, not on translation table walk</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010100</field_value>
<field_value_description>
<para>Synchronous External abort, on translation table walk, level 0</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010101</field_value>
<field_value_description>
<para>Synchronous External abort, on translation table walk, level 1</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010110</field_value>
<field_value_description>
<para>Synchronous External abort, on translation table walk, level 2</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010111</field_value>
<field_value_description>
<para>Synchronous External abort, on translation table walk, level 3</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011000</field_value>
<field_value_description>
<para>Synchronous parity or ECC error on memory access, not on translation table walk</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011100</field_value>
<field_value_description>
<para>Synchronous parity or ECC error on memory access on translation table walk, level 0</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011101</field_value>
<field_value_description>
<para>Synchronous parity or ECC error on memory access on translation table walk, level 1</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011110</field_value>
<field_value_description>
<para>Synchronous parity or ECC error on memory access on translation table walk, level 2</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011111</field_value>
<field_value_description>
<para>Synchronous parity or ECC error on memory access on translation table walk, level 3</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b110000</field_value>
<field_value_description>
<para>TLB conflict abort</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b110001</field_value>
<field_value_description>
<para>Unsupported atomic hardware update fault, if the implementation includes <xref browsertext="ARMv8.1-TTHM]" filename="A_introduction_to_the_armv8_architecture.fm" linkend="v8.1.TTHM"></xref>. Otherwise reserved.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>All other values are reserved.</para>
<para>When the RAS Extension is implemented, <binarynumber>0b011000</binarynumber>, <binarynumber>0b011100</binarynumber>, <binarynumber>0b011101</binarynumber>, <binarynumber>0b011110</binarynumber>, and <binarynumber>0b011111</binarynumber>, are reserved.</para>
<note><para>Armv8.2 requires the implementation of the RAS Extension.</para></note><para>For more information about the lookup level associated with a fault, see <xref linkend="CACDHEEH" browsertext="'The level associated with MMU faults' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile"/>.</para>
<note><para>Because Access flag faults and Permission faults can only result from a Block or Page translation table descriptor, they cannot occur at level 0.</para></note><para>If the S1PTW bit is set, then the level refers the level of the stage2 translation that is translating a stage 1 translation walk.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_13" msb="24" lsb="13"/>
<fieldat id="SET_12_11" msb="12" lsb="11"/>
<fieldat id="FnV_10_10" msb="10" lsb="10"/>
<fieldat id="EA_9_9" msb="9" lsb="9"/>
<fieldat id="0_8_8" msb="8" lsb="8"/>
<fieldat id="S1PTW_7_7" msb="7" lsb="7"/>
<fieldat id="0_6_6" msb="6" lsb="6"/>
<fieldat id="IFSC_5_0" msb="5" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from a Data Abort</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="ISV_24_24"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>ISV</field_name>
<field_msb>24</field_msb>
<field_lsb>24</field_lsb>
<field_description order="before">
<para>Instruction syndrome valid. Indicates whether the syndrome information in ISS[23:0] is valid.</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>No valid instruction syndrome. ISS[23:14] are <arm-defined-word>RES0</arm-defined-word>.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>ISS[23:14] hold a valid instruction syndrome.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>This bit is 0 for all faults reported in ESR_EL2 except the following stage 2 aborts:</para>
<list type="unordered">
<listitem><content>AArch64 loads and stores of a single general-purpose register (including the register specified with <binarynumber>0b11111</binarynumber>, including those with Acquire/Release semantics, but excluding Load Exclusive or Store Exclusive and excluding those with writeback.</content>
</listitem><listitem><content>AArch32 instructions where the instruction:<list type="unordered">
<listitem><content>Is an LDR, LDA, LDRT, LDRSH, LDRSHT, LDRH, LDAH, LDRHT, LDRSB, LDRSBT, LDRB, LDAB, LDRBT, STR, STL, STRT, STRH, STLH, STRHT, STRB, STLB, or STRBT instruction.</content>
</listitem><listitem><content>Is not performing register writeback.</content>
</listitem><listitem><content>Is not using R15 as a source or destination register.</content>
</listitem></list>
</content>
</listitem></list>
<para>For these cases, ISV is <arm-defined-word>UNKNOWN</arm-defined-word> if the exception was generated in Debug state in memory access mode, and otherwise indicates whether ISS[23:14] hold a valid syndrome.</para>
<para>ISV is 0 for all faults reported in ESR_EL1 or ESR_EL3.</para>
<para>When the RAS Extension is implemented, ISV is 0 for any synchronous External abort.</para>
<para>For ISS reporting, a stage 2 abort on a stage 1 translation table walk does not return a valid instruction syndrome, and therefore ISV is 0 for these aborts.</para>
<para>When the RAS Extension is not implemented, the value of ISV on a synchronous External abort on a stage 2 translation table walk is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word>.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="SAS_23_22"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>SAS</field_name>
<field_msb>23</field_msb>
<field_lsb>22</field_lsb>
<field_description order="before">
<para>Syndrome Access Size. When ISV is 1, indicates the size of the access attempted by the faulting operation.</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b00</field_value>
<field_value_description>
<para>Byte</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b01</field_value>
<field_value_description>
<para>Halfword</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b10</field_value>
<field_value_description>
<para>Word</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b11</field_value>
<field_value_description>
<para>Doubleword</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> when the value of ISV is <arm-defined-word>UNKNOWN</arm-defined-word>.</para>
<para>This field is <arm-defined-word>RES0</arm-defined-word> when the value of ISV is 0.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="SSE_21_21"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>SSE</field_name>
<field_msb>21</field_msb>
<field_lsb>21</field_lsb>
<field_description order="before">
<para>Syndrome Sign Extend. When ISV is 1, for a byte, halfword, or word load operation, indicates whether the data item must be sign extended. For these cases, the possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Sign-extension not required.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Data item must be sign-extended.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>For all other operations this bit is 0.</para>
<para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> when the value of ISV is <arm-defined-word>UNKNOWN</arm-defined-word>.</para>
<para>This field is <arm-defined-word>RES0</arm-defined-word> when the value of ISV is 0.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="SRT_20_16"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>SRT</field_name>
<field_msb>20</field_msb>
<field_lsb>16</field_lsb>
<field_description order="before">
<para>Syndrome Register transfer. When ISV is 1, the register number of the Rt operand of the faulting instruction. If the exception was taken from an Exception level that is using AArch32 then this is the AArch64 view of the register. See <xref linkend="BEIDFCCE" browsertext="'Mapping of the general-purpose registers between the Execution states' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.20.1"/>.</para>
<para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> when the value of ISV is <arm-defined-word>UNKNOWN</arm-defined-word>.</para>
<para>This field is <arm-defined-word>RES0</arm-defined-word> when the value of ISV is 0.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="SF_15_15"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>SF</field_name>
<field_msb>15</field_msb>
<field_lsb>15</field_lsb>
<field_description order="before">
<para>Width of the register accessed by the instruction is Sixty-Four. When ISV is 1, the possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Instruction loads/stores a 32-bit wide register.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Instruction loads/stores a 64-bit wide register.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<note><para>This field specifies the register width identified by the instruction, not the Execution state.</para></note><para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> when the value of ISV is <arm-defined-word>UNKNOWN</arm-defined-word>.</para>
<para>This field is <arm-defined-word>RES0</arm-defined-word> when the value of ISV is 0.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="AR_14_14"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>AR</field_name>
<field_msb>14</field_msb>
<field_lsb>14</field_lsb>
<field_description order="before">
<para>Acquire/Release. When ISV is 1, the possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Instruction did not have acquire/release semantics.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Instruction did have acquire/release semantics.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> when the value of ISV is <arm-defined-word>UNKNOWN</arm-defined-word>.</para>
<para>This field is <arm-defined-word>RES0</arm-defined-word> when the value of ISV is 0.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="VNCR_13_13_1"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>VNCR</field_name>
<field_msb>13</field_msb>
<field_lsb>13</field_lsb>
<field_description order="before">
<para>Indicates that the fault came from use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link> register by EL1 code.</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The fault was not generated by the use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link>, by an MRS or MSR instruction executed at EL1.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The fault was generated by the use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link>, by an MRS or MSR instruction executed at EL1.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>This field is 0 in ESR_EL1.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
<fields_condition>When ARMv8.4-NV is implemented</fields_condition>
</field>
<field
id="0_13_13_2"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>13</field_msb>
<field_lsb>13</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="SET_12_11"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>SET</field_name>
<field_msb>12</field_msb>
<field_lsb>11</field_lsb>
<field_description order="before">
<para>Synchronous Error Type. When the RAS Extension is implemented and DFSC is <binarynumber>0b010000</binarynumber>, describes the state of the PE after taking the Data Abort exception. The possible values of this field are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b00</field_value>
<field_value_description>
<para>Recoverable error (UER).</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b10</field_value>
<field_value_description>
<para>Uncontainable error (UC).</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b11</field_value>
<field_value_description>
<para>Restartable error (UEO) or Corrected error (CE).</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>All other values are reserved.</para>
<note><para>Software can use this information to determine what recovery might be possible. Taking a synchronous External Abort exception might result in an unrecoverable PE state.</para></note><para>This field is <arm-defined-word>RES0</arm-defined-word> if either:</para>
<list type="unordered">
<listitem><content>The RAS Extension is not implemented.</content>
</listitem><listitem><content>The value returned in the DFSC field is not <binarynumber>0b010000</binarynumber>.</content>
</listitem></list>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="FnV_10_10"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>FnV</field_name>
<field_msb>10</field_msb>
<field_lsb>10</field_lsb>
<field_description order="before">
<para>FAR not Valid, for a synchronous External abort other than a synchronous External abort on a translation table walk.</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>FAR is valid.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>FAR is not valid, and holds an <arm-defined-word>UNKNOWN</arm-defined-word> value.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>This field is valid only if the DFSC code is <binarynumber>0b010000</binarynumber>. It is <arm-defined-word>RES0</arm-defined-word> for all other aborts.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="EA_9_9"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>EA</field_name>
<field_msb>9</field_msb>
<field_lsb>9</field_lsb>
<field_description order="before">
<para>External abort type. This bit can provide an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> classification of External aborts.</para>
<para>For any abort other than an External abort this bit returns a value of 0.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="CM_8_8"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CM</field_name>
<field_msb>8</field_msb>
<field_lsb>8</field_lsb>
<field_description order="before">
<para>Cache maintenance. Indicates whether the Data Abort came from a cache maintenance or address translation instruction:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The Data Abort was not generated by the execution of one of the System instructions identified in the description of value 1.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The Data Abort was generated by either the execution of a cache maintenance instruction or by a synchronous fault on the execution of an address translation instruction. The <register_link id="AArch64-dc-zva.xml" state="AArch64">DC ZVA</register_link> instruction is not classified as a cache maintenance instruction, and therefore its execution cannot cause this field to be set to 1.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="S1PTW_7_7"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>S1PTW</field_name>
<field_msb>7</field_msb>
<field_lsb>7</field_lsb>
<field_description order="before">
<para>For a stage 2 fault, indicates whether the fault was a stage 2 fault on an access made for a stage 1 translation table walk:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Fault not on a stage 2 translation for a stage 1 translation table walk.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Fault on the stage 2 translation of an access for a stage 1 translation table walk.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>For any abort other than a stage 2 fault this bit is <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="WnR_6_6"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>WnR</field_name>
<field_msb>6</field_msb>
<field_lsb>6</field_lsb>
<field_description order="before">
<para>Write not Read. Indicates whether a synchronous abort was caused by an instruction writing to a memory location, or by an instruction reading from a memory location. The possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Abort caused by an instruction reading from a memory location.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Abort caused by an instruction writing to a memory location.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>For faults on cache maintenance and address translation instructions, this bit always returns a value of 1.</para>
<para>For faults from an atomic instruction that both reads and writes from a memory location, this bit is set to 0 if a read of the address specified by the instruction would have generated the fault which is being reported, otherwise it is set to 1. The architecture permits, but does not require, a relaxation of this requirement such that for all stage 2 aborts on stage 1 translation table walks for atomic instructions, the WnR bit is always 0.</para>
<para>This field is <arm-defined-word>UNKNOWN</arm-defined-word> for:</para>
<list type="unordered">
<listitem><content>An External abort on an Atomic access.</content>
</listitem><listitem><content>A fault reported using a DFSC value of <binarynumber>0b110101</binarynumber> or <binarynumber>0b110001</binarynumber>, indicating an unsupported Exclusive or atomic access.</content>
</listitem></list>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="DFSC_5_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>DFSC</field_name>
<field_msb>5</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Data Fault Status Code. Possible values of this field are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b000000</field_value>
<field_value_description>
<para>Address size fault, level 0 of translation or translation table base register.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000001</field_value>
<field_value_description>
<para>Address size fault, level 1.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000010</field_value>
<field_value_description>
<para>Address size fault, level 2.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000011</field_value>
<field_value_description>
<para>Address size fault, level 3.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000100</field_value>
<field_value_description>
<para>Translation fault, level 0.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000101</field_value>
<field_value_description>
<para>Translation fault, level 1.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000110</field_value>
<field_value_description>
<para>Translation fault, level 2.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b000111</field_value>
<field_value_description>
<para>Translation fault, level 3.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001001</field_value>
<field_value_description>
<para>Access flag fault, level 1.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001010</field_value>
<field_value_description>
<para>Access flag fault, level 2.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001011</field_value>
<field_value_description>
<para>Access flag fault, level 3.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001101</field_value>
<field_value_description>
<para>Permission fault, level 1.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001110</field_value>
<field_value_description>
<para>Permission fault, level 2.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001111</field_value>
<field_value_description>
<para>Permission fault, level 3.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010000</field_value>
<field_value_description>
<para>Synchronous External abort, not on translation table walk.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010001</field_value>
<field_value_description>
<para>Synchronous Tag Check fail</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010100</field_value>
<field_value_description>
<para>Synchronous External abort, on translation table walk, level 0.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010101</field_value>
<field_value_description>
<para>Synchronous External abort, on translation table walk, level 1.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010110</field_value>
<field_value_description>
<para>Synchronous External abort, on translation table walk, level 2.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010111</field_value>
<field_value_description>
<para>Synchronous External abort, on translation table walk, level 3.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011000</field_value>
<field_value_description>
<para>Synchronous parity or ECC error on memory access, not on translation table walk.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011100</field_value>
<field_value_description>
<para>Synchronous parity or ECC error on memory access on translation table walk, level 0.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011101</field_value>
<field_value_description>
<para>Synchronous parity or ECC error on memory access on translation table walk, level 1.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011110</field_value>
<field_value_description>
<para>Synchronous parity or ECC error on memory access on translation table walk, level 2.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011111</field_value>
<field_value_description>
<para>Synchronous parity or ECC error on memory access on translation table walk, level 3.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b100001</field_value>
<field_value_description>
<para>Alignment fault.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b110000</field_value>
<field_value_description>
<para>TLB conflict abort.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b110001</field_value>
<field_value_description>
<para>Unsupported atomic hardware update fault, if the implementation includes <xref browsertext="ARMv8.1-TTHM]" filename="A_introduction_to_the_armv8_architecture.fm" linkend="v8.1.TTHM"></xref>. Otherwise reserved.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b110100</field_value>
<field_value_description>
<para><arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> fault (Lockdown).</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b110101</field_value>
<field_value_description>
<para><arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> fault (Unsupported Exclusive or Atomic access).</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b111101</field_value>
<field_value_description>
<para>Section Domain Fault, used only for faults reported in the <register_link state="AArch64" id="AArch64-par_el1.xml">PAR_EL1</register_link>.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b111110</field_value>
<field_value_description>
<para>Page Domain Fault, used only for faults reported in the <register_link state="AArch64" id="AArch64-par_el1.xml">PAR_EL1</register_link>.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>All other values are reserved.</para>
<para>When the RAS Extension is implemented, <binarynumber>0b011000</binarynumber>, <binarynumber>0b011100</binarynumber>, <binarynumber>0b011101</binarynumber>, <binarynumber>0b011110</binarynumber>, and <binarynumber>0b011111</binarynumber>, are reserved.</para>
<para>For more information about the lookup level associated with a fault, see <xref linkend="CACDHEEH" browsertext="'The level associated with MMU faults' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile"/>.</para>
<note><para>Because Access flag faults and Permission faults can only result from a Block or Page translation table descriptor, they cannot occur at level 0.</para></note><para>If the S1PTW bit is set, then the level refers the level of the stage2 translation that is translating a stage 1 translation walk.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="ISV_24_24" msb="24" lsb="24"/>
<fieldat id="SAS_23_22" msb="23" lsb="22"/>
<fieldat id="SSE_21_21" msb="21" lsb="21"/>
<fieldat id="SRT_20_16" msb="20" lsb="16"/>
<fieldat id="SF_15_15" msb="15" lsb="15"/>
<fieldat id="AR_14_14" msb="14" lsb="14"/>
<fieldat id="VNCR_13_13_1" msb="13" lsb="13"/>
<fieldat id="SET_12_11" msb="12" lsb="11"/>
<fieldat id="FnV_10_10" msb="10" lsb="10"/>
<fieldat id="EA_9_9" msb="9" lsb="9"/>
<fieldat id="CM_8_8" msb="8" lsb="8"/>
<fieldat id="S1PTW_7_7" msb="7" lsb="7"/>
<fieldat id="WnR_6_6" msb="6" lsb="6"/>
<fieldat id="DFSC_5_0" msb="5" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from a trapped floating-point exception</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_24"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>24</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="TFV_23_23"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>TFV</field_name>
<field_msb>23</field_msb>
<field_lsb>23</field_lsb>
<field_description order="before">
<para>Trapped Fault Valid bit. Indicates whether the IDF, IXF, UFF, OFF, DZF, and IOF bits hold valid information about trapped floating-point exceptions. The possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The IDF, IXF, UFF, OFF, DZF, and IOF bits do not hold valid information about trapped floating-point exceptions and are <arm-defined-word>UNKNOWN</arm-defined-word>.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>One or more floating-point exceptions occurred during an operation performed while executing the reported instruction. The IDF, IXF, UFF, OFF, DZF, and IOF bits indicate trapped floating-point exceptions that occurred. For more information see <xref linkend="BEIJDDAG" browsertext="'Floating-point exception traps' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1.13.4"/>.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>It is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> whether this field is set to 0 on an exception generated by a trapped floating point exception from a vector instruction.</para>
<note><para>This is not a requirement. Implementations can set this field to 1 on a trapped floating-point exception from a vector instruction and return valid information in the {IDF, IXF, UFF, OFF, DZF, IOF} fields.</para></note>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_22_11"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>22</field_msb>
<field_lsb>11</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="VECITR_10_8"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>VECITR</field_name>
<field_msb>10</field_msb>
<field_lsb>8</field_lsb>
<field_description order="before">
<para>For a trapped floating-point exception from an instruction executed in AArch32 state this field is <arm-defined-word>RES1</arm-defined-word>.</para>
<para>For a trapped floating-point exception from an instruction executed in AArch64 state this field is <arm-defined-word>UNKNOWN</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="IDF_7_7"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>IDF</field_name>
<field_msb>7</field_msb>
<field_lsb>7</field_lsb>
<field_description order="before">
<para>Input Denormal floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Input denormal floating-point exception has not occurred.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Input denormal floating-point exception occurred during execution of the reported instruction.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_6_5"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>6</field_msb>
<field_lsb>5</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="IXF_4_4"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>IXF</field_name>
<field_msb>4</field_msb>
<field_lsb>4</field_lsb>
<field_description order="before">
<para>Inexact floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Inexact floating-point exception has not occurred.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Inexact floating-point exception occurred during execution of the reported instruction.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="UFF_3_3"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>UFF</field_name>
<field_msb>3</field_msb>
<field_lsb>3</field_lsb>
<field_description order="before">
<para>Underflow floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Underflow floating-point exception has not occurred.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Underflow floating-point exception occurred during execution of the reported instruction.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="OFF_2_2"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>OFF</field_name>
<field_msb>2</field_msb>
<field_lsb>2</field_lsb>
<field_description order="before">
<para>Overflow floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Overflow floating-point exception has not occurred.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Overflow floating-point exception occurred during execution of the reported instruction.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="DZF_1_1"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>DZF</field_name>
<field_msb>1</field_msb>
<field_lsb>1</field_lsb>
<field_description order="before">
<para>Divide by Zero floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Divide by Zero floating-point exception has not occurred.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Divide by Zero floating-point exception occurred during execution of the reported instruction.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="IOF_0_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>IOF</field_name>
<field_msb>0</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Invalid Operation floating-point exception trapped bit. If the TFV field is 0, this bit is <arm-defined-word>UNKNOWN</arm-defined-word>. Otherwise, the possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Invalid Operation floating-point exception has not occurred.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Invalid Operation floating-point exception occurred during execution of the reported instruction.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>In an implementation that supports the trapping of floating-point exceptions:</para>
<list type="unordered">
<listitem><content>From an Exception level using AArch64, the <register_link state="AArch64" id="AArch64-fpcr.xml">FPCR</register_link>.{IDE, IXE, UFE, OFE, DZE, IOE} bits enable each of the floating-point exception traps.</content>
</listitem><listitem><content>From an Exception level using AArch32, the <register_link state="AArch32" id="AArch32-fpscr.xml">FPSCR</register_link>.{IDE, IXE, UFE, OFE, DZE, IOE} bits enable each of the floating-point exception traps.</content>
</listitem></list>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_24" msb="24" lsb="24"/>
<fieldat id="TFV_23_23" msb="23" lsb="23"/>
<fieldat id="0_22_11" msb="22" lsb="11"/>
<fieldat id="VECITR_10_8" msb="10" lsb="8"/>
<fieldat id="IDF_7_7" msb="7" lsb="7"/>
<fieldat id="0_6_5" msb="6" lsb="5"/>
<fieldat id="IXF_4_4" msb="4" lsb="4"/>
<fieldat id="UFF_3_3" msb="3" lsb="3"/>
<fieldat id="OFF_2_2" msb="2" lsb="2"/>
<fieldat id="DZF_1_1" msb="1" lsb="1"/>
<fieldat id="IOF_0_0" msb="0" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>SError interrupt</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="IDS_24_24"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>IDS</field_name>
<field_msb>24</field_msb>
<field_lsb>24</field_lsb>
<field_description order="before">
<para><arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> syndrome. Possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Bits[23:0] of the ISS field holds the fields described in this encoding.</para>
<note><para>If the RAS Extension is not implemented, this means that bits[23:0] of the ISS field are <arm-defined-word>RES0</arm-defined-word>.</para></note>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Bits[23:0] of the ISS field holds <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> syndrome information that can be used to provide additional information about the SError interrupt.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<note><para>This field was previously called ISV.</para></note>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_23_14"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>23</field_msb>
<field_lsb>14</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="IESB_13_13_1"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>IESB</field_name>
<field_msb>13</field_msb>
<field_lsb>13</field_lsb>
<field_description order="before">
<para>Implicit error synchronization event.</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The SError interrupt was either not synchronized by the implicit error synchronization event or not taken immediately.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The SError interrupt was synchronized by the implicit error synchronization event and taken immediately.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>This field is <arm-defined-word>RES0</arm-defined-word> if the value returned in the DFSC field is not <binarynumber>0b010001</binarynumber>.</para>
<note><para>Armv8.2 requires the implementation of the RAS Extension and <xref linkend="v8.2.IESB" browsertext="ARMv8.2-IESB" filename="A_introduction_to_the_armv8_architecture.fm"/>.</para></note>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
<fields_condition>When ARMv8.2-IESB is implemented</fields_condition>
</field>
<field
id="0_13_13_2"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>13</field_msb>
<field_lsb>13</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="AET_12_10"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>AET</field_name>
<field_msb>12</field_msb>
<field_lsb>10</field_lsb>
<field_description order="before">
<para>Asynchronous Error Type.</para>
<para>When the RAS Extension is implemented and DFSC is <binarynumber>0b010001</binarynumber>, describes the state of the PE after taking the SError interrupt exception. The possible values of this field are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b000</field_value>
<field_value_description>
<para>Uncontainable error (UC).</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b001</field_value>
<field_value_description>
<para>Unrecoverable error (UEU).</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010</field_value>
<field_value_description>
<para>Restartable error (UEO).</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b011</field_value>
<field_value_description>
<para>Recoverable error (UER).</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b110</field_value>
<field_value_description>
<para>Corrected error (CE).</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>All other values are reserved.</para>
<para>If multiple errors are taken as a single SError interrupt exception, the overall state of the PE is reported. For example, if both a Recoverable and Unrecoverable error occurred, the state is Unrecoverable.</para>
<note><para>Software can use this information to determine what recovery might be possible. The recovery software must also examine any implemented fault records to determine the location and extent of the error.</para></note><para>This field is <arm-defined-word>RES0</arm-defined-word> if either:</para>
<list type="unordered">
<listitem><content>The RAS Extension is not implemented.</content>
</listitem><listitem><content>The value returned in the DFSC field is not <binarynumber>0b010001</binarynumber>.</content>
</listitem></list>
<note><para>Armv8.2 requires the implementation of the RAS Extension.</para></note>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="EA_9_9"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>EA</field_name>
<field_msb>9</field_msb>
<field_lsb>9</field_lsb>
<field_description order="before">
<para>External abort type. When the RAS Extension is implemented, this bit can provide an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> classification of External aborts.</para>
<para>For any abort other than an External abort this bit returns a value of 0.</para>
<para>This field is <arm-defined-word>RES0</arm-defined-word> if either:</para>
<list type="unordered">
<listitem><content>The RAS Extension is not implemented.</content>
</listitem><listitem><content>The value returned in the DFSC field is not <binarynumber>0b010001</binarynumber>.</content>
</listitem></list>
<note><para>Armv8.2 requires the implementation of the RAS Extension.</para></note>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_8_6"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>8</field_msb>
<field_lsb>6</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="DFSC_5_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>DFSC</field_name>
<field_msb>5</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Data Fault Status Code. When the RAS Extension is implemented, possible values of this field are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b000000</field_value>
<field_value_description>
<para>Uncategorized.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b010001</field_value>
<field_value_description>
<para>Asynchronous SError interrupt.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>All other values are reserved.</para>
<para>If the RAS Extension is not implemented, this field is <arm-defined-word>RES0</arm-defined-word>.</para>
<note><para>Armv8.2 requires the implementation of the RAS Extension.</para></note>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="IDS_24_24" msb="24" lsb="24"/>
<fieldat id="0_23_14" msb="23" lsb="14"/>
<fieldat id="IESB_13_13_1" msb="13" lsb="13"/>
<fieldat id="AET_12_10" msb="12" lsb="10"/>
<fieldat id="EA_9_9" msb="9" lsb="9"/>
<fieldat id="0_8_6" msb="8" lsb="6"/>
<fieldat id="DFSC_5_0" msb="5" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from a Breakpoint or Vector Catch debug exception</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_6"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>6</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="IFSC_5_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>IFSC</field_name>
<field_msb>5</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Instruction Fault Status Code. This field is set to <binarynumber>0b100010</binarynumber>, to indicate a Debug exception.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>For more information about generating these exceptions:</para>
<list type="unordered">
<listitem><content>For exceptions from AArch64, see <xref linkend="BCGGEABJ" browsertext="'Breakpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug)" filename="D_debug_exceptions"/>.</content>
</listitem><listitem><content>For exceptions from AArch32, see <xref linkend="BGBDJAJB" browsertext="'Breakpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G2 (AArch32 Self-hosted Debug)" filename="G_aarch32_self_hosted_debug"/> and <xref linkend="G2BCGJGBCC" browsertext="'Vector Catch exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G2" filename="G_aarch32_self_hosted_debug"/>.</content>
</listitem></list>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_6" msb="24" lsb="6"/>
<fieldat id="IFSC_5_0" msb="5" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from a Software Step exception</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="ISV_24_24"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>ISV</field_name>
<field_msb>24</field_msb>
<field_lsb>24</field_lsb>
<field_description order="before">
<para>Instruction syndrome valid. Indicates whether the EX bit, ISS[6], is valid, as follows:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>EX bit is <arm-defined-word>RES0</arm-defined-word>.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>EX bit is valid.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>See the EX bit description for more information.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_23_7"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>23</field_msb>
<field_lsb>7</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="EX_6_6"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>EX</field_name>
<field_msb>6</field_msb>
<field_lsb>6</field_lsb>
<field_description order="before">
<para>Exclusive operation. If the ISV bit is set to 1, this bit indicates whether a Load-Exclusive instruction was stepped.</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>An instruction other than a Load-Exclusive instruction was stepped.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>A Load-Exclusive instruction was stepped.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>If the ISV bit is set to 0, this bit is <arm-defined-word>RES0</arm-defined-word>, indicating no syndrome data is available.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="IFSC_5_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>IFSC</field_name>
<field_msb>5</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Instruction Fault Status Code. This field is set to <binarynumber>0b100010</binarynumber>, to indicate a Debug exception.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>For more information about generating these exceptions, see <xref linkend="BCGIIDAJ" browsertext="'Software Step exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug)" filename="D_debug_exceptions"/>.</para>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="ISV_24_24" msb="24" lsb="24"/>
<fieldat id="0_23_7" msb="23" lsb="7"/>
<fieldat id="EX_6_6" msb="6" lsb="6"/>
<fieldat id="IFSC_5_0" msb="5" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from a Watchpoint exception</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_14"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>14</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="VNCR_13_13_1"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>VNCR</field_name>
<field_msb>13</field_msb>
<field_lsb>13</field_lsb>
<field_description order="before">
<para>Indicates that the watchpoint came from use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link> register by EL1 code.</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The watchpoint was not generated by the use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link> by EL1 code.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The watchpoint was generated by the use of <register_link state="AArch64" id="AArch64-vncr_el2.xml">VNCR_EL2</register_link> by EL1 code.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>This field is 0 in ESR_EL1.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
<fields_condition>When ARMv8.4-NV is implemented</fields_condition>
</field>
<field
id="0_13_13_2"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>13</field_msb>
<field_lsb>13</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="0_12_9"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>12</field_msb>
<field_lsb>9</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="CM_8_8"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>CM</field_name>
<field_msb>8</field_msb>
<field_lsb>8</field_lsb>
<field_description order="before">
<para>Cache maintenance. Indicates whether the Watchpoint exception came from a cache maintenance or address translation instruction:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>The Watchpoint exception was not generated by the execution of one of the System instructions identified in the description of value 1.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>The Watchpoint exception was generated by either the execution of a cache maintenance instruction or by a synchronous Watchpoint exception on the execution of an address translation instruction. The <register_link id="AArch64-dc-zva.xml" state="AArch64">DC ZVA</register_link> instruction is not classified as a cache maintenance instruction, and therefore its execution cannot cause this field to be set to 1.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="0_7_7"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>7</field_msb>
<field_lsb>7</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="WnR_6_6"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>WnR</field_name>
<field_msb>6</field_msb>
<field_lsb>6</field_lsb>
<field_description order="before">
<para>Write not Read. Indicates whether the Watchpoint exception was caused by an instruction writing to a memory location, or by an instruction reading from a memory location. The possible values of this bit are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>Watchpoint exception caused by an instruction reading from a memory location.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>Watchpoint exception caused by an instruction writing to a memory location.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>For Watchpoint exceptions on cache maintenance and address translation instructions, this bit always returns a value of 1.</para>
<para>For Watchpoint exceptions from an atomic instruction, this field is set to 0 if a read of the location would have generated the Watchpoint exception, otherwise it is set to 1.</para>
<para>If multiple watchpoints match on the same access, it is <arm-defined-word>UNPREDICTABLE</arm-defined-word> which watchpoint generates the Watchpoint exception.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="DFSC_5_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>DFSC</field_name>
<field_msb>5</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Data Fault Status Code. This field is set to <binarynumber>0b100010</binarynumber>, to indicate a Debug exception.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>For more information about generating these exceptions, see <xref linkend="BCGGECBJ" browsertext="'Watchpoint exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug)" filename="D_debug_exceptions"/>.</para>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_14" msb="24" lsb="14"/>
<fieldat id="VNCR_13_13_1" msb="13" lsb="13"/>
<fieldat id="0_12_9" msb="12" lsb="9"/>
<fieldat id="CM_8_8" msb="8" lsb="8"/>
<fieldat id="0_7_7" msb="7" lsb="7"/>
<fieldat id="WnR_6_6" msb="6" lsb="6"/>
<fieldat id="DFSC_5_0" msb="5" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from execution of a Breakpoint instruction</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_16"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>16</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="Comment_15_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>Comment</field_name>
<field_msb>15</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Set to the instruction comment field value, zero extended as necessary. For the AArch32 BKPT instructions, the comment field is described as the immediate field.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>For more information about generating these exceptions, see <xref linkend="BCGIEHAG" browsertext="'Breakpoint instruction exceptions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D2 (AArch64 Self-hosted Debug)" filename="D_debug_exceptions"/>.</para>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_16" msb="24" lsb="16"/>
<fieldat id="Comment_15_0" msb="15" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_condition>When ARMv8.3-NV is implemented</fields_condition>
<fields_instance>Exception from ERET, ERETAA or ERETAB instruction</fields_instance>
<text_before_fields>
<para>This EC value only applies when <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.NV is 1.</para>
</text_before_fields>
<field
id="0_24_2"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>2</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="ERET_1_1"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>ERET</field_name>
<field_msb>1</field_msb>
<field_lsb>1</field_lsb>
<field_description order="before">
<para>Indicates whether an ERET or ERETA* instruction was trapped to EL2. Possible values are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>ERET instruction trapped to EL2.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>ERETAA or ERETAB instruction trapped to EL2.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>If this bit is 0, the ERETA field is <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<field
id="ERETA_0_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>ERETA</field_name>
<field_msb>0</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Indicates whether an ERETAA or ERETAB instruction was trapped to EL2. Possible values are:</para>
</field_description>
<field_values>
<field_value_instance>
<field_value>0b0</field_value>
<field_value_description>
<para>ERETAA instruction trapped to EL2.</para>
</field_value_description>
</field_value_instance>
<field_value_instance>
<field_value>0b1</field_value>
<field_value_description>
<para>ERETAB instruction trapped to EL2.</para>
</field_value_description>
</field_value_instance>
</field_values>
<field_description order="after">
<para>When the ERET field is 0, this bit is <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_resets>
<field_reset>
<field_reset_standard_text>U</field_reset_standard_text>
</field_reset>
</field_resets>
</field>
<text_after_fields>
<para>For more information about generating these exceptions, see <xref linkend="CHDCFJDF" browsertext="'Traps to EL2 for Nested virtualization' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</para>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fields_condition>When ARMv8.3-NV is implemented</fields_condition>
<fieldat id="0_24_2" msb="24" lsb="2"/>
<fieldat id="ERET_1_1" msb="1" lsb="1"/>
<fieldat id="ERETA_0_0" msb="0" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_condition>When ARMv8.5-BTI is implemented</fields_condition>
<fields_instance>Exception from Branch Target Identification instruction</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_2"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>2</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<field
id="BTYPE_1_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
>
<field_name>BTYPE</field_name>
<field_msb>1</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>This field is set to the PSTATE.BTYPE value that generated the Branch Target Exception.</para>
</field_description>
<field_values>
</field_values>
<field_resets>
</field_resets>
</field>
<text_after_fields>
<para>For more information about generating these exceptions, see <xref browsertext="The AArch64 application level programmers' model' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section B1" filename="B_the_aarch64_application_level_programmers_model.fm" linkend="BEIBJCGI"></xref>.</para>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fields_condition>When ARMv8.5-BTI is implemented</fields_condition>
<fieldat id="0_24_2" msb="24" lsb="2"/>
<fieldat id="BTYPE_1_0" msb="1" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
<partial_fieldset>
<fields length="25">
<fields_instance>Exception from a Pointer Authentication instruction when HCR_EL2.API == 0 || SCR_EL3.API == 0</fields_instance>
<text_before_fields>
</text_before_fields>
<field
id="0_24_0"
is_variable_length="False"
has_partial_fieldset="False"
is_linked_to_partial_fieldset="False"
is_access_restriction_possible="False"
is_constant_value="False"
rwtype="RES0"
>
<field_name>0</field_name>
<field_msb>24</field_msb>
<field_lsb>0</field_lsb>
<field_description order="before">
<para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
</field_description>
<field_values>
</field_values>
</field>
<text_after_fields>
<para>For more information about generating these exceptions, see:</para>
<list type="unordered">
<listitem><content><xref linkend="CHDGDDCJ" browsertext="'Trap to EL2 Non-secure EL0 accesses to Pointer authentication key registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem><listitem><content><xref linkend="CHDIGBED" browsertext="'Trap to EL3 accesses to Pointer authentication instructions' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section D1" filename="D_the_aarch64_system_level_programmers_model"/>.</content>
</listitem></list>
</text_after_fields>
</fields>
<reg_fieldset length="25">
<fieldat id="0_24_0" msb="24" lsb="0"/>
</reg_fieldset>
</partial_fieldset>
</field>
<text_after_fields>
</text_after_fields>
</fields>
<reg_fieldset length="64">
<fieldat id="0_63_32" msb="63" lsb="32"/>
<fieldat id="EC_31_26" msb="31" lsb="26"/>
<fieldat id="IL_25_25" msb="25" lsb="25"/>
<fieldat id="ISS_24_0" msb="24" lsb="0"/>
</reg_fieldset>
</reg_fieldsets>
<access_mechanisms>
<access_permission_text>
<para>When <register_link state="AArch64" id="AArch64-hcr_el2.xml">HCR_EL2</register_link>.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic ESR_EL1 or ESR_EL12 are not guaranteed to be ordered with respect to accesses using the other mnemonic.</para>
</access_permission_text>
<access_mechanism accessor="MRS ESR_EL1">
<encoding>
<access_instruction>MRS <Xt>, ESR_EL1</access_instruction>
<enc n="op0" v="0b11"/>
<enc n="op1" v="0b000"/>
<enc n="CRn" v="0b0101"/>
<enc n="CRm" v="0b0010"/>
<enc n="op2" v="0b000"/>
</encoding>
<access_permission>
<ps name="MRS" sections="1" secttype="access_permission">
<pstext>
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then
return NVMem[0x138];
else
return ESR_EL1;
elsif PSTATE.EL == EL2 then
if HCR_EL2.E2H == '1' then
return ESR_EL2;
else
return ESR_EL1;
elsif PSTATE.EL == EL3 then
return ESR_EL1;
</pstext>
</ps>
</access_permission>
</access_mechanism>
<access_mechanism accessor="MSRregister ESR_EL1">
<encoding>
<access_instruction>MSR ESR_EL1, <Xt></access_instruction>
<enc n="op0" v="0b11"/>
<enc n="op1" v="0b000"/>
<enc n="CRn" v="0b0101"/>
<enc n="CRm" v="0b0010"/>
<enc n="op2" v="0b000"/>
</encoding>
<access_permission>
<ps name="MSRregister" sections="1" secttype="access_permission">
<pstext>
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '111' then
NVMem[0x138] = X[t];
else
ESR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if HCR_EL2.E2H == '1' then
ESR_EL2 = X[t];
else
ESR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
ESR_EL1 = X[t];
</pstext>
</ps>
</access_permission>
</access_mechanism>
<access_mechanism accessor="MRS ESR_EL12">
<encoding>
<access_instruction>MRS <Xt>, ESR_EL12</access_instruction>
<enc n="op0" v="0b11"/>
<enc n="op1" v="0b101"/>
<enc n="CRn" v="0b0101"/>
<enc n="CRm" v="0b0010"/>
<enc n="op2" v="0b000"/>
</encoding>
<access_permission>
<ps name="MRS" sections="1" secttype="access_permission">
<pstext>
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then
return NVMem[0x138];
elsif EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if EL2Enabled() && HCR_EL2.E2H == '1' then
return ESR_EL1;
else
UNDEFINED;
elsif PSTATE.EL == EL3 then
if EL2Enabled() && HCR_EL2.E2H == '1' then
return ESR_EL1;
else
UNDEFINED;
</pstext>
</ps>
</access_permission>
</access_mechanism>
<access_mechanism accessor="MSRregister ESR_EL12">
<encoding>
<access_instruction>MSR ESR_EL12, <Xt></access_instruction>
<enc n="op0" v="0b11"/>
<enc n="op1" v="0b101"/>
<enc n="CRn" v="0b0101"/>
<enc n="CRm" v="0b0010"/>
<enc n="op2" v="0b000"/>
</encoding>
<access_permission>
<ps name="MSRregister" sections="1" secttype="access_permission">
<pstext>
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then
NVMem[0x138] = X[t];
elsif EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if EL2Enabled() && HCR_EL2.E2H == '1' then
ESR_EL1 = X[t];
else
UNDEFINED;
elsif PSTATE.EL == EL3 then
if EL2Enabled() && HCR_EL2.E2H == '1' then
ESR_EL1 = X[t];
else
UNDEFINED;
</pstext>
</ps>
</access_permission>
</access_mechanism>
<access_mechanism accessor="MRS ESR_EL2">
<encoding>
<access_instruction>MRS <Xt>, ESR_EL2</access_instruction>
<enc n="op0" v="0b11"/>
<enc n="op1" v="0b100"/>
<enc n="CRn" v="0b0101"/>
<enc n="CRm" v="0b0010"/>
<enc n="op2" v="0b000"/>
</encoding>
<access_permission>
<ps name="MRS" sections="1" secttype="access_permission">
<pstext>
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
return ESR_EL1;
elsif EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
return ESR_EL2;
elsif PSTATE.EL == EL3 then
return ESR_EL2;
</pstext>
</ps>
</access_permission>
</access_mechanism>
<access_mechanism accessor="MSRregister ESR_EL2">
<encoding>
<access_instruction>MSR ESR_EL2, <Xt></access_instruction>
<enc n="op0" v="0b11"/>
<enc n="op1" v="0b100"/>
<enc n="CRn" v="0b0101"/>
<enc n="CRm" v="0b0010"/>
<enc n="op2" v="0b000"/>
</encoding>
<access_permission>
<ps name="MSRregister" sections="1" secttype="access_permission">
<pstext>
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
ESR_EL1 = X[t];
elsif EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
ESR_EL2 = X[t];
elsif PSTATE.EL == EL3 then
ESR_EL2 = X[t];
</pstext>
</ps>
</access_permission>
</access_mechanism>
</access_mechanisms>
<arch_variants>
</arch_variants>
</register>
</registers>
<timestamp>27/03/2019 21:59; e5e4db499bf9867a4b93324c4dbac985d3da9376</timestamp>
</register_page>