#include <kern/machine.h>
#include <kern/processor.h>
#include <mach/machine.h>
#include <mach/processor_info.h>
#include <mach/mach_types.h>
#include <mach/boolean.h>
#include <kern/thread.h>
#include <kern/task.h>
#include <mach/vm_param.h>
#include <vm/vm_kern.h>
#include <vm/vm_map.h>
#include <vm/vm_page.h>
#include <vm/pmap.h>
#include <ppc/exception.h>
#include <ppc/Firmware.h>
#include <ppc/low_trace.h>
#include <ppc/db_low_trace.h>
#include <ppc/mappings.h>
#include <ppc/pmap.h>
#include <ppc/mem.h>
#include <ppc/savearea.h>
#include <ppc/Diagnostics.h>
#include <ppc/machine_cpu.h>
#include <pexpert/pexpert.h>
#include <console/video_console.h>
#include <ppc/trap.h>
extern struct vc_info vinfo;
kern_return_t testPerfTrap(int trapno, struct savearea *ss,
unsigned int dsisr, addr64_t dar);
int diagCall(struct savearea *save) {
union {
unsigned long long tbase;
unsigned int tb[2];
} ttt, adj;
natural_t tbu, tbu2, tbl;
struct per_proc_info *per_proc;
int cpu, ret;
unsigned int tstrt, tend, temp, temp2;
addr64_t src, snk;
uint64_t scom, hid1, hid4, srrwrk, stat;
scomcomm sarea;
if(!(dgWork.dgFlags & enaDiagSCs)) return 0;
switch(save->save_r3) {
case dgAdjTB:
adj.tb[0] = 0;
adj.tb[1] = save->save_r4;
if(adj.tb[1] & 0x80000000) adj.tb[0] = 0xFFFFFFFF;
do {
asm volatile(" mftbu %0" : "=r" (tbu));
asm volatile(" mftb %0" : "=r" (tbl));
asm volatile(" mftbu %0" : "=r" (tbu2));
} while (tbu != tbu2);
ttt.tb[0] = tbu;
ttt.tb[1] = tbl;
ttt.tbase = ttt.tbase + adj.tbase;
tbu = ttt.tb[0];
tbl = ttt.tb[1];
mttb(0);
mttbu(tbu);
mttb(tbl);
return -1;
case dgLRA:
save->save_r3 = pmap_find_phys(current_act()->map->pmap, save->save_r4);
return -1;
case dgpcpy:
#if 1
src = (save->save_r4 << 32) | (0x00000000FFFFFFFFULL & save->save_r5);
snk = (save->save_r6 << 32) | (0x00000000FFFFFFFFULL & save->save_r7);
save->save_r3 = copypv(src, snk, save->save_r8, save->save_r9);
#endif
return 1;
case dgprw:
src = (save->save_r5 << 32) | (0x00000000FFFFFFFFULL & save->save_r6);
switch(save->save_r4) {
case 0:
save->save_r3 = (uint64_t)ml_phys_read_byte((unsigned int)src);
break;
case 1:
save->save_r3 = (uint64_t)ml_phys_read_byte_64(src);
break;
case 2:
save->save_r3 = (uint64_t)ml_phys_read((unsigned int)src);
break;
case 3:
save->save_r3 = (uint64_t)ml_phys_read_64(src);
break;
case 4:
ml_phys_write_byte((unsigned int)src, (unsigned int)save->save_r7);
break;
case 5:
ml_phys_write_byte_64(src, (unsigned int)save->save_r7);
break;
case 6:
ml_phys_write((unsigned int)src, (unsigned int)save->save_r7);
break;
case 7:
ml_phys_write_64(src, (unsigned int)save->save_r7);
break;
}
return 1;
case dgreset:
cpu = save->save_r4;
if(cpu >= NCPUS) {
save->save_r3 = KERN_FAILURE;
return 1;
}
if(!machine_slot[cpu].running) return KERN_FAILURE;
per_proc = &per_proc_info[cpu];
(void)PE_cpu_start(per_proc->cpu_id,
per_proc->start_paddr, (vm_offset_t)per_proc);
save->save_r3 = KERN_SUCCESS;
return 1;
case dgFlush:
cacheInit();
return 1;
case dgtest:
if(save->save_r4) perfTrapHook = testPerfTrap;
else perfTrapHook = 0;
return 1;
case dgBMphys:
pmap_map_block(current_act()->map->pmap, (addr64_t)save->save_r4,
save->save_r5, save->save_r6, save->save_r7, save->save_r8, 0);
return 1;
case dgUnMap:
(void)mapping_remove(current_act()->map->pmap, save->save_r4);
return 1;
case dgAlign:
temp = dgWork.dgFlags;
temp2 = (save->save_r4 & 1) << (31 - enaNotifyEMb);
dgWork.dgFlags = (temp & ~enaNotifyEM) | temp2;
save->save_r3 = (temp >> (31 - enaNotifyEMb)) & 1;
return 1;
case dgBootScreen:
ml_set_interrupts_enabled(1);
(void)copyout((char *)&vinfo, CAST_DOWN(char *, save->save_r4), sizeof(struct vc_info));
ml_set_interrupts_enabled(0);
return 1;
case dgCPNull:
ml_set_interrupts_enabled(1);
(void)copyout((char *)&vinfo, CAST_DOWN(char *, save->save_r4), 0);
ml_set_interrupts_enabled(0);
return 1;
case dgmck:
if(!(per_proc_info[0].pf.Available & pf64Bit)) return 0;
fwEmMck(save->save_r4, save->save_r5, save->save_r6, save->save_r7, save->save_r8, save->save_r9);
return -1;
case dg64:
if(!(per_proc_info[0].pf.Available & pf64Bit)) return 0;
srrwrk = save->save_srr1 >> 63;
save->save_srr1 = (save->save_srr1 & 0x7FFFFFFFFFFFFFFFULL) | (save->save_r4 << 63);
save->save_r3 = srrwrk;
return -1;
case dgProbeRead:
src = (save->save_r4 << 32) | (0x00000000FFFFFFFFULL & save->save_r5);
save->save_r3 = ml_probe_read_64(src, &temp);
save->save_r4 = temp;
return -1;
case dgPerfMon:
setPmon(save->save_r4, save->save_r5);
return -1;
case dgMapPage:
(void)mapping_map(current_act()->map->pmap,
(addr64_t)(((save->save_r5 & 0xFFFFFFFF) << 32) | (save->save_r5 & 0xFFFFFFFF)), save->save_r6, 0, 1, VM_PROT_READ|VM_PROT_WRITE);
return -1;
case dgScom:
ret = copyin((unsigned int)(save->save_r4), &sarea, sizeof(scomcomm));
if(ret) return 0;
sarea.scomstat = 0xFFFFFFFFFFFFFFFFULL;
cpu = cpu_number();
if((sarea.scomcpu < NCPUS) && machine_slot[sarea.scomcpu].running) {
if(sarea.scomcpu == cpu) fwSCOM(&sarea);
else {
(void)cpu_signal(sarea.scomcpu, SIGPcpureq, CPRQscom ,(unsigned int)&sarea);
(void)hw_cpu_sync((unsigned long)&sarea.scomstat, LockTimeOut);
}
}
ret = copyout(&sarea, (unsigned int)(save->save_r4), sizeof(scomcomm));
if(ret) return 0;
return -1;
default:
return 0;
}
};
kern_return_t testPerfTrap(int trapno, struct savearea *ss,
unsigned int dsisr, addr64_t dar) {
if(trapno != T_ALIGNMENT) return KERN_FAILURE;
kprintf("alignment exception at %08X, srr1 = %08X, dsisr = %08X, dar = %08X\n", ss->save_srr0,
ss->save_srr1, dsisr, dar);
return KERN_SUCCESS;
}