/*
* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
*
* @APPLE_LICENSE_HEADER_START@
*
* The contents of this file constitute Original Code as defined in and
* are subject to the Apple Public Source License Version 1.1 (the
* "License"). You may not use this file except in compliance with the
* License. Please obtain a copy of the License at
* http://www.apple.com/publicsource and read it before using this file.
*
* This Original Code and all software distributed under the License are
* distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
* License for the specific language governing rights and limitations
* under the License.
*
* @APPLE_LICENSE_HEADER_END@
*/
/*
* @OSF_COPYRIGHT@
*/
#include <cpus.h>
#include <mach_kdb.h>
#include <mach_kdp.h>
#include <mach_kgdb.h>
#include <ppc/asm.h>
#include <ppc/proc_reg.h>
#include <ppc/spec_reg.h>
#include <mach/ppc/vm_param.h>
#include <assym.s>
#define ptFilter 0
#define ptVersion 4
#define ptRevision 6
#define ptFeatures 8
#define ptInitRout 12
#define ptRptdProc 16
#define ptTempMax 20
#define ptTempThr 24
#define ptLineSize 28
#define ptl1iSize 32
#define ptl1dSize 36
#define ptSize 40
#define bootCPU 10
#define firstInit 9
#define firstBoot 8
/* Defines for PVRs */
#define PROCESSOR_VERSION_601 1
#define PROCESSOR_VERSION_603 3
#define PROCESSOR_VERSION_604 4
#define PROCESSOR_VERSION_603e 6
#define PROCESSOR_VERSION_750 8
#define PROCESSOR_VERSION_750FX 0x7000 /* ? */
#define PROCESSOR_VERSION_604e 9
#define PROCESSOR_VERSION_604ev 10 /* ? */
#define PROCESSOR_VERSION_7400 12 /* ? */
#define PROCESSOR_VERSION_7410 0x800C /* ? */
#define PROCESSOR_VERSION_7450 0x8000 /* ? */
#define PROCESSOR_VERSION_7455 0x8001 /* ? */
/*
* Interrupt and bootup stack for initial processor
*/
.file "start.s"
.data
/* Align on page boundry */
.align PPC_PGSHIFT
/* Red zone for interrupt stack, one page (will be unmapped)*/
.set ., .+PPC_PGBYTES
/* intstack itself */
.globl EXT(FixedStackStart)
EXT(FixedStackStart):
.globl EXT(intstack)
EXT(intstack):
.set ., .+INTSTACK_SIZE*NCPUS
/* Debugger stack - used by the debugger if present */
/* NOTE!!! Keep the debugger stack right after the interrupt stack */
#if MACH_KDP || MACH_KDB
.globl EXT(debstack)
EXT(debstack):
.set ., .+KERNEL_STACK_SIZE*NCPUS
.globl EXT(FixedStackEnd)
EXT(FixedStackEnd):
.align ALIGN
.globl EXT(intstack_top_ss)
EXT(intstack_top_ss):
.long EXT(intstack)+INTSTACK_SIZE-FM_SIZE /* intstack_top_ss points to the top of interrupt stack */
.align ALIGN
.globl EXT(debstack_top_ss)
EXT(debstack_top_ss):
.long EXT(debstack)+KERNEL_STACK_SIZE-FM_SIZE /* debstack_top_ss points to the top of debug stack */
.globl EXT(debstackptr)
EXT(debstackptr):
.long EXT(debstack)+KERNEL_STACK_SIZE-FM_SIZE
#endif /* MACH_KDP || MACH_KDB */
/*
* All CPUs start here.
*
* This code is called from SecondaryLoader
*
* Various arguments are passed via a table:
* ARG0 = pointer to other startup parameters
*/
.text
ENTRY(_start_cpu,TAG_NO_FRAME_USED)
crclr bootCPU mr r30,r3 lwz r15,ruptStamp(r3) lwz r16,ruptStamp+4(r3) mtspr tbu,r15
b allstart
ENTRY(_start,TAG_NO_FRAME_USED)
lis r30,hi16(EXT(per_proc_info)) crset bootCPU lwz r17,pfAvailable(r30) crmove firstInit,cr0_eq
lis r20,HIGH_ADDR(fwdisplock) ori r20,r20,LOW_ADDR(fwdisplock)
allstart: mr r31,r3 ori r23,r23,lo16(EXT(per_proc_info)) mtsprg 0,r30 mfspr r6,hid0 rlwinm r6,r6,0,sleep+1,doze-1 mtmsr r7
li r7,((0x7FF<<2)|2) li r9,0 mtsprg 1,r9 mtsprg 3,r9
sync
isync
mtdbatu 0,r7 mtdbatu 1,r9 mtdbatu 2,r9 mtdbatu 3,r9 sync
isync
mtibatu 0,r7 mtibatu 1,r9 mtibatu 2,r9 mtibatu 3,r9 sync
isync
lis r26,hi16(processor_types) mfpvr r10 nextPVR: lwz r28,ptFilter(r26) and r28,r10,r28 beq donePVR b nextPVR donePVR: lwz r20,ptInitRout(r26)
bf firstInit,notFirst
lwz r17,ptFeatures(r26) lwz r13,ptRptdProc(r26)
lwz r13,ptTempMax(r26) lwz r13,ptTempThr(r26)
lwz r13,ptLineSize(r26) lwz r13,ptl1iSize(r26) lwz r13,ptl1dSize(r26) b doOurInit notFirst: lwz r17,pfAvailable(r30) bne doOurInit lis r23,hi16(EXT(per_proc_info))
la r7,pfAvailable(r30) li r9,(pfSize+thrmSize)/4 cpyFeat: subi r9,r9,1 stw r0,0(r7) addi r7,r7,4 bgt cpyFeat lwz r17,pfAvailable(r30) doOurInit:
mr. r20,r20 bnelrl ori r17,r17,lo16(pfValid) mtsprg 2,r17 rlwinm. r0,r17,0,pfFloatb,pfFloatb
li r0,MSR_VM_OFF|MASK(MSR_FP) isync
lis r5,HIGH_ADDR(EXT(FloatInit)) /* Get top of floating point init value */
ori r5,r5,LOW_ADDR(EXT(FloatInit)) /* Slam bottom */
lfd f0,0(r5) /* Initialize FP0 */
fmr f1,f0 /* Ours in not */
fmr f2,f0 /* to wonder why, */
fmr f3,f0 /* ours is but to */
fmr f4,f0 /* do or die! */
fmr f5,f0
fmr f6,f0
fmr f7,f0
fmr f8,f0
fmr f9,f0
fmr f10,f0
fmr f11,f0
fmr f12,f0
fmr f13,f0
fmr f14,f0
fmr f15,f0
fmr f16,f0
fmr f17,f0
fmr f18,f0
fmr f19,f0
fmr f20,f0
fmr f21,f0
fmr f22,f0
fmr f23,f0
fmr f24,f0
fmr f25,f0
fmr f26,f0
fmr f27,f0
fmr f28,f0
fmr f29,f0
fmr f30,f0
fmr f31,f0
li r0, MSR_VM_OFF isync
noFloat: rlwinm. r0,r17,0,pfAltivecb,pfAltivecb
li r0,0 lis r7,hi16(MSR_VEC_ON) mtmsr r7
lis r5,hi16(EXT(QNaNbarbarian))
mtspr vrsave,r0 vspltisw v1,0 mtvscr v1 vor v1,v0,v0 vor v4,v0,v0 vor v6,v0,v0 vor v8,v0,v0 vor v10,v0,v0 vor v12,v0,v0 vor v14,v0,v0 vor v16,v0,v0 vor v18,v0,v0 vor v20,v0,v0 vor v22,v0,v0 vor v24,v0,v0 vor v26,v0,v0 vor v28,v0,v0 vor v30,v0,v0
li r0, MSR_VM_OFF isync
noVector: rlwinm. r0,r17,0,pfSMPcapb,pfSMPcapb
lhz r13,PP_CPU_NUMBER(r30)
noSMP: rlwinm. r0,r17,0,pfThermalb,pfThermalb
li r13,0 li r13,lo16(thrmtidm|thrmvm) lis r13,hi16(thrmthrm) mtspr thrm2,r13 noThermometer:
bl EXT(cacheInit) li r0,MSR_SUPERVISOR_INT_OFF isync
bf bootCPU,callcpu lis r29,HIGH_ADDR(EXT(intstack_top_ss)) lwz r29,0(r29)
li r28,0
stw r28,FM_BACKPTR(r29) mr r1,r29
mr r3,r31 bl EXT(ppc_init)
callcpu:
lwz r29,PP_INTSTACK_TOP_SS(r31) li r28,0
stw r28,FM_BACKPTR(r29)
mr r1,r29
bl EXT(ppc_init_cpu)
init750:
bf firstBoot, init750nb mfspr r13,l2cr bne+ i750hl2
i750hl2:
lis r14,hi16(256*1024) rlwinm r15,r15,4,30,31 slw r14,r14,r15
stw r13,pfl2crOriginal(r30) stw r14,pfl2Size(r30)
init750l2none:
rlwinm r17,r17,0,pfL2b+1,pfL2b-1 init750l2done:
mfspr r11,hid0 blr init750nb:
lwz r11,pfHID0(r30) mtspr hid0,r11 sync
blr
init750CX:
bf firstBoot, init750 li r14,lo16(0xFD5F) slw r14,r14,r13 b init750
init750FX:
bf firstBoot, init750FXnb
mfspr r11, hid1
stw r11, pfHID1(r30)
init750FXnb:
lwz r13, pfHID0(r30)
rlwinm. r0, r11, 0, hid1ps, hid1ps rlwinm r13, r13, 0, btic+1, btic-1 init750FXnb2:
sync
mtspr hid0, r13 sync
rlwinm r12, r11, 0, hid1ps+1, hid1ps-1 mftb r13 init750FXnbloop:
mftb r14
sub r14, r14, r13
cmpli cr0, r14, 5000
ble init750FXnbloop
mtspr hid1, r11
bf firstBoot, init750FXV2nb mfspr r11, hid2
stw r11, pfHID2(r30)
init750FXV2nb:
lwz r13, pfHID2(r30) mtspr hid2, r13 b init750FX
init7400: bf firstBoot,i7400nb rlwinm. r0,r13,0,l2e,l2e rlwinm r17,r17,0,pfL2b+1,pfL2b-1 i7400hl2: lis r14,hi16(256*1024) rlwinm r15,r15,4,30,31
slw r14,r14,r15 stw r13,pfl2crOriginal(r30) stw r14,pfl2Size(r30) mfspr r11,hid0 mtspr hid0,r11 stw r11,pfHID0(r30) mfspr r11,msscr0 mfspr r11,msscr1 blr i7400nb:
li r11,0
mtspr l2cr,r11 sync
mtspr hid0,r11 sync
lwz r11,pfMSSCR0(r30) sync
mtspr msscr0,r11 isync
sync
mtspr msscr1,r11 sync
blr
init7400v2_7:
bf firstBoot, init7400
mfspr r13, hid0 mtspr hid0, r13 sync
b init7400
init7410: li r13,0 b init7400
init745X:
bf firstBoot,init745Xnb mfspr r13,l2cr bne+ init745Xhl2
init745Xhl2: lis r14,hi16(256*1024) add r14,r14,r15 stw r13,pfl2crOriginal(r30) stw r14,pfl2Size(r30) mfspr r13,l3cr bne+ init745Xhl3
init745Xhl3: cmplwi cr0,r13,0 lis r14,hi16(1024*1024) slw r14,r14,r15 stw r13,pfl3crOriginal(r30) stw r14,pfl3Size(r30)
init745Xnone:
rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 or r17,r17,r11
init745Xfin:
rlwinm r17,r17,0,pfWillNapb+1,pfWillNapb-1 mfspr r11,hid0 mfspr r11,hid1 mfspr r11,msscr0 mfspr r11,msscr1 mfspr r11,ictrl mfspr r11,ldstcr mfspr r11,ldstdb mfspr r11,pir blr
init745Xnb: lwz r11,pfHID0(r30) mtspr hid0,r11 lwz r11,pfHID1(r30) mtspr hid1,r11 lwz r11,pfMSSCR0(r30) mtspr msscr0,r11 sync
lwz r11,pfICTRL(r30) mtspr ictrl,r11 sync
lwz r11,pfLDSTCR(r30) mtspr ldstcr,r11 sync
lwz r11,pfLDSTDB(r30) mtspr ldstdb,r11 sync
blr
init7450:
bf firstBoot, init745X mfspr r13, pir bne init7450done ori r13, r13, 0x0400
init7450done:
b init745X
.align 2
processor_types:
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfSMPcap | pfL1i | pfL1d
.long 0
.long CPU_SUBTYPE_POWERPC_ALL
.long 0
.long 0
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfL1i | pfL1d
.long 0
.long CPU_SUBTYPE_POWERPC_603
.long 0
.long 0
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfL1i | pfL1d
.long 0
.long CPU_SUBTYPE_POWERPC_603e
.long 0
.long 0
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfSMPcap | pfL1i | pfL1d
.long 0
.long CPU_SUBTYPE_POWERPC_604
.long 0
.long 0
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfSMPcap | pfL1i | pfL1d
.long 0
.long CPU_SUBTYPE_POWERPC_604e
.long 0
.long 0
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfSMPcap | pfL1i | pfL1d
.long 0
.long CPU_SUBTYPE_POWERPC_604e
.long 0
.long 0
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFFFFFF .short 0x4202
.long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL2
.long init750
.long CPU_SUBTYPE_POWERPC_750
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0F00 .short 0x0200
.long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL2
.long init750CX
.long CPU_SUBTYPE_POWERPC_750
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pfL1i | pfL1d | pfL2
.long init750
.long CPU_SUBTYPE_POWERPC_750
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0F00 .short 0x0100
.long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pfL1i | pfL1d | pfL2
.long init750FX
.long CPU_SUBTYPE_POWERPC_750
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfCanSleep | pfCanNap | pfCanDoze | pfSlowNap | pfNoMuMMCK | pfL1i | pfL1d | pfL2
.long init750FXV2
.long CPU_SUBTYPE_POWERPC_750
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFFFFF8 .short 0x0200
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
.long init7400v2_7
.long CPU_SUBTYPE_POWERPC_7400
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfThermal | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
.long init7400
.long CPU_SUBTYPE_POWERPC_7400
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFFFFFF .short 0x1101
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
.long init7410
.long CPU_SUBTYPE_POWERPC_7400
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfCanDoze | pfL1i | pfL1d | pfL1fa | pfL2 | pfL2fa
.long init7410
.long CPU_SUBTYPE_POWERPC_7400
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFFFF00 .short 0x0100
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
.long init7450
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFFFFFF .short 0x0200
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
.long init7450
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
.long init7450
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFFFF00 .short 0x0100
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
.long init745X
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFFFFFF .short 0x0200
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfWillNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
.long init745X
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0xFFFF0000 .short 0
.long pfFloat | pfAltivec | pfSMPcap | pfCanSleep | pfCanNap | pfNoMSRir | pfNoL2PFNap | pfLClck | pfL1i | pfL1d | pfL2 | pfL2fa | pfL2i | pfL3 | pfL3fa
.long init745X
.long CPU_SUBTYPE_POWERPC_7450
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024
.align 2
.long 0x00000000 .short 0
.long pfFloat | pfL1i | pfL1d
.long 0
.long CPU_SUBTYPE_POWERPC_ALL
.long 105
.long 90
.long 32
.long 32*1024
.long 32*1024