#ifndef _I386_PROC_REG_H_
#define _I386_PROC_REG_H_
#define MSR_P5_TSC 0x10
#define MSR_P5_CESR 0x11
#define MSR_P5_CTR0 0x12
#define MSR_P5_CTR1 0x13
#define MSR_P5_CESR_PC 0x0200
#define MSR_P5_CESR_CC 0x01C0
#define MSR_P5_CESR_ES 0x003F
#define MSR_P5_CESR_SHIFT 16
#define MSR_P5_CESR_MASK (MSR_P5_CESR_PC|\
MSR_P5_CESR_CC|\
MSR_P5_CESR_ES)
#define MSR_P5_CESR_CC_CLOCK 0x0100
#define MSR_P5_CESR_CC_DISABLE 0x0000
#define MSR_P5_CESR_CC_CPL012 0x0040
#define MSR_P5_CESR_CC_CPL3 0x0080
#define MSR_P5_CESR_CC_CPL 0x00C0
#define MSR_P5_CESR_ES_DATA_READ 0x000000
#define MSR_P5_CESR_ES_DATA_WRITE 0x000001
#define MSR_P5_CESR_ES_DATA_RW 0x101000
#define MSR_P5_CESR_ES_DATA_TLB_MISS 0x000010
#define MSR_P5_CESR_ES_DATA_READ_MISS 0x000011
#define MSR_P5_CESR_ES_DATA_WRITE_MISS 0x000100
#define MSR_P5_CESR_ES_DATA_RW_MISS 0x101001
#define MSR_P5_CESR_ES_HIT_EM 0x000101
#define MSR_P5_CESR_ES_DATA_CACHE_WB 0x000110
#define MSR_P5_CESR_ES_EXTERNAL_SNOOP 0x000111
#define MSR_P5_CESR_ES_CACHE_SNOOP_HIT 0x001000
#define MSR_P5_CESR_ES_MEM_ACCESS_PIPE 0x001001
#define MSR_P5_CESR_ES_BANK_CONFLICTS 0x001010
#define MSR_P5_CESR_ES_MISALIGNED 0x001011
#define MSR_P5_CESR_ES_CODE_READ 0x001100
#define MSR_P5_CESR_ES_CODE_TLB_MISS 0x001101
#define MSR_P5_CESR_ES_CODE_CACHE_MISS 0x001110
#define MSR_P5_CESR_ES_SEGMENT_LOADED 0x001111
#define MSR_P5_CESR_ES_BRANCHE 0x010010
#define MSR_P5_CESR_ES_BTB_HIT 0x010011
#define MSR_P5_CESR_ES_BRANCHE_BTB 0x010100
#define MSR_P5_CESR_ES_PIPELINE_FLUSH 0x010101
#define MSR_P5_CESR_ES_INSTRUCTION 0x010110
#define MSR_P5_CESR_ES_INSTRUCTION_V 0x010111
#define MSR_P5_CESR_ES_BUS_CYCLE 0x011000
#define MSR_P5_CESR_ES_FULL_WRITE_BUF 0x011001
#define MSR_P5_CESR_ES_DATA_MEM_READ 0x011010
#define MSR_P5_CESR_ES_WRITE_EM 0x011011
#define MSR_P5_CESR_ES_LOCKED_CYCLE 0x011100
#define MSR_P5_CESR_ES_IO_CYCLE 0x011101
#define MSR_P5_CESR_ES_NON_CACHEABLE 0x011110
#define MSR_P5_CESR_ES_AGI 0x011111
#define MSR_P5_CESR_ES_FLOP 0x100010
#define MSR_P5_CESR_ES_BREAK_DR0 0x100011
#define MSR_P5_CESR_ES_BREAK_DR1 0x100100
#define MSR_P5_CESR_ES_BREAK_DR2 0x100101
#define MSR_P5_CESR_ES_BREAK_DR3 0x100110
#define MSR_P5_CESR_ES_HARDWARE_IT 0x100111
#define CR0_PG 0x80000000
#define CR0_CD 0x40000000
#define CR0_NW 0x20000000
#define CR0_AM 0x00040000
#define CR0_WP 0x00010000
#define CR0_NE 0x00000020
#define CR0_ET 0x00000010
#define CR0_TS 0x00000008
#define CR0_EM 0x00000004
#define CR0_MP 0x00000002
#define CR0_PE 0x00000001
#define CR4_MCE 0x00000040
#define CR4_PSE 0x00000010
#define CR4_DE 0x00000008
#define CR4_TSD 0x00000004
#define CR4_PVI 0x00000002
#define CR4_VME 0x00000001
#ifndef ASSEMBLER
extern unsigned int get_cr0(void);
extern void set_cr0(
unsigned int value);
extern unsigned int get_cr2(void);
extern unsigned int get_cr3(void);
extern void set_cr3(
unsigned int value);
extern unsigned int get_cr4(void);
extern void set_cr4(
unsigned int value);
#define set_ts() \
set_cr0(get_cr0() | CR0_TS)
extern void clear_ts(void);
extern unsigned short get_tr(void);
extern void set_tr(
unsigned int seg);
extern unsigned short get_ldt(void);
extern void set_ldt(
unsigned int seg);
#ifdef __GNUC__
extern __inline__ unsigned int get_cr0(void)
{
register unsigned int cr0;
__asm__ volatile("mov %%cr0, %0" : "=r" (cr0));
return(cr0);
}
extern __inline__ void set_cr0(unsigned int value)
{
__asm__ volatile("mov %0, %%cr0" : : "r" (value));
}
extern __inline__ unsigned int get_cr2(void)
{
register unsigned int cr2;
__asm__ volatile("mov %%cr2, %0" : "=r" (cr2));
return(cr2);
}
#if NCPUS > 1 && AT386
#else
extern __inline__ unsigned int get_cr3(void)
{
register unsigned int cr3;
__asm__ volatile("mov %%cr3, %0" : "=r" (cr3));
return(cr3);
}
extern __inline__ void set_cr3(unsigned int value)
{
__asm__ volatile("mov %0, %%cr3" : : "r" (value));
}
#endif
extern __inline__ void clear_ts(void)
{
__asm__ volatile("clts");
}
extern __inline__ unsigned short get_tr(void)
{
unsigned short seg;
__asm__ volatile("str %0" : "=rm" (seg));
return(seg);
}
extern __inline__ void set_tr(unsigned int seg)
{
__asm__ volatile("ltr %0" : : "rm" ((unsigned short)(seg)));
}
extern __inline__ unsigned short get_ldt(void)
{
unsigned short seg;
__asm__ volatile("sldt %0" : "=rm" (seg));
return(seg);
}
extern __inline__ void set_ldt(unsigned int seg)
{
__asm__ volatile("lldt %0" : : "rm" ((unsigned short)(seg)));
}
extern __inline__ void flush_tlb(void)
{
unsigned long cr3_temp;
__asm__ volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (cr3_temp) :: "memory");
}
extern __inline__ void invlpg(unsigned long addr)
{
__asm__ volatile("invlpg (%0)" :: "r" (addr) : "memory");
}
#endif
#endif
#endif