#ifndef GCC_SH_H
#define GCC_SH_H
#define TARGET_VERSION \
fputs (" (Hitachi SH)", stderr);
extern int code_for_indirect_jump_scratch;
#define TARGET_CPU_CPP_BUILTINS() \
do { \
builtin_define ("__sh__"); \
builtin_assert ("cpu=sh"); \
builtin_assert ("machine=sh"); \
switch ((int) sh_cpu) \
{ \
case PROCESSOR_SH1: \
builtin_define ("__sh1__"); \
break; \
case PROCESSOR_SH2: \
builtin_define ("__sh2__"); \
break; \
case PROCESSOR_SH2E: \
builtin_define ("__SH2E__"); \
break; \
case PROCESSOR_SH2A: \
builtin_define ("__SH2A__"); \
builtin_define (TARGET_SH2A_DOUBLE \
? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
: TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
: "__SH2A_NOFPU__"); \
break; \
case PROCESSOR_SH3: \
builtin_define ("__sh3__"); \
builtin_define ("__SH3__"); \
if (TARGET_HARD_SH4) \
builtin_define ("__SH4_NOFPU__"); \
break; \
case PROCESSOR_SH3E: \
builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
break; \
case PROCESSOR_SH4: \
builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
break; \
case PROCESSOR_SH4A: \
builtin_define ("__SH4A__"); \
builtin_define (TARGET_SH4 \
? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
: TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
: "__SH4_NOFPU__"); \
break; \
case PROCESSOR_SH5: \
{ \
builtin_define_with_value ("__SH5__", \
TARGET_SHMEDIA64 ? "64" : "32", 0); \
builtin_define_with_value ("__SHMEDIA__", \
TARGET_SHMEDIA ? "1" : "0", 0); \
if (! TARGET_FPU_DOUBLE) \
builtin_define ("__SH4_NOFPU__"); \
} \
} \
if (TARGET_FPU_ANY) \
builtin_define ("__SH_FPU_ANY__"); \
if (TARGET_FPU_DOUBLE) \
builtin_define ("__SH_FPU_DOUBLE__"); \
if (TARGET_HITACHI) \
builtin_define ("__HITACHI__"); \
builtin_define (TARGET_LITTLE_ENDIAN \
? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
} while (0)
#define CONDITIONAL_REGISTER_USAGE do \
{ \
int regno; \
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
if (! VALID_REGISTER_P (regno)) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
\
if (TARGET_SH5) \
{ \
call_used_regs[FIRST_GENERAL_REG + 8] \
= call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
call_really_used_regs[FIRST_GENERAL_REG + 8] \
= call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
} \
if (TARGET_SHMEDIA) \
{ \
regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
regno_reg_class[FIRST_FP_REG] = FP_REGS; \
} \
if (flag_pic) \
{ \
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
} \
\
if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
{ \
call_really_used_regs[MACH_REG] = 0; \
call_really_used_regs[MACL_REG] = 0; \
} \
for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
regno <= LAST_FP_REG; regno += 2) \
SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
if (TARGET_SHMEDIA) \
{ \
for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
if (! fixed_regs[regno] && call_really_used_regs[regno]) \
SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
} \
else \
for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
if (! fixed_regs[regno] && call_really_used_regs[regno]) \
SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
} while (0)
#define TARGET_ELF 0
#define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
#define TARGET_SH2A TARGET_HARD_SH2A
#define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
#define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
#define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
#define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
#define TARGET_SUPERSCALAR TARGET_HARD_SH4
#define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
#define TARGET_FPU_DOUBLE \
((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
#define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
#undef TARGET_SH4
#define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
#define TARGET_SH4A_ARCH TARGET_SH4A
#define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
#define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
#define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
#define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
#define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
#define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
#define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
(TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
&& ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT SELECT_SH1
#define SUPPORT_SH1 1
#define SUPPORT_SH2E 1
#define SUPPORT_SH4 1
#define SUPPORT_SH4_SINGLE 1
#define SUPPORT_SH2A 1
#define SUPPORT_SH2A_SINGLE 1
#endif
#define TARGET_DIVIDE_INV \
(sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
|| sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
|| sh_div_strategy == SH_DIV_INV_CALL \
|| sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
#define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
#define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
#define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
#define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
#define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
#define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
#define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
#define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
#define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
#define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
#define SELECT_SH1 (MASK_SH1)
#define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
#define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
| MASK_FPU_SINGLE)
#define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
| MASK_HARD_SH2A_DOUBLE \
| MASK_SH2 | MASK_SH1)
#define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
#define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
| MASK_SH1 | MASK_FPU_SINGLE)
#define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
| MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
| MASK_SH2 | MASK_SH1)
#define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
#define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
#define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
#define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
#define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
| SELECT_SH3)
#define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
#define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
#define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
#define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
#define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
#define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
#define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
#define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
#if SUPPORT_SH1
#define SUPPORT_SH2 1
#endif
#if SUPPORT_SH2
#define SUPPORT_SH3 1
#endif
#if SUPPORT_SH3
#define SUPPORT_SH4_NOFPU 1
#endif
#if SUPPORT_SH4_NOFPU
#define SUPPORT_SH4A_NOFPU 1
#define SUPPORT_SH4AL 1
#define SUPPORT_SH2A_NOFPU 1
#endif
#if SUPPORT_SH2E
#define SUPPORT_SH3E 1
#endif
#if SUPPORT_SH3E
#define SUPPORT_SH4_SINGLE_ONLY 1
#define SUPPORT_SH4A_SINGLE_ONLY 1
#define SUPPORT_SH2A_SINGLE_ONLY 1
#endif
#if SUPPORT_SH4
#define SUPPORT_SH4A 1
#endif
#if SUPPORT_SH4_SINGLE
#define SUPPORT_SH4A_SINGLE 1
#endif
#if SUPPORT_SH5_COMPAT
#define SUPPORT_SH5_32MEDIA 1
#endif
#if SUPPORT_SH5_COMPACT_NOFPU
#define SUPPORT_SH5_32MEDIA_NOFPU 1
#endif
#define SUPPORT_ANY_SH5_32MEDIA \
(SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
#define SUPPORT_ANY_SH5_64MEDIA \
(SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
#define SUPPORT_ANY_SH5 \
(SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
| MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
#ifndef TARGET_ENDIAN_DEFAULT
#define TARGET_ENDIAN_DEFAULT 0
#endif
#ifndef TARGET_OPT_DEFAULT
#define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
#endif
#define TARGET_DEFAULT \
(TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
#ifndef SH_MULTILIB_CPU_DEFAULT
#define SH_MULTILIB_CPU_DEFAULT "m1"
#endif
#if TARGET_ENDIAN_DEFAULT
#define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
#else
#define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
#endif
#define CPP_SPEC " %(subtarget_cpp_spec) "
#ifndef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC ""
#endif
#ifndef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#endif
#define EXTRA_SPECS \
{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
{ "link_emul_prefix", LINK_EMUL_PREFIX }, \
{ "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
{ "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
{ "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
{ "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
{ "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
{ "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
{ "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
SUBTARGET_EXTRA_SPECS
#if TARGET_CPU_DEFAULT & MASK_HARD_SH4
#define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
#else
#define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
#endif
#define SH_ASM_SPEC \
"%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
%(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
%{m2a:--isa=sh2a} \
%{m2a-single:--isa=sh2a} \
%{m2a-single-only:--isa=sh2a} \
%{m2a-nofpu:--isa=sh2a-nofpu} \
%{m5-compact*:--isa=SHcompact} \
%{m5-32media*:--isa=SHmedia --abi=32} \
%{m5-64media*:--isa=SHmedia --abi=64} \
%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
#define ASM_SPEC SH_ASM_SPEC
#ifndef SUBTARGET_ASM_ENDIAN_SPEC
#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
#define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
#else
#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
#endif
#endif
#if STRICT_NOFPU == 1
#if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
#define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
#else
#define SUBTARGET_ASM_ISA_SPEC \
"%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
#endif
#else
#define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
#endif
#ifndef SUBTARGET_ASM_SPEC
#define SUBTARGET_ASM_SPEC ""
#endif
#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
#define LINK_EMUL_PREFIX "sh%{!mb:l}"
#else
#define LINK_EMUL_PREFIX "sh%{ml:l}"
#endif
#if TARGET_CPU_DEFAULT & MASK_SH5
#if TARGET_CPU_DEFAULT & MASK_SH_E
#define LINK_DEFAULT_CPU_EMUL "32"
#if TARGET_CPU_DEFAULT & MASK_SH1
#define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
#else
#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
#endif
#else
#define LINK_DEFAULT_CPU_EMUL "64"
#define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
#endif
#define ASM_ISA_DEFAULT_SPEC \
" %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
#else
#define LINK_DEFAULT_CPU_EMUL ""
#define ASM_ISA_DEFAULT_SPEC ""
#endif
#define SUBTARGET_LINK_EMUL_SUFFIX ""
#define SUBTARGET_LINK_SPEC ""
#define LINK_SPEC SH_LINK_SPEC
#define SH_LINK_SPEC "\
-m %(link_emul_prefix)\
%{m5-compact*|m5-32media*:32}\
%{m5-64media*:64}\
%{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
%(subtarget_link_emul_suffix) \
%{mrelax:-relax} %(subtarget_link_spec)"
#ifndef SH_DIV_STR_FOR_SIZE
#define SH_DIV_STR_FOR_SIZE "call"
#endif
#define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
do { \
if (LEVEL) \
{ \
flag_omit_frame_pointer = -1; \
if (! SIZE) \
sh_div_str = "inv:minlat"; \
} \
if (SIZE) \
{ \
target_flags |= MASK_SMALLCODE; \
sh_div_str = SH_DIV_STR_FOR_SIZE ; \
} \
\
if (LEVEL > 1) \
{ \
flag_branch_target_load_optimize = 1; \
if (! (SIZE)) \
target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
} \
\
flag_finite_math_only = 2; \
\
if (flag_schedule_insns > 0) \
flag_schedule_insns = 2; \
} while (0)
#define ASSEMBLER_DIALECT assembler_dialect
extern int assembler_dialect;
enum sh_divide_strategy_e {
SH_DIV_CALL,
SH_DIV_CALL2,
SH_DIV_FP,
SH_DIV_INV,
SH_DIV_INV_MINLAT,
SH_DIV_INV20U,
SH_DIV_INV20L,
SH_DIV_INV_CALL,
SH_DIV_INV_CALL2,
SH_DIV_INV_FP,
SH_DIV_CALL_DIV1,
SH_DIV_CALL_FP,
SH_DIV_CALL_TABLE,
SH_DIV_INTRINSIC
};
extern enum sh_divide_strategy_e sh_div_strategy;
#ifndef SH_DIV_STRATEGY_DEFAULT
#define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
#endif
#define OVERRIDE_OPTIONS \
do { \
int regno; \
\
if (flag_finite_math_only == 2) \
flag_finite_math_only \
= !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
if (TARGET_SH2E && !flag_finite_math_only) \
target_flags |= MASK_IEEE; \
sh_cpu = CPU_SH1; \
assembler_dialect = 0; \
if (TARGET_SH2) \
sh_cpu = CPU_SH2; \
if (TARGET_SH2E) \
sh_cpu = CPU_SH2E; \
if (TARGET_SH2A) \
{ \
sh_cpu = CPU_SH2A; \
if (TARGET_SH2A_DOUBLE) \
target_flags |= MASK_FMOVD; \
} \
if (TARGET_SH3) \
sh_cpu = CPU_SH3; \
if (TARGET_SH3E) \
sh_cpu = CPU_SH3E; \
if (TARGET_SH4) \
{ \
assembler_dialect = 1; \
sh_cpu = CPU_SH4; \
} \
if (TARGET_SH4A_ARCH) \
{ \
assembler_dialect = 1; \
sh_cpu = CPU_SH4A; \
} \
if (TARGET_SH5) \
{ \
sh_cpu = CPU_SH5; \
target_flags |= MASK_ALIGN_DOUBLE; \
if (TARGET_SHMEDIA_FPU) \
target_flags |= MASK_FMOVD; \
if (TARGET_SHMEDIA) \
{ \
\
flag_delayed_branch = 0; \
\
target_flags &= ~MASK_RELAX; \
\
flag_if_conversion2 = 0; \
if (! strcmp (sh_div_str, "call")) \
sh_div_strategy = SH_DIV_CALL; \
else if (! strcmp (sh_div_str, "call2")) \
sh_div_strategy = SH_DIV_CALL2; \
if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
sh_div_strategy = SH_DIV_FP; \
else if (! strcmp (sh_div_str, "inv")) \
sh_div_strategy = SH_DIV_INV; \
else if (! strcmp (sh_div_str, "inv:minlat")) \
sh_div_strategy = SH_DIV_INV_MINLAT; \
else if (! strcmp (sh_div_str, "inv20u")) \
sh_div_strategy = SH_DIV_INV20U; \
else if (! strcmp (sh_div_str, "inv20l")) \
sh_div_strategy = SH_DIV_INV20L; \
else if (! strcmp (sh_div_str, "inv:call2")) \
sh_div_strategy = SH_DIV_INV_CALL2; \
else if (! strcmp (sh_div_str, "inv:call")) \
sh_div_strategy = SH_DIV_INV_CALL; \
else if (! strcmp (sh_div_str, "inv:fp")) \
{ \
if (TARGET_FPU_ANY) \
sh_div_strategy = SH_DIV_INV_FP; \
else \
sh_div_strategy = SH_DIV_INV; \
} \
} \
\
if (profile_flag) \
warning (0, "profiling is still experimental for this target");\
} \
else \
{ \
\
targetm.asm_out.aligned_op.di = NULL; \
targetm.asm_out.unaligned_op.di = NULL; \
} \
if (TARGET_SH1) \
{ \
if (! strcmp (sh_div_str, "call-div1")) \
sh_div_strategy = SH_DIV_CALL_DIV1; \
else if (! strcmp (sh_div_str, "call-fp") \
&& (TARGET_FPU_DOUBLE \
|| (TARGET_HARD_SH4 && TARGET_SH2E) \
|| (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
sh_div_strategy = SH_DIV_CALL_FP; \
else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2) \
sh_div_strategy = SH_DIV_CALL_TABLE; \
else \
\
\
\
if (TARGET_HARD_SH4) \
sh_div_strategy = SH_DIV_CALL_TABLE; \
\
else if (TARGET_SH2A) \
sh_div_strategy = SH_DIV_INTRINSIC; \
\
else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
sh_div_strategy = SH_DIV_CALL_FP; \
\
else if (TARGET_SH2) \
sh_div_strategy = SH_DIV_CALL_TABLE; \
else \
sh_div_strategy = SH_DIV_CALL_DIV1; \
} \
if (!TARGET_SH1) \
TARGET_PRETEND_CMOVE = 0; \
if (sh_divsi3_libfunc[0]) \
; \
else if (TARGET_DIVIDE_CALL_FP) \
sh_divsi3_libfunc = "__sdivsi3_i4"; \
else if (TARGET_DIVIDE_CALL_TABLE) \
sh_divsi3_libfunc = "__sdivsi3_i4i"; \
else if (TARGET_SH5) \
sh_divsi3_libfunc = "__sdivsi3_1"; \
else \
sh_divsi3_libfunc = "__sdivsi3"; \
if (TARGET_FMOVD) \
reg_class_from_letter['e' - 'a'] = NO_REGS; \
\
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
if (! VALID_REGISTER_P (regno)) \
sh_register_names[regno][0] = '\0'; \
\
for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
sh_additional_register_names[regno][0] = '\0'; \
\
if (flag_omit_frame_pointer < 0) \
{ \
\
if (0) \
flag_omit_frame_pointer \
= (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
else \
flag_omit_frame_pointer = 0; \
} \
\
if ((flag_pic && ! TARGET_PREFERGOT) \
|| (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
flag_no_function_cse = 1; \
\
if (SMALL_REGISTER_CLASSES) \
{ \
\
\
if (!TARGET_HARD_SH4) \
flag_schedule_insns = 0; \
\
else if (flag_exceptions) \
{ \
if (flag_schedule_insns == 1) \
warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
flag_schedule_insns = 0; \
} \
} \
\
if (align_loops == 0) \
align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
if (align_jumps == 0) \
align_jumps = 1 << CACHE_LOG; \
else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
align_jumps = TARGET_SHMEDIA ? 4 : 2; \
\
\
if (align_functions == 0) \
align_functions \
= TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
\
if (TARGET_RELAX) \
{ \
int min_align \
= align_loops > align_jumps ? align_loops : align_jumps; \
\
\
if (min_align < 4) \
min_align = 4; \
if (align_functions < min_align) \
align_functions = min_align; \
} \
} while (0)
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
#if defined(__LITTLE_ENDIAN__)
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#else
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#endif
#define MAX_BITS_PER_WORD 64
#define INT_TYPE_SIZE 32
#define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
#define LONG_LONG_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE 64
#define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
#define MIN_UNITS_PER_WORD 4
#define DWARF_CIE_DATA_ALIGNMENT -4
#define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
#define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
#define STACK_BOUNDARY BIGGEST_ALIGNMENT
#define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
#define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
#define TARGET_PTRMEMFUNC_VBIT_LOCATION \
(TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
#define EMPTY_FIELD_BOUNDARY 32
#define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
#define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
((TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < FASTEST_ALIGNMENT) \
? FASTEST_ALIGNMENT : (ALIGN))
#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
|| GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
: (unsigned) ALIGN)
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(TREE_CODE (TYPE) == ARRAY_TYPE \
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
&& (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
#define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
#define STRICT_ALIGNMENT 1
#define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
barrier_align (LABEL_AFTER_BARRIER)
#define LOOP_ALIGN(A_LABEL) \
((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
? 0 : sh_loop_align (A_LABEL))
#define LABEL_ALIGN(A_LABEL) \
( \
(PREV_INSN (A_LABEL) \
&& GET_CODE (PREV_INSN (A_LABEL)) == INSN \
&& GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
&& XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
\
? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
: 0)
#define ADDR_VEC_ALIGN(ADDR_VEC) 2
#define INSN_LENGTH_ALIGNMENT(A_INSN) \
(GET_CODE (A_INSN) == INSN \
? 1 << TARGET_SHMEDIA \
: GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
? 1 << TARGET_SHMEDIA \
: CACHE_LOG)
#define MAX_REGISTER_NAME_LENGTH 5
extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
#define SH_REGISTER_NAMES_INITIALIZER \
{ \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
"r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
"fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
"fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
"fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
"fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
"fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
"fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
"tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
"xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
"rap", "sfp" \
}
#define REGNAMES_ARR_INDEX_1(index) \
(sh_register_names[index])
#define REGNAMES_ARR_INDEX_2(index) \
REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
#define REGNAMES_ARR_INDEX_4(index) \
REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
#define REGNAMES_ARR_INDEX_8(index) \
REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
#define REGNAMES_ARR_INDEX_16(index) \
REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
#define REGNAMES_ARR_INDEX_32(index) \
REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
#define REGNAMES_ARR_INDEX_64(index) \
REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
#define REGISTER_NAMES \
{ \
REGNAMES_ARR_INDEX_64 (0), \
REGNAMES_ARR_INDEX_64 (64), \
REGNAMES_ARR_INDEX_8 (128), \
REGNAMES_ARR_INDEX_8 (136), \
REGNAMES_ARR_INDEX_8 (144), \
REGNAMES_ARR_INDEX_2 (152) \
}
#define ADDREGNAMES_SIZE 32
#define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
[MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
#define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
{ \
"dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
"dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
"dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
"dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
}
#define ADDREGNAMES_REGNO(index) \
((index < 32) ? (FIRST_FP_REG + (index) * 2) \
: (-1))
#define ADDREGNAMES_ARR_INDEX_1(index) \
{ (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
#define ADDREGNAMES_ARR_INDEX_2(index) \
ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
#define ADDREGNAMES_ARR_INDEX_4(index) \
ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
#define ADDREGNAMES_ARR_INDEX_8(index) \
ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
#define ADDREGNAMES_ARR_INDEX_16(index) \
ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
#define ADDREGNAMES_ARR_INDEX_32(index) \
ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
#define ADDITIONAL_REGISTER_NAMES \
{ \
ADDREGNAMES_ARR_INDEX_32 (0) \
}
#define FIRST_GENERAL_REG R0_REG
#define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
#define FIRST_FP_REG DR0_REG
#define LAST_FP_REG (FIRST_FP_REG + \
(TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
#define FIRST_XD_REG XD0_REG
#define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
#define FIRST_TARGET_REG TR0_REG
#define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
#define GENERAL_REGISTER_P(REGNO) \
IN_RANGE ((REGNO), \
(unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
(unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
#define GENERAL_OR_AP_REGISTER_P(REGNO) \
(GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
|| ((REGNO) == FRAME_POINTER_REGNUM))
#define FP_REGISTER_P(REGNO) \
((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
#define XD_REGISTER_P(REGNO) \
((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
#define FP_OR_XD_REGISTER_P(REGNO) \
(FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
#define FP_ANY_REGISTER_P(REGNO) \
(FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
#define SPECIAL_REGISTER_P(REGNO) \
((REGNO) == GBR_REG || (REGNO) == T_REG \
|| (REGNO) == MACH_REG || (REGNO) == MACL_REG)
#define TARGET_REGISTER_P(REGNO) \
((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
#define SHMEDIA_REGISTER_P(REGNO) \
(GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
|| TARGET_REGISTER_P (REGNO))
#define VALID_REGISTER_P(REGNO) \
(SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
|| (REGNO) == AP_REG || (REGNO) == RAP_REG \
|| (REGNO) == FRAME_POINTER_REGNUM \
|| (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
|| (TARGET_SH2E && (REGNO) == FPUL_REG))
#define REGISTER_NATURAL_MODE(REGNO) \
(FP_REGISTER_P (REGNO) ? SFmode \
: XD_REGISTER_P (REGNO) ? DFmode \
: TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
? DImode \
: SImode)
#define FIRST_PSEUDO_REGISTER 154
#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
#define FIXED_REGISTERS \
{ \
\
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, \
\
1, 0, 0, 0, 0, 0, 0, 0, \
\
\
1, 1, 1, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, \
\
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
\
0, 0, 0, 0, 0, 0, 0, 0, \
\
0, 0, 0, 0, 0, 0, 0, 0, \
\
1, 1, 1, 1, 1, 1, 0, 1, \
\
1, 1, \
}
#define CALL_USED_REGISTERS \
{ \
\
1, 1, 1, 1, 1, 1, 1, 1, \
\
0, 0, 0, 0, 0, 0, 0, 1, \
1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 1, 1, 1, \
1, 1, 1, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
\
1, 1, 1, 1, 1, 0, 0, 0, \
\
1, 1, 1, 1, 1, 1, 0, 0, \
\
1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, \
}
#define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
(TARGET_SHMEDIA32 \
&& GET_MODE_SIZE (MODE) > 4 \
&& (((REGNO) >= FIRST_GENERAL_REG + 10 \
&& (REGNO) <= FIRST_GENERAL_REG + 15) \
|| TARGET_REGISTER_P (REGNO) \
|| (REGNO) == PR_MEDIA_REG))
#define HARD_REGNO_NREGS(REGNO, MODE) \
(XD_REGISTER_P (REGNO) \
? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
: (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
: (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
: FP_REGISTER_P (REGNO) && (MODE) == SFmode \
? 1 \
: (MODE) == V2SFmode \
? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
|| GENERAL_REGISTER_P (REGNO)) \
: (MODE) == V4SFmode \
? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
|| GENERAL_REGISTER_P (REGNO)) \
: (MODE) == V16SFmode \
? (TARGET_SHMEDIA \
? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
: (REGNO) == FIRST_XD_REG) \
: FP_REGISTER_P (REGNO) \
? ((MODE) == SFmode || (MODE) == SImode \
|| ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
|| ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
|| (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
|| (MODE) == V2SFmode || (MODE) == TImode))) \
&& (((REGNO) - FIRST_FP_REG) & 1) == 0) \
|| ((TARGET_SH4 || TARGET_SHMEDIA) \
&& (MODE) == TImode \
&& (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
: XD_REGISTER_P (REGNO) \
? (MODE) == DFmode \
: TARGET_REGISTER_P (REGNO) \
? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
: (REGNO) == PR_REG ? (MODE) == SImode \
: (REGNO) == FPSCR_REG ? (MODE) == PSImode \
: 1)
#define MODES_TIEABLE_P(MODE1, MODE2) \
((MODE1) == (MODE2) \
|| (TARGET_SHMEDIA \
&& GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
&& INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
|| (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
&& (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
&& (GET_MODE_SIZE (MODE2) <= 4)) \
: ((MODE1) != SFmode && (MODE2) != SFmode))))
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
#define STACK_POINTER_REGNUM SP_REG
#define HARD_FRAME_POINTER_REGNUM FP_REG
#define FRAME_POINTER_REGNUM 153
#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
#define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
#define FRAME_POINTER_REQUIRED 0
#define ELIMINABLE_REGS \
{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{ RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
#define CAN_ELIMINATE(FROM, TO) \
(!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
OFFSET = initial_elimination_offset ((FROM), (TO))
#define ARG_POINTER_REGNUM AP_REG
#define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
#define DEFAULT_PCC_STRUCT_RETURN 0
#define SHMEDIA_REGS_STACK_ADJUST() \
(TARGET_SHCOMPACT && current_function_has_nonlocal_label \
? (8 * ( 8 + 16 + 3) \
+ (TARGET_FPU_ANY ? 4 * ( 28) : 0)) \
: 0)
enum reg_class
{
NO_REGS,
R0_REGS,
PR_REGS,
T_REGS,
MAC_REGS,
FPUL_REGS,
SIBCALL_REGS,
GENERAL_REGS,
FP0_REGS,
FP_REGS,
DF_HI_REGS,
DF_REGS,
FPSCR_REGS,
GENERAL_FP_REGS,
GENERAL_DF_REGS,
TARGET_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"R0_REGS", \
"PR_REGS", \
"T_REGS", \
"MAC_REGS", \
"FPUL_REGS", \
"SIBCALL_REGS", \
"GENERAL_REGS", \
"FP0_REGS", \
"FP_REGS", \
"DF_HI_REGS", \
"DF_REGS", \
"FPSCR_REGS", \
"GENERAL_FP_REGS", \
"GENERAL_DF_REGS", \
"TARGET_REGS", \
"ALL_REGS", \
}
#define REG_CLASS_CONTENTS \
{ \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
\
{ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
\
{ 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
\
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
\
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
\
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
\
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
\
{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
\
{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
\
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
\
{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
}
extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
#define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
#define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
#define REG_ALLOC_ORDER \
{ \
65, 66, 67, 68, 69, 70, 71, 64, \
72, 73, 74, 75, 80, 81, 82, 83, \
84, 85, 86, 87, 88, 89, 90, 91, \
92, 93, 94, 95, 96, 97, 98, 99, \
\
76, 77, 78, 79,100,101,102,103, \
104,105,106,107,108,109,110,111, \
112,113,114,115,116,117,118,119, \
120,121,122,123,124,125,126,127, \
136,137,138,139,140,141,142,143, \
151, \
\
1, 2, 3, 7, 6, 5, 4, 0, \
8, 9, 17, 19, 20, 21, 22, 23, \
36, 37, 38, 39, 40, 41, 42, 43, \
60, 61, 62, \
\
10, 11, 12, 13, 14, 18, \
\
28, 29, 30, 31, 32, 33, 34, 35, \
44, 45, 46, 47, 48, 49, 50, 51, \
52, 53, 54, 55, 56, 57, 58, 59, \
150, \
\
128,129,130,131,132,133,134,135, \
\
15, 16, 24, 25, 26, 27, 63,144, \
145,146,147,148,149,152,153 }
#define INDEX_REG_CLASS \
(!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
#define BASE_REG_CLASS GENERAL_REGS
extern enum reg_class reg_class_from_letter[];
#define REG_CLASS_FROM_CONSTRAINT(C, STR) \
(ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
#define CONSTRAINT_LEN(C,STR) \
(((C) == 'A' || (C) == 'B' || (C) == 'C' \
|| (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
|| (C) == 'R' || (C) == 'S') \
? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
#define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
&& ((HOST_WIDE_INT)(VALUE)) <= 31)
#define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
&& ((HOST_WIDE_INT)(VALUE)) <= 127)
#define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
&& ((HOST_WIDE_INT)(VALUE)) <= 511)
#define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
&& ((HOST_WIDE_INT)(VALUE)) <= 32767)
#define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
&& ((HOST_WIDE_INT)(VALUE)) <= 524287 \
&& TARGET_SH2A)
#define CONST_OK_FOR_I(VALUE, STR) \
((STR)[1] == '0' && (STR)[2] == '6' ? CONST_OK_FOR_I06 (VALUE) \
: (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
: (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
: (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
: (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
: 0)
#define CONST_OK_FOR_J16(VALUE) \
((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
|| (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
#define CONST_OK_FOR_J(VALUE, STR) \
((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
: 0)
#define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
&& ((HOST_WIDE_INT)(VALUE)) <= 255)
#define CONST_OK_FOR_K16(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
&& ((HOST_WIDE_INT)(VALUE)) <= 65535)
#define CONST_OK_FOR_K(VALUE, STR) \
((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
: (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_K16 (VALUE) \
: 0)
#define CONST_OK_FOR_P27(VALUE) \
((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
#define CONST_OK_FOR_P(VALUE, STR) \
((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
: 0)
#define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
#define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
: (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
: (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
: (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
: (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
: (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
: 0)
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
: (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
: (C) == 'F')
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
((CLASS) == NO_REGS && TARGET_SHMEDIA \
&& (GET_CODE (X) == CONST_DOUBLE \
|| GET_CODE (X) == SYMBOL_REF \
|| PIC_DIRECT_ADDR_P (X)) \
? GENERAL_REGS \
: (CLASS)) \
#if 0
#define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
((((REGCLASS_HAS_FP_REG (CLASS) \
&& (GET_CODE (X) == REG \
&& (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
|| (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
&& TARGET_FMOVD)))) \
|| (REGCLASS_HAS_GENERAL_REG (CLASS) \
&& GET_CODE (X) == REG \
&& FP_REGISTER_P (REGNO (X)))) \
&& ! TARGET_SHMEDIA \
&& ((MODE) == SFmode || (MODE) == SImode)) \
? FPUL_REGS \
: (((CLASS) == FPUL_REGS \
|| (REGCLASS_HAS_FP_REG (CLASS) \
&& ! TARGET_SHMEDIA && MODE == SImode)) \
&& (GET_CODE (X) == MEM \
|| (GET_CODE (X) == REG \
&& (REGNO (X) >= FIRST_PSEUDO_REGISTER \
|| REGNO (X) == T_REG \
|| system_reg_operand (X, VOIDmode))))) \
? GENERAL_REGS \
: (((CLASS) == TARGET_REGS \
|| (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
&& !EXTRA_CONSTRAINT_Csy (X) \
&& (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
? GENERAL_REGS \
: (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
&& GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
&& (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
? GENERAL_REGS \
: ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
&& TARGET_REGISTER_P (REGNO (X))) \
? GENERAL_REGS : (ELSE))
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
((REGCLASS_HAS_FP_REG (CLASS) \
&& ! TARGET_SHMEDIA \
&& immediate_operand ((X), (MODE)) \
&& ! ((fp_zero_operand (X) || fp_one_operand (X)) \
&& (MODE) == SFmode && fldi_ok ())) \
? R0_REGS \
: ((CLASS) == FPUL_REGS \
&& ((GET_CODE (X) == REG \
&& (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
|| REGNO (X) == T_REG)) \
|| GET_CODE (X) == PLUS)) \
? GENERAL_REGS \
: (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
? GENERAL_REGS \
: R0_REGS) \
: ((CLASS) == FPSCR_REGS \
&& ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
|| (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
? GENERAL_REGS \
: (REGCLASS_HAS_FP_REG (CLASS) \
&& TARGET_SHMEDIA \
&& immediate_operand ((X), (MODE)) \
&& (X) != CONST0_RTX (GET_MODE (X)) \
&& GET_MODE (X) != V4SFmode) \
? GENERAL_REGS \
: (((MODE) == QImode || (MODE) == HImode) \
&& TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
? GENERAL_REGS \
: (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
&& (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
? TARGET_REGS \
: SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
#else
#define HAVE_SECONDARY_RELOADS
#endif
#define CLASS_MAX_NREGS(CLASS, MODE) \
(TARGET_SHMEDIA \
&& TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
sh_cannot_change_mode_class (FROM, TO, CLASS)
#define NPARM_REGS(MODE) \
(TARGET_FPU_ANY && (MODE) == SFmode \
? (TARGET_SH5 ? 12 : 8) \
: (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
? (TARGET_SH5 ? 12 : 8) \
: (TARGET_SH5 ? 8 : 4))
#define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
#define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
#define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
#define FIRST_FP_RET_REG FIRST_FP_REG
#define STACK_GROWS_DOWNWARD
#define FRAME_GROWS_DOWNWARD 1
#define STARTING_FRAME_OFFSET 0
#if 0
#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
#endif
#define FIRST_PARM_OFFSET(FNDECL) 0
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
#define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
#define BASE_RETURN_VALUE_REG(MODE) \
((TARGET_FPU_ANY && ((MODE) == SFmode)) \
? FIRST_FP_RET_REG \
: TARGET_FPU_ANY && (MODE) == SCmode \
? FIRST_FP_RET_REG \
: (TARGET_FPU_DOUBLE \
&& ((MODE) == DFmode || (MODE) == SFmode \
|| (MODE) == DCmode || (MODE) == SCmode )) \
? FIRST_FP_RET_REG \
: FIRST_RET_REG)
#define BASE_ARG_REG(MODE) \
((TARGET_SH2E && ((MODE) == SFmode)) \
? FIRST_FP_PARM_REG \
: (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
? FIRST_FP_PARM_REG \
: FIRST_PARM_REG)
#define FUNCTION_VALUE(VALTYPE, FUNC) \
gen_rtx_REG ( \
((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
&& GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
&& (TREE_CODE (VALTYPE) == INTEGER_TYPE \
|| TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
|| TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
|| TREE_CODE (VALTYPE) == REAL_TYPE \
|| TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
&& sh_promote_prototypes (VALTYPE) \
? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
#define LIBCALL_VALUE(MODE) \
gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
#define FUNCTION_VALUE_REGNO_P(REGNO) \
((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
|| (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
#define FUNCTION_ARG_REGNO_P(REGNO) \
(((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
&& (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
|| (TARGET_FPU_ANY \
&& (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
&& (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
+ NPARM_REGS (SFmode))))
enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
struct sh_args {
int arg_count[2];
int force_mem;
int prototype_p;
int free_single_fp_reg;
int outgoing;
int stack_regs;
int byref_regs;
int byref;
#define CALL_COOKIE_RET_TRAMP_SHIFT 0
#define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
#define CALL_COOKIE_STACKSEQ_SHIFT 1
#define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
#define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
(((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
#define CALL_COOKIE_INT_REG_SHIFT(REG) \
(4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
#define CALL_COOKIE_INT_REG(REG, VAL) \
((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
#define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
(((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
long call_cookie;
int renesas_abi;
};
#define CUMULATIVE_ARGS struct sh_args
#define GET_SH_ARG_CLASS(MODE) \
((TARGET_FPU_ANY && (MODE) == SFmode) \
? SH_ARG_FLOAT \
\
: TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
? SH_ARG_INT \
: TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
? SH_ARG_FLOAT : SH_ARG_INT)
#define ROUND_ADVANCE(SIZE) \
(((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define ROUND_REG(CUM, MODE) \
(((TARGET_ALIGN_DOUBLE \
|| ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
&& (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
&& GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
+ ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
: (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
#define PASS_IN_REG_P(CUM, MODE, TYPE) \
(((TYPE) == 0 \
|| (! TREE_ADDRESSABLE ((tree)(TYPE)) \
&& (! (TARGET_HITACHI || (CUM).renesas_abi) \
|| ! (AGGREGATE_TYPE_P (TYPE) \
|| (!TARGET_FPU_ANY \
&& (GET_MODE_CLASS (MODE) == MODE_FLOAT \
&& GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
&& ! (CUM).force_mem \
&& (TARGET_SH2E \
? ((MODE) == BLKmode \
? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
+ int_size_in_bytes (TYPE)) \
<= NPARM_REGS (SImode) * UNITS_PER_WORD) \
: ((ROUND_REG((CUM), (MODE)) \
+ HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
<= NPARM_REGS (MODE))) \
: ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
#define FUNCTION_ARG_SCmode_WART 1
#define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
((MODE) == BLKmode \
&& TARGET_SHCOMPACT \
&& ! TARGET_LITTLE_ENDIAN \
&& int_size_in_bytes (TYPE) > 4 \
&& int_size_in_bytes (TYPE) < 8)
#define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
#define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
(gen_rtx_PARALLEL \
((MODE), \
gen_rtvec (2, \
gen_rtx_EXPR_LIST \
(VOIDmode, \
((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
+ (CUM).arg_count[(int) SH_ARG_FLOAT]) \
: NULL_RTX), \
const0_rtx), \
gen_rtx_EXPR_LIST \
(VOIDmode, \
((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
? gen_rtx_REG ((MODE), FIRST_PARM_REG \
+ (CUM).arg_count[(int) SH_ARG_INT]) \
: gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
+ (CUM).arg_count[(int) SH_ARG_FLOAT])), \
const0_rtx))))
#define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
? gen_rtx_REG ((MODE), (REG)) \
: gen_rtx_PARALLEL ((MODE), \
gen_rtvec (2, \
gen_rtx_EXPR_LIST \
(VOIDmode, NULL_RTX, \
const0_rtx), \
gen_rtx_EXPR_LIST \
(VOIDmode, gen_rtx_REG ((MODE), \
(REG)), \
const0_rtx))))
#define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
(TARGET_SH5 \
&& ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
|| (MODE) == DCmode) \
&& ((CUM).arg_count[(int) SH_ARG_INT] \
+ (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
: GET_MODE_SIZE (MODE)) \
+ 7) / 8) > NPARM_REGS (SImode))
#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
sh_va_start (valist, nextarg)
#define FUNCTION_PROFILER(STREAM,LABELNO) \
{ \
if (TARGET_SHMEDIA) \
{ \
fprintf((STREAM), "\tmovi\t33,r0\n"); \
fprintf((STREAM), "\ttrapa\tr0\n"); \
asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
} \
else \
{ \
fprintf((STREAM), "\t.align\t2\n"); \
fprintf((STREAM), "\ttrapa\t#33\n"); \
fprintf((STREAM), "\t.align\t2\n"); \
asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
} \
}
#define PROFILE_BEFORE_PROLOGUE
#define EXIT_IGNORE_STACK 1
#define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
#define TRAMPOLINE_ALIGNMENT \
((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
: TARGET_SHMEDIA ? 256 : 64)
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
#define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
{ \
if (TARGET_SHMEDIA) \
(TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
gen_reg_rtx (Pmode), 0, \
OPTAB_LIB_WIDEN); \
} while (0)
#define RETURN_ADDR_RTX(COUNT, FRAME) \
(((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
#define INCOMING_RETURN_ADDR_RTX \
gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
#define HAVE_POST_INCREMENT TARGET_SH1
#define HAVE_PRE_DECREMENT TARGET_SH1
#define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
? 0 : TARGET_SH1)
#define USE_LOAD_PRE_DECREMENT(mode) 0
#define USE_STORE_POST_INCREMENT(mode) 0
#define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
? 0 : TARGET_SH1)
#define MOVE_BY_PIECES_P(SIZE, ALIGN) \
(move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
< (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
#define STORE_BY_PIECES_P(SIZE, ALIGN) \
(move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
< (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
#define REGNO_OK_FOR_BASE_P(REGNO) \
(GENERAL_OR_AP_REGISTER_P (REGNO) \
|| GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
#define REGNO_OK_FOR_INDEX_P(REGNO) \
(TARGET_SHMEDIA \
? (GENERAL_REGISTER_P (REGNO) \
|| GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
: (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
#define MAX_REGS_PER_ADDRESS 2
#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
#define LEGITIMATE_CONSTANT_P(X) \
(TARGET_SHMEDIA \
? ((GET_MODE (X) != DFmode \
&& GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
|| (X) == CONST0_RTX (GET_MODE (X)) \
|| ! TARGET_SHMEDIA_FPU \
|| TARGET_SHMEDIA64) \
: (GET_CODE (X) != CONST_DOUBLE \
|| GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
|| (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
#ifndef REG_OK_STRICT
#define REG_OK_FOR_BASE_P(X) \
(GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
#define REG_OK_FOR_INDEX_P(X) \
((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
: REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
: REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
#else
#define REG_OK_FOR_BASE_P(X) \
REGNO_OK_FOR_BASE_P (REGNO (X))
#define REG_OK_FOR_INDEX_P(X) \
REGNO_OK_FOR_INDEX_P (REGNO (X))
#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
(REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
#endif
#define EXTRA_CONSTRAINT_Q(OP) \
(GET_CODE (OP) == MEM \
&& ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
|| (GET_CODE (XEXP ((OP), 0)) == CONST \
&& GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
&& GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
&& GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
#define EXTRA_CONSTRAINT_A(OP, STR) 0
#define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
#define EXTRA_CONSTRAINT_B(OP, STR) \
((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
: 0)
#define EXTRA_CONSTRAINT_Css(OP) \
(GET_CODE (OP) == CONST \
&& GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
&& (GET_MODE (XEXP ((OP), 0)) == DImode \
|| GET_MODE (XEXP ((OP), 0)) == SImode) \
&& GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
&& GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
&& (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
|| (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
&& (MOVI_SHORI_BASE_OPERAND_P \
(XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
&& GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
1)) == CONST_INT)))
#define EXTRA_CONSTRAINT_Csu(OP) \
(GET_CODE (OP) == CONST \
&& GET_CODE (XEXP ((OP), 0)) == ZERO_EXTEND \
&& (GET_MODE (XEXP ((OP), 0)) == DImode \
|| GET_MODE (XEXP ((OP), 0)) == SImode) \
&& GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
&& GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
&& (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
|| (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
&& (MOVI_SHORI_BASE_OPERAND_P \
(XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
&& GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
1)) == CONST_INT)))
#define DATALABEL_REF_NO_CONST_P(OP) \
(GET_CODE (OP) == UNSPEC \
&& XINT ((OP), 1) == UNSPEC_DATALABEL \
&& XVECLEN ((OP), 0) == 1 \
&& GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
#define GOT_ENTRY_P(OP) \
(GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
&& XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
#define GOTPLT_ENTRY_P(OP) \
(GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
&& XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
#define UNSPEC_GOTOFF_P(OP) \
(GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
#define GOTOFF_P(OP) \
(GET_CODE (OP) == CONST \
&& (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
|| (GET_CODE (XEXP ((OP), 0)) == PLUS \
&& UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
&& GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
#define PIC_ADDR_P(OP) \
(GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
&& XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
#define PIC_OFFSET_P(OP) \
(PIC_ADDR_P (OP) \
&& GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
&& reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
#define PIC_DIRECT_ADDR_P(OP) \
(PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
#define NON_PIC_REFERENCE_P(OP) \
(GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
|| (GET_CODE (OP) == CONST \
&& (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
|| GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
|| DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
|| (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
&& (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
|| GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
|| DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
&& GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
#define PIC_REFERENCE_P(OP) \
(GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
|| GOTOFF_P (OP) || PIC_ADDR_P (OP))
#define MOVI_SHORI_BASE_OPERAND_P(OP) \
(flag_pic \
? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
|| PIC_OFFSET_P (OP)) \
: NON_PIC_REFERENCE_P (OP))
#define EXTRA_CONSTRAINT_Csy(OP) \
(NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
#define EXTRA_CONSTRAINT_Z(OP) \
((OP) == CONST0_RTX (GET_MODE (OP)))
#define EXTRA_CONSTRAINT_W(OP) \
(GET_CODE (OP) == CONST_VECTOR \
&& (sh_rep_vec ((OP), VOIDmode) \
|| (HOST_BITS_PER_WIDE_INT >= 64 \
? sh_const_vec ((OP), VOIDmode) \
: sh_1el_vec ((OP), VOIDmode))))
#define EXTRA_CONSTRAINT_Cpg(OP) \
(CONSTANT_P (OP) \
&& GET_CODE (OP) != CONST_INT \
&& GET_CODE (OP) != CONST_DOUBLE \
&& (!flag_pic \
|| (LEGITIMATE_PIC_OPERAND_P (OP) \
&& (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
&& GET_CODE (OP) != LABEL_REF)))
#define EXTRA_CONSTRAINT_C(OP, STR) \
((STR)[1] == 's' && (STR)[2] == 's' ? EXTRA_CONSTRAINT_Css (OP) \
: (STR)[1] == 's' && (STR)[2] == 'u' ? EXTRA_CONSTRAINT_Csu (OP) \
: (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
: (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
: 0)
#define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
#define EXTRA_CONSTRAINT_Sr0(OP) \
(memory_operand((OP), GET_MODE (OP)) \
&& ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
#define EXTRA_CONSTRAINT_Sua(OP) \
(memory_operand((OP), GET_MODE (OP)) \
&& GET_CODE (XEXP (OP, 0)) != PLUS)
#define EXTRA_CONSTRAINT_S(OP, STR) \
((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
: (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
: 0)
#define EXTRA_CONSTRAINT_STR(OP, C, STR) \
((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
: (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
: (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
: (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
: (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
: (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
: (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
: 0)
#define MODE_DISP_OK_4(X,MODE) \
(GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
&& ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
#define MODE_DISP_OK_8(X,MODE) \
((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
&& ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
#undef MODE_DISP_OK_4
#define MODE_DISP_OK_4(X,MODE) \
((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
&& ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
|| ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
&& ! (INTVAL(X) & 3) && TARGET_SH2A))
#undef MODE_DISP_OK_8
#define MODE_DISP_OK_8(X,MODE) \
(((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
&& ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
|| ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
&& ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
#define BASE_REGISTER_RTX_P(X) \
((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
|| (GET_CODE (X) == SUBREG \
&& TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
&& GET_CODE (SUBREG_REG (X)) == REG \
&& REG_OK_FOR_BASE_P (SUBREG_REG (X))))
#define INDEX_REGISTER_RTX_P(X) \
((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
|| (GET_CODE (X) == SUBREG \
&& TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
&& GET_CODE (SUBREG_REG (X)) == REG \
&& SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
#define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
do { \
if (GET_CODE (OP) == CONST_INT) \
{ \
if (TARGET_SHMEDIA) \
{ \
int MODE_SIZE; \
\
if ((MODE) == VOIDmode) \
{ \
if (CONST_OK_FOR_I06 (INTVAL (OP))) \
goto LABEL; \
break; \
} \
MODE_SIZE = GET_MODE_SIZE (MODE); \
if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
&& INTVAL (OP) >= -512 * MODE_SIZE \
&& INTVAL (OP) < 512 * MODE_SIZE) \
goto LABEL; \
else \
break; \
} \
if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
} \
} while(0)
#define ALLOW_INDEXED_ADDRESS \
((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
{ \
if (BASE_REGISTER_RTX_P (X)) \
goto LABEL; \
else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
&& ! TARGET_SHMEDIA \
&& BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
goto LABEL; \
else if (GET_CODE (X) == PLUS \
&& ((MODE) != PSImode || reload_completed)) \
{ \
rtx xop0 = XEXP ((X), 0); \
rtx xop1 = XEXP ((X), 1); \
if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
|| ((xop0 == stack_pointer_rtx \
|| xop0 == hard_frame_pointer_rtx) \
&& REG_P (xop1) && REGNO (xop1) == R0_REG) \
|| ((xop1 == stack_pointer_rtx \
|| xop1 == hard_frame_pointer_rtx) \
&& REG_P (xop0) && REGNO (xop0) == R0_REG)) \
&& ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
|| (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
|| ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
&& TARGET_FMOVD && MODE == DFmode))) \
{ \
if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
goto LABEL; \
if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
goto LABEL; \
} \
} \
}
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
{ \
if (flag_pic) \
(X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
if (GET_CODE (X) == PLUS \
&& (GET_MODE_SIZE (MODE) == 4 \
|| GET_MODE_SIZE (MODE) == 8) \
&& GET_CODE (XEXP ((X), 1)) == CONST_INT \
&& BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
&& ! TARGET_SHMEDIA \
&& ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
&& ! (TARGET_SH2E && (MODE) == SFmode)) \
{ \
rtx index_rtx = XEXP ((X), 1); \
HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
rtx sum; \
\
GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
\
\
if (offset > 127) \
{ \
offset_base = ((offset + 4) & ~60) - 4; \
} \
else \
offset_base = offset & ~60; \
\
if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
{ \
sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
GEN_INT (offset_base), NULL_RTX, 0, \
OPTAB_LIB_WIDEN); \
\
(X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
goto WIN; \
} \
} \
}
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
{ \
if (GET_CODE (X) == PLUS \
&& (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
&& BASE_REGISTER_RTX_P (XEXP (X, 0)) \
&& ! TARGET_SHMEDIA \
&& ! (TARGET_SH4 && (MODE) == DFmode) \
&& ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
&& (ALLOW_INDEXED_ADDRESS \
|| XEXP ((X), 0) == stack_pointer_rtx \
|| XEXP ((X), 0) == hard_frame_pointer_rtx)) \
{ \
rtx index_rtx = XEXP (X, 1); \
HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
rtx sum; \
\
if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
{ \
push_reload (X, NULL_RTX, &X, NULL, \
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
(TYPE)); \
goto WIN; \
} \
if (TARGET_SH2E && MODE == SFmode) \
{ \
X = copy_rtx (X); \
push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
(TYPE)); \
goto WIN; \
} \
\
if (offset > 127) \
{ \
offset_base = ((offset + 4) & ~60) - 4; \
} \
else \
offset_base = offset & ~60; \
\
if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
{ \
sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
GEN_INT (offset_base)); \
X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
(TYPE)); \
goto WIN; \
} \
} \
\
else if (GET_CODE (X) == PLUS \
&& (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
&& GET_CODE (XEXP (X, 0)) == PLUS \
&& GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
&& BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT \
&& ! TARGET_SHMEDIA \
&& ! (TARGET_SH2E && MODE == SFmode)) \
{ \
\
push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
goto WIN; \
} \
}
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
{ \
if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
goto LABEL; \
}
#define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
#define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
: (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
: (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
: SImode)
#define CASE_VECTOR_PC_RELATIVE 1
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
#if defined(__SH2E__) || defined(__SH3E__) || defined( __SH4_SINGLE_ONLY__)
#define LIBGCC2_DOUBLE_TYPE_SIZE 32
#else
#define LIBGCC2_DOUBLE_TYPE_SIZE 64
#endif
#define DEFAULT_SIGNED_CHAR 1
#define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
#define WCHAR_TYPE "short unsigned int"
#define WCHAR_TYPE_SIZE 16
#define SH_ELF_WCHAR_TYPE "long int"
#define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
#define MAX_MOVE_MAX 8
#define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
#define WORD_REGISTER_OPERATIONS
#define LOAD_EXTEND_OP(MODE) \
(((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
: (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
#define SHORT_IMMEDIATES_SIGN_EXTEND
#define SLOW_BYTE_ACCESS 1
#define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
(!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
#define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
#define FUNCTION_MODE Pmode
#define INSN_SETS_ARE_DELAYED(X) \
((GET_CODE (X) == INSN \
&& GET_CODE (PATTERN (X)) != SEQUENCE \
&& GET_CODE (PATTERN (X)) != USE \
&& GET_CODE (PATTERN (X)) != CLOBBER \
&& get_attr_is_sfunc (X)))
#define INSN_REFERENCES_ARE_DELAYED(X) \
((GET_CODE (X) == INSN \
&& GET_CODE (PATTERN (X)) != SEQUENCE \
&& GET_CODE (PATTERN (X)) != USE \
&& GET_CODE (PATTERN (X)) != CLOBBER \
&& get_attr_is_sfunc (X)))
#define LEGITIMATE_PIC_OPERAND_P(X) \
((! nonpic_symbol_mentioned_p (X) \
&& (GET_CODE (X) != SYMBOL_REF \
|| ! CONSTANT_POOL_ADDRESS_P (X) \
|| ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
|| (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
#define SYMBOLIC_CONST_P(X) \
((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
&& nonpic_symbol_mentioned_p (X))
#define REGCLASS_HAS_GENERAL_REG(CLASS) \
((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
|| (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
#define REGCLASS_HAS_FP_REG(CLASS) \
((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
|| (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
#define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
#define ASM_COMMENT_START "!"
#define ASM_APP_ON ""
#define ASM_APP_OFF ""
#define FILE_ASM_OP "\t.file\n"
#define SET_ASM_OP "\t.set\t"
#define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
#define DATA_SECTION_ASM_OP "\t.data"
#if defined CRT_BEGIN || defined CRT_END
# undef TEXT_SECTION_ASM_OP
# if __SHMEDIA__ == 1 && __SH5__ == 32
# define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
# else
# define TEXT_SECTION_ASM_OP "\t.text"
# endif
#endif
#ifndef BSS_SECTION_ASM_OP
#define BSS_SECTION_ASM_OP "\t.section\t.bss"
#endif
#ifndef ASM_OUTPUT_ALIGNED_BSS
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
#endif
#define JUMP_TABLES_IN_TEXT_SECTION 1
#undef DO_GLOBAL_CTORS_BODY
#define DO_GLOBAL_CTORS_BODY \
{ \
typedef (*pfunc)(); \
extern pfunc __ctors[]; \
extern pfunc __ctors_end[]; \
pfunc *p; \
for (p = __ctors_end; p > __ctors; ) \
{ \
(*--p)(); \
} \
}
#undef DO_GLOBAL_DTORS_BODY
#define DO_GLOBAL_DTORS_BODY \
{ \
typedef (*pfunc)(); \
extern pfunc __dtors[]; \
extern pfunc __dtors_end[]; \
pfunc *p; \
for (p = __dtors; p < __dtors_end; p++) \
{ \
(*p)(); \
} \
}
#define ASM_OUTPUT_REG_PUSH(file, v) \
{ \
if (TARGET_SHMEDIA) \
{ \
fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
} \
else \
fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
}
#define ASM_OUTPUT_REG_POP(file, v) \
{ \
if (TARGET_SHMEDIA) \
{ \
fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
} \
else \
fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
}
#define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
#define SH_DBX_REGISTER_NUMBER(REGNO) \
(IN_RANGE ((REGNO), \
(unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
: ((int) (REGNO) >= FIRST_FP_REG \
&& ((int) (REGNO) \
<= (FIRST_FP_REG + \
((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
? ((unsigned) (REGNO) - FIRST_FP_REG \
+ (TARGET_SH5 ? 77 : 25)) \
: XD_REGISTER_P (REGNO) \
? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
: TARGET_REGISTER_P (REGNO) \
? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
: (REGNO) == PR_REG \
? (TARGET_SH5 ? 18 : 17) \
: (REGNO) == PR_MEDIA_REG \
? (TARGET_SH5 ? 18 : (unsigned) -1) \
: (REGNO) == T_REG \
? (TARGET_SH5 ? 242 : 18) \
: (REGNO) == GBR_REG \
? (TARGET_SH5 ? 238 : 19) \
: (REGNO) == MACH_REG \
? (TARGET_SH5 ? 239 : 20) \
: (REGNO) == MACL_REG \
? (TARGET_SH5 ? 240 : 21) \
: (REGNO) == FPUL_REG \
? (TARGET_SH5 ? 244 : 23) \
: (unsigned) -1)
#define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
do \
{ \
if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
fputs ("datalabel ", (FILE)); \
assemble_name ((FILE), XSTR ((SYM), 0)); \
} \
while (0)
#define ASM_OUTPUT_ALIGN(FILE,LOG) \
if ((LOG) != 0) \
fprintf ((FILE), "\t.align %d\n", (LOG))
#define GLOBAL_ASM_OP "\t.global\t"
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
switch (GET_MODE (BODY)) \
{ \
case SImode: \
if (TARGET_SH5) \
{ \
asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
(VALUE), (REL)); \
break; \
} \
asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
break; \
case HImode: \
if (TARGET_SH5) \
{ \
asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
(VALUE), (REL)); \
break; \
} \
asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
break; \
case QImode: \
if (TARGET_SH5) \
{ \
asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
(VALUE), (REL)); \
break; \
} \
asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
break; \
default: \
break; \
}
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
if (! optimize || TARGET_BIGTABLE) \
asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
else \
asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
#define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
#define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
|| (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
do \
if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
{ \
switch (XINT ((X), 1)) \
{ \
case UNSPEC_DATALABEL: \
fputs ("datalabel ", (STREAM)); \
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
break; \
case UNSPEC_PIC: \
\
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
break; \
case UNSPEC_GOT: \
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
fputs ("@GOT", (STREAM)); \
break; \
case UNSPEC_GOTOFF: \
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
fputs ("@GOTOFF", (STREAM)); \
break; \
case UNSPEC_PLT: \
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
fputs ("@PLT", (STREAM)); \
break; \
case UNSPEC_GOTPLT: \
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
fputs ("@GOTPLT", (STREAM)); \
break; \
case UNSPEC_DTPOFF: \
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
fputs ("@DTPOFF", (STREAM)); \
break; \
case UNSPEC_GOTTPOFF: \
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
fputs ("@GOTTPOFF", (STREAM)); \
break; \
case UNSPEC_TPOFF: \
output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
fputs ("@TPOFF", (STREAM)); \
break; \
case UNSPEC_CALLER: \
{ \
char name[32]; \
\
ASM_GENERATE_INTERNAL_LABEL \
(name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
assemble_name ((STREAM), name); \
} \
break; \
default: \
goto FAIL; \
} \
break; \
} \
else \
goto FAIL; \
while (0)
extern struct rtx_def *sh_compare_op0;
extern struct rtx_def *sh_compare_op1;
enum processor_type {
PROCESSOR_SH1,
PROCESSOR_SH2,
PROCESSOR_SH2E,
PROCESSOR_SH2A,
PROCESSOR_SH3,
PROCESSOR_SH3E,
PROCESSOR_SH4,
PROCESSOR_SH4A,
PROCESSOR_SH5
};
#define sh_cpu_attr ((enum attr_cpu)sh_cpu)
extern enum processor_type sh_cpu;
extern int optimize;
enum mdep_reorg_phase_e
{
SH_BEFORE_MDEP_REORG,
SH_INSERT_USES_LABELS,
SH_SHORTEN_BRANCHES0,
SH_FIXUP_PCLOAD,
SH_SHORTEN_BRANCHES1,
SH_AFTER_MDEP_REORG
};
extern enum mdep_reorg_phase_e mdep_reorg_phase;
#define REGISTER_TARGET_PRAGMAS() do { \
c_register_pragma (0, "interrupt", sh_pr_interrupt); \
c_register_pragma (0, "trapa", sh_pr_trapa); \
c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
} while (0)
extern tree sh_deferred_function_attributes;
extern tree *sh_deferred_function_attributes_tail;
extern int current_function_interrupt;
#define ADJUST_INSN_LENGTH(X, LENGTH) \
(LENGTH) += sh_insn_length_adjustment (X);
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < 4)\
(UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
(MODE) = (TARGET_SH1 ? SImode \
: TARGET_SHMEDIA32 ? SImode : DImode);
#define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
#define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
#define SH_DYNAMIC_SHIFT_COST \
(TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
#define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
#define ACTUAL_NORMAL_MODE(ENTITY) \
(TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
#define NORMAL_MODE(ENTITY) \
(sh_cfun_interrupt_handler_p () \
? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
: ACTUAL_NORMAL_MODE (ENTITY))
#define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
#define MODE_EXIT(ENTITY) \
(sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
#define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
&& (REGNO) == FPSCR_REG)
#define MODE_NEEDED(ENTITY, INSN) \
(recog_memoized (INSN) >= 0 \
? get_attr_fp_mode (INSN) \
: FP_MODE_NONE)
#define MODE_AFTER(MODE, INSN) \
(TARGET_HITACHI \
&& recog_memoized (INSN) >= 0 \
&& get_attr_fp_set (INSN) != FP_SET_NONE \
? (int) get_attr_fp_set (INSN) \
: (MODE))
#define MODE_PRIORITY_TO_MODE(ENTITY, N) \
((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
#define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
sh_can_redirect_branch ((INSN), (SEQ))
#define DWARF_FRAME_RETURN_COLUMN \
(TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
#define EH_RETURN_DATA_REGNO(N) \
((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
| (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
| ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
do { \
if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
&& ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
{ \
gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
if (0) goto DONE; \
} \
} while (0)
#if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm (SECTION_OP "\n\
mov.l 1f,r1\n\
mova 2f,r0\n\
braf r1\n\
lds r0,pr\n\
0: .p2align 2\n\
1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2:\n" TEXT_SECTION_ASM_OP);
#endif
#define SIMULTANEOUS_PREFETCHES 2
#define high_life_started reload_in_progress
#endif