#ifndef SPU_ISELLOWERING_H
#define SPU_ISELLOWERING_H
#include "llvm/Target/TargetLowering.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "SPU.h"
namespace llvm {
namespace SPUISD {
enum NodeType {
FIRST_NUMBER = ISD::BUILTIN_OP_END,
RET_FLAG,
Hi, Lo, PCRelAddr, AFormAddr, IndirectAddr,
LDRESULT, CALL, SHUFB, SHUFFLE_MASK, CNTB, PREFSLOT2VEC, VEC2PREFSLOT, SHLQUAD_L_BITS, SHLQUAD_L_BYTES, VEC_ROTL, VEC_ROTR, ROTBYTES_LEFT, ROTBYTES_LEFT_BITS, SELECT_MASK, SELB, ADD64_MARKER, SUB64_MARKER, MUL64_MARKER, LAST_SPUISD };
}
namespace SPU {
SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
EVT ValueType);
SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
EVT ValueType);
SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
EVT ValueType);
SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
EVT ValueType);
SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
EVT ValueType);
SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
const SPUTargetMachine &TM);
SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
DebugLoc dl);
}
class SPUTargetMachine;
class SPUTargetLowering :
public TargetLowering
{
int VarArgsFrameIndex; SPUTargetMachine &SPUTM;
public:
SPUTargetLowering(SPUTargetMachine &TM);
SPUTargetMachine &getSPUTargetMachine() {
return SPUTM;
}
virtual const char *getTargetNodeName(unsigned Opcode) const;
virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG);
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
const APInt &Mask,
APInt &KnownZero,
APInt &KnownOne,
const SelectionDAG &DAG,
unsigned Depth = 0) const;
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
unsigned Depth = 0) const;
ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
bool hasMemory,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
virtual bool isLegalAddressImmediate(GlobalValue *) const;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
virtual unsigned getFunctionAlignment(const Function *F) const;
virtual SDValue
LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
virtual SDValue
LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals);
virtual SDValue
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG);
};
}
#endif