LiveIntervalAnalysis.cpp [plain text]
#define DEBUG_TYPE "regalloc"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/Value.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include <algorithm>
#include <limits>
#include <cmath>
using namespace llvm;
static cl::opt<bool> DisableReMat("disable-rematerialization",
cl::init(false), cl::Hidden);
STATISTIC(numIntervals , "Number of original intervals");
char LiveIntervals::ID = 0;
INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
"Live Interval Analysis", false, false)
INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
INITIALIZE_PASS_DEPENDENCY(LiveVariables)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
"Live Interval Analysis", false, false)
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<AliasAnalysis>();
AU.addPreserved<AliasAnalysis>();
AU.addRequired<LiveVariables>();
AU.addPreserved<LiveVariables>();
AU.addPreservedID(MachineLoopInfoID);
AU.addPreservedID(MachineDominatorsID);
AU.addPreserved<SlotIndexes>();
AU.addRequiredTransitive<SlotIndexes>();
MachineFunctionPass::getAnalysisUsage(AU);
}
void LiveIntervals::releaseMemory() {
for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
E = r2iMap_.end(); I != E; ++I)
delete I->second;
r2iMap_.clear();
RegMaskSlots.clear();
RegMaskBits.clear();
RegMaskBlocks.clear();
VNInfoAllocator.Reset();
}
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
mf_ = &fn;
mri_ = &mf_->getRegInfo();
tm_ = &fn.getTarget();
tri_ = tm_->getRegisterInfo();
tii_ = tm_->getInstrInfo();
aa_ = &getAnalysis<AliasAnalysis>();
lv_ = &getAnalysis<LiveVariables>();
indexes_ = &getAnalysis<SlotIndexes>();
allocatableRegs_ = tri_->getAllocatableSet(fn);
reservedRegs_ = tri_->getReservedRegs(fn);
computeIntervals();
numIntervals += getNumIntervals();
DEBUG(dump());
return true;
}
void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
OS << "********** INTERVALS **********\n";
for (unsigned Reg = 1, RegE = tri_->getNumRegs(); Reg != RegE; ++Reg)
if (const LiveInterval *LI = r2iMap_.lookup(Reg)) {
LI->print(OS, tri_);
OS << '\n';
}
for (unsigned Reg = 0, RegE = mri_->getNumVirtRegs(); Reg != RegE; ++Reg)
if (const LiveInterval *LI =
r2iMap_.lookup(TargetRegisterInfo::index2VirtReg(Reg))) {
LI->print(OS, tri_);
OS << '\n';
}
printInstrs(OS);
}
void LiveIntervals::printInstrs(raw_ostream &OS) const {
OS << "********** MACHINEINSTRS **********\n";
mf_->print(OS, indexes_);
}
void LiveIntervals::dumpInstrs() const {
printInstrs(dbgs());
}
static
bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
unsigned Reg = MI.getOperand(MOIdx).getReg();
for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg())
continue;
if (MO.getReg() == Reg && MO.isDef()) {
assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
MI.getOperand(MOIdx).getSubReg() &&
(MO.getSubReg() || MO.isImplicit()));
return true;
}
}
return false;
}
bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
LiveInterval &interval) {
if (!MO.getSubReg() || MO.isEarlyClobber())
return false;
SlotIndex RedefIndex = MIIdx.getRegSlot();
const LiveRange *OldLR =
interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
if (DefMI != 0) {
return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
}
return false;
}
void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
MachineBasicBlock::iterator mi,
SlotIndex MIIdx,
MachineOperand& MO,
unsigned MOIdx,
LiveInterval &interval) {
DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
if (interval.empty()) {
SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
assert(!MO.readsReg() && "First def cannot also read virtual register "
"missing <undef> flag?");
VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
assert(ValNo->id == 0 && "First value in interval is not 0?");
if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
SlotIndex killIdx;
if (vi.Kills[0] != mi)
killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
else
killIdx = defIndex.getDeadSlot();
if (killIdx > defIndex) {
assert(vi.AliveBlocks.empty() &&
"Shouldn't be alive across any blocks!");
LiveRange LR(defIndex, killIdx, ValNo);
interval.addRange(LR);
DEBUG(dbgs() << " +" << LR << "\n");
return;
}
}
LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
DEBUG(dbgs() << " +" << NewLR);
interval.addRange(NewLR);
bool PHIJoin = lv_->isPHIJoin(interval.reg);
if (PHIJoin) {
assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
DEBUG(dbgs() << " phi-join");
ValNo->setHasPHIKill(true);
} else {
for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
E = vi.AliveBlocks.end(); I != E; ++I) {
MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
interval.addRange(LR);
DEBUG(dbgs() << " +" << LR);
}
}
for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
MachineInstr *Kill = vi.Kills[i];
SlotIndex Start = getMBBStartIdx(Kill->getParent());
SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
if (PHIJoin) {
assert(getInstructionFromIndex(Start) == 0 &&
"PHI def index points at actual instruction.");
ValNo = interval.getNextValue(Start, VNInfoAllocator);
ValNo->setIsPHIDef(true);
}
LiveRange LR(Start, killIdx, ValNo);
interval.addRange(LR);
DEBUG(dbgs() << " +" << LR);
}
} else {
if (MultipleDefsBySameMI(*mi, MOIdx))
return;
bool PartReDef = isPartialRedef(MIIdx, MO, interval);
if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
const LiveRange *OldLR =
interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
VNInfo *OldValNo = OldLR->valno;
SlotIndex DefIndex = OldValNo->def.getRegSlot();
interval.removeRange(DefIndex, RedefIndex);
VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
OldValNo->def = RedefIndex;
LiveRange LR(DefIndex, RedefIndex, ValNo);
DEBUG(dbgs() << " replace range with " << LR);
interval.addRange(LR);
if (MO.isDead())
interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
OldValNo));
DEBUG({
dbgs() << " RESULT: ";
interval.print(dbgs(), tri_);
});
} else if (lv_->isPHIJoin(interval.reg)) {
SlotIndex defIndex = MIIdx.getRegSlot();
if (MO.isEarlyClobber())
defIndex = MIIdx.getRegSlot(true);
VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
SlotIndex killIndex = getMBBEndIdx(mbb);
LiveRange LR(defIndex, killIndex, ValNo);
interval.addRange(LR);
ValNo->setHasPHIKill(true);
DEBUG(dbgs() << " phi-join +" << LR);
} else {
llvm_unreachable("Multiply defined register");
}
}
DEBUG(dbgs() << '\n');
}
static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) {
for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
SE = MBB->succ_end();
SI != SE; ++SI) {
const MachineBasicBlock* succ = *SI;
if (succ->isLiveIn(Reg))
return true;
}
return false;
}
void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator mi,
SlotIndex MIIdx,
MachineOperand& MO,
LiveInterval &interval) {
DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
SlotIndex baseIndex = MIIdx;
SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
SlotIndex end = start;
if (MO.isDead()) {
DEBUG(dbgs() << " dead");
end = start.getDeadSlot();
goto exit;
}
baseIndex = baseIndex.getNextIndex();
while (++mi != MBB->end()) {
if (mi->isDebugValue())
continue;
if (getInstructionFromIndex(baseIndex) == 0)
baseIndex = indexes_->getNextNonNullIndex(baseIndex);
if (mi->killsRegister(interval.reg, tri_)) {
DEBUG(dbgs() << " killed");
end = baseIndex.getRegSlot();
goto exit;
} else {
int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
if (DefIdx != -1) {
if (mi->isRegTiedToUseOperand(DefIdx)) {
end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
} else {
DEBUG(dbgs() << " dead");
end = start.getDeadSlot();
}
goto exit;
}
}
baseIndex = baseIndex.getNextIndex();
}
assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
if (isReserved(interval.reg)) {
end = start.getDeadSlot();
} else {
assert(isRegLiveIntoSuccessor(MBB, interval.reg) &&
"Unreserved reg not live-out?");
end = getMBBEndIdx(MBB);
}
exit:
assert(start < end && "did not find end of interval?");
VNInfo *ValNo = interval.getVNInfoAt(start);
bool Extend = ValNo != 0;
if (!Extend)
ValNo = interval.getNextValue(start, VNInfoAllocator);
LiveRange LR(start, end, ValNo);
interval.addRange(LR);
DEBUG(dbgs() << " +" << LR << '\n');
}
void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI,
SlotIndex MIIdx,
MachineOperand& MO,
unsigned MOIdx) {
if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
getOrCreateInterval(MO.getReg()));
else
handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
getOrCreateInterval(MO.getReg()));
}
void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
SlotIndex MIIdx,
LiveInterval &interval) {
assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
"Only physical registers can be live in.");
assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
MBB->isLandingPad()) &&
"Allocatable live-ins only valid for entry blocks and landing pads.");
DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, tri_));
MachineBasicBlock::iterator mi = MBB->begin();
MachineBasicBlock::iterator E = MBB->end();
if (mi != E && mi->isDebugValue()) {
while (++mi != E && mi->isDebugValue())
;
if (mi == E)
return;
}
SlotIndex baseIndex = MIIdx;
SlotIndex start = baseIndex;
if (getInstructionFromIndex(baseIndex) == 0)
baseIndex = indexes_->getNextNonNullIndex(baseIndex);
SlotIndex end = baseIndex;
bool SeenDefUse = false;
while (mi != E) {
if (mi->killsRegister(interval.reg, tri_)) {
DEBUG(dbgs() << " killed");
end = baseIndex.getRegSlot();
SeenDefUse = true;
break;
} else if (mi->modifiesRegister(interval.reg, tri_)) {
DEBUG(dbgs() << " dead");
end = start.getDeadSlot();
SeenDefUse = true;
break;
}
while (++mi != E && mi->isDebugValue())
;
if (mi != E)
baseIndex = indexes_->getNextNonNullIndex(baseIndex);
}
if (!SeenDefUse) {
if (isAllocatable(interval.reg) ||
!isRegLiveIntoSuccessor(MBB, interval.reg)) {
DEBUG(dbgs() << " dead");
return;
} else {
DEBUG(dbgs() << " live through");
end = getMBBEndIdx(MBB);
}
}
SlotIndex defIdx = getMBBStartIdx(MBB);
assert(getInstructionFromIndex(defIdx) == 0 &&
"PHI def index points at actual instruction.");
VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
vni->setIsPHIDef(true);
LiveRange LR(start, end, vni);
interval.addRange(LR);
DEBUG(dbgs() << " +" << LR << '\n');
}
void LiveIntervals::computeIntervals() {
DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
<< "********** Function: "
<< ((Value*)mf_->getFunction())->getName() << '\n');
RegMaskBlocks.resize(mf_->getNumBlockIDs());
SmallVector<unsigned, 8> UndefUses;
for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
MBBI != E; ++MBBI) {
MachineBasicBlock *MBB = MBBI;
RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
if (MBB->empty())
continue;
SlotIndex MIIndex = getMBBStartIdx(MBB);
DEBUG(dbgs() << "BB#" << MBB->getNumber()
<< ":\t\t# derived from " << MBB->getName() << "\n");
for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
LE = MBB->livein_end(); LI != LE; ++LI) {
handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
}
if (getInstructionFromIndex(MIIndex) == 0)
MIIndex = indexes_->getNextNonNullIndex(MIIndex);
for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
MI != miEnd; ++MI) {
DEBUG(dbgs() << MIIndex << "\t" << *MI);
if (MI->isDebugValue())
continue;
assert(indexes_->getInstructionFromIndex(MIIndex) == MI &&
"Lost SlotIndex synchronization");
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegMask()) {
RegMaskSlots.push_back(MIIndex.getRegSlot());
RegMaskBits.push_back(MO.getRegMask());
continue;
}
if (!MO.isReg() || !MO.getReg())
continue;
if (MO.isDef())
handleRegisterDef(MBB, MI, MIIndex, MO, i);
else if (MO.isUndef())
UndefUses.push_back(MO.getReg());
}
MIIndex = indexes_->getNextNonNullIndex(MIIndex);
}
std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
RMB.second = RegMaskSlots.size() - RMB.first;;
}
for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
unsigned UndefReg = UndefUses[i];
(void)getOrCreateInterval(UndefReg);
}
}
LiveInterval* LiveIntervals::createInterval(unsigned reg) {
float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
return new LiveInterval(reg, Weight);
}
LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) {
LiveInterval *NewLI = createInterval(li->reg);
NewLI->Copy(*li, mri_, getVNInfoAllocator());
return NewLI;
}
bool LiveIntervals::shrinkToUses(LiveInterval *li,
SmallVectorImpl<MachineInstr*> *dead) {
DEBUG(dbgs() << "Shrink: " << *li << '\n');
assert(TargetRegisterInfo::isVirtualRegister(li->reg)
&& "Can only shrink virtual registers");
SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li->reg);
MachineInstr *UseMI = I.skipInstruction();) {
if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
continue;
SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
VNInfo *VNI = li->getVNInfoBefore(Idx);
if (!VNI) {
DEBUG(dbgs() << Idx << '\t' << *UseMI
<< "Warning: Instr claims to read non-existent value in "
<< *li << '\n');
continue;
}
if (SlotIndex::isSameInstr(VNI->def, Idx)) {
Idx = VNI->def;
VNI = li->getVNInfoBefore(Idx);
assert(VNI && "Early-clobber tied value not available");
}
WorkList.push_back(std::make_pair(Idx, VNI));
}
LiveInterval NewLI(li->reg, 0);
for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
I != E; ++I) {
VNInfo *VNI = *I;
if (VNI->isUnused())
continue;
NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
}
SmallPtrSet<VNInfo*, 8> UsedPHIs;
while (!WorkList.empty()) {
SlotIndex Idx = WorkList.back().first;
VNInfo *VNI = WorkList.back().second;
WorkList.pop_back();
const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
SlotIndex BlockStart = getMBBStartIdx(MBB);
if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
(void)ExtVNI;
assert(ExtVNI == VNI && "Unexpected existing value number");
if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
continue;
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
PE = MBB->pred_end(); PI != PE; ++PI) {
if (!LiveOut.insert(*PI))
continue;
SlotIndex Stop = getMBBEndIdx(*PI);
if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
WorkList.push_back(std::make_pair(Stop, PVNI));
}
continue;
}
DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
PE = MBB->pred_end(); PI != PE; ++PI) {
if (!LiveOut.insert(*PI))
continue;
SlotIndex Stop = getMBBEndIdx(*PI);
assert(li->getVNInfoBefore(Stop) == VNI &&
"Wrong value out of predecessor");
WorkList.push_back(std::make_pair(Stop, VNI));
}
}
bool CanSeparate = false;
for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
I != E; ++I) {
VNInfo *VNI = *I;
if (VNI->isUnused())
continue;
LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
assert(LII != NewLI.end() && "Missing live range for PHI");
if (LII->end != VNI->def.getDeadSlot())
continue;
if (VNI->isPHIDef()) {
VNI->setIsUnused(true);
NewLI.removeRange(*LII);
DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
CanSeparate = true;
} else {
MachineInstr *MI = getInstructionFromIndex(VNI->def);
assert(MI && "No instruction defining live value");
MI->addRegisterDead(li->reg, tri_);
if (dead && MI->allDefsAreDead()) {
DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
dead->push_back(MI);
}
}
}
li->ranges.swap(NewLI.ranges);
DEBUG(dbgs() << "Shrunk: " << *li << '\n');
return CanSeparate;
}
void LiveIntervals::addKillFlags() {
for (iterator I = begin(), E = end(); I != E; ++I) {
unsigned Reg = I->first;
if (TargetRegisterInfo::isPhysicalRegister(Reg))
continue;
if (mri_->reg_nodbg_empty(Reg))
continue;
LiveInterval *LI = I->second;
for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
++RI) {
if (RI->end.isBlock())
continue;
MachineInstr *MI = getInstructionFromIndex(RI->end);
if (!MI)
continue;
MI->addRegisterKilled(Reg, NULL);
}
}
}
unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
MachineInstr *MI) const {
unsigned RegOp = 0;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
unsigned Reg = MO.getReg();
if (Reg == 0 || Reg == li.reg)
continue;
if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isAllocatable(Reg))
continue;
RegOp = MO.getReg();
break; }
return RegOp;
}
bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
SlotIndex UseIdx) const {
VNInfo *UValNo = li.getVNInfoAt(UseIdx);
return UValNo && UValNo == li.getVNInfoAt(getInstructionIndex(MI));
}
bool
LiveIntervals::isReMaterializable(const LiveInterval &li,
const VNInfo *ValNo, MachineInstr *MI,
const SmallVectorImpl<LiveInterval*> *SpillIs,
bool &isLoad) {
if (DisableReMat)
return false;
if (!tii_->isTriviallyReMaterializable(MI, aa_))
return false;
unsigned ImpUse = getReMatImplicitUse(li, MI);
if (ImpUse) {
const LiveInterval &ImpLi = getInterval(ImpUse);
for (MachineRegisterInfo::use_nodbg_iterator
ri = mri_->use_nodbg_begin(li.reg), re = mri_->use_nodbg_end();
ri != re; ++ri) {
MachineInstr *UseMI = &*ri;
SlotIndex UseIdx = getInstructionIndex(UseMI);
if (li.getVNInfoAt(UseIdx) != ValNo)
continue;
if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
return false;
}
if (SpillIs)
for (unsigned i = 0, e = SpillIs->size(); i != e; ++i)
if (ImpUse == (*SpillIs)[i]->reg)
return false;
}
return true;
}
bool
LiveIntervals::isReMaterializable(const LiveInterval &li,
const SmallVectorImpl<LiveInterval*> *SpillIs,
bool &isLoad) {
isLoad = false;
for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
i != e; ++i) {
const VNInfo *VNI = *i;
if (VNI->isUnused())
continue; MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
if (!ReMatDefMI)
return false;
bool DefIsLoad = false;
if (!ReMatDefMI ||
!isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
return false;
isLoad |= DefIsLoad;
}
return true;
}
MachineBasicBlock*
LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
SlotIndex Start = LI.beginIndex();
if (Start.isBlock())
return NULL;
SlotIndex Stop = LI.endIndex();
if (Stop.isBlock())
return NULL;
MachineBasicBlock *MBB1 = indexes_->getMBBFromIndex(Start);
MachineBasicBlock *MBB2 = indexes_->getMBBFromIndex(Stop);
return MBB1 == MBB2 ? MBB1 : NULL;
}
float
LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
if (loopDepth > 200)
loopDepth = 200;
float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
return (isDef + isUse) * lc;
}
LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
MachineInstr* startInst) {
LiveInterval& Interval = getOrCreateInterval(reg);
VNInfo* VN = Interval.getNextValue(
SlotIndex(getInstructionIndex(startInst).getRegSlot()),
getVNInfoAllocator());
VN->setHasPHIKill(true);
LiveRange LR(
SlotIndex(getInstructionIndex(startInst).getRegSlot()),
getMBBEndIdx(startInst->getParent()), VN);
Interval.addRange(LR);
return LR;
}
bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
BitVector &UsableRegs) {
if (LI.empty())
return false;
LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
ArrayRef<SlotIndex> Slots;
ArrayRef<const uint32_t*> Bits;
if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
Slots = getRegMaskSlotsInBlock(MBB->getNumber());
Bits = getRegMaskBitsInBlock(MBB->getNumber());
} else {
Slots = getRegMaskSlots();
Bits = getRegMaskBits();
}
ArrayRef<SlotIndex>::iterator SlotI =
std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
if (SlotI == SlotE)
return false;
bool Found = false;
for (;;) {
assert(*SlotI >= LiveI->start);
while (*SlotI < LiveI->end) {
if (!Found) {
UsableRegs.clear();
UsableRegs.resize(tri_->getNumRegs(), true);
Found = true;
}
UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
if (++SlotI == SlotE)
return Found;
}
LiveI = LI.advanceTo(LiveI, *SlotI);
if (LiveI == LiveE)
return Found;
while (*SlotI < LiveI->start)
if (++SlotI == SlotE)
return Found;
}
}
class LiveIntervals::HMEditor {
private:
LiveIntervals& LIS;
const MachineRegisterInfo& MRI;
const TargetRegisterInfo& TRI;
SlotIndex NewIdx;
typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
typedef DenseSet<IntRangePair> RangeSet;
struct RegRanges {
LiveRange* Use;
LiveRange* EC;
LiveRange* Dead;
LiveRange* Def;
RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
};
typedef DenseMap<unsigned, RegRanges> BundleRanges;
public:
HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
const TargetRegisterInfo& TRI, SlotIndex NewIdx)
: LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
RangeSet Entering, Internal, Exiting;
bool hasRegMaskOp = false;
collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
moveAllEnteringFrom(OldIdx, Entering);
moveAllInternalFrom(OldIdx, Internal);
moveAllExitingFrom(OldIdx, Exiting);
if (hasRegMaskOp)
updateRegMaskSlots(OldIdx);
#ifndef NDEBUG
LIValidator validator;
std::for_each(Entering.begin(), Entering.end(), validator);
std::for_each(Internal.begin(), Internal.end(), validator);
std::for_each(Exiting.begin(), Exiting.end(), validator);
assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
#endif
}
void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
if (MI == BundleStart)
return;
SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
"SlotIndex <-> Instruction mapping broken for MI");
MachineBasicBlock::instr_iterator BII(BundleStart);
RangeSet Entering, Internal, Exiting;
bool hasRegMaskOp = false;
collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
if (&*BII == MI)
continue;
collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
}
BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
moveAllEnteringFromInto(OldIdx, Entering, BR);
moveAllInternalFromInto(OldIdx, Internal, BR);
moveAllExitingFromInto(OldIdx, Exiting, BR);
#ifndef NDEBUG
LIValidator validator;
std::for_each(Entering.begin(), Entering.end(), validator);
std::for_each(Internal.begin(), Internal.end(), validator);
std::for_each(Exiting.begin(), Exiting.end(), validator);
assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
#endif
}
private:
#ifndef NDEBUG
class LIValidator {
private:
DenseSet<const LiveInterval*> Checked, Bogus;
public:
void operator()(const IntRangePair& P) {
const LiveInterval* LI = P.first;
if (Checked.count(LI))
return;
Checked.insert(LI);
if (LI->empty())
return;
SlotIndex LastEnd = LI->begin()->start;
for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
LRI != LRE; ++LRI) {
const LiveRange& LR = *LRI;
if (LastEnd > LR.start || LR.start >= LR.end)
Bogus.insert(LI);
LastEnd = LR.end;
}
}
bool rangesOk() const {
return Bogus.empty();
}
};
#endif
void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
hasRegMaskOp = false;
for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
MOE = MI->operands_end();
MOI != MOE; ++MOI) {
const MachineOperand& MO = *MOI;
if (MO.isRegMask()) {
hasRegMaskOp = true;
continue;
}
if (!MO.isReg() || MO.getReg() == 0)
continue;
unsigned Reg = MO.getReg();
if (!LIS.hasInterval(Reg) ||
(TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
continue;
LiveInterval* LI = &LIS.getInterval(Reg);
if (MO.readsReg()) {
LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
if (LR != 0)
Entering.insert(std::make_pair(LI, LR));
}
if (MO.isDef()) {
if (MO.isEarlyClobber()) {
LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot(true));
assert(LR != 0 && "No EC range?");
if (LR->end > OldIdx.getDeadSlot())
Exiting.insert(std::make_pair(LI, LR));
else
Internal.insert(std::make_pair(LI, LR));
} else if (MO.isDead()) {
LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
assert(LR != 0 && "No dead-def range?");
Internal.insert(std::make_pair(LI, LR));
} else {
LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getDeadSlot());
assert(LR && LR->end > OldIdx.getDeadSlot() &&
"Non-dead-def should have live range exiting.");
Exiting.insert(std::make_pair(LI, LR));
}
}
}
}
void collectRangesInBundle(MachineInstr* MI, RangeSet& Entering,
RangeSet& Exiting, SlotIndex MIStartIdx,
SlotIndex MIEndIdx) {
for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
MOE = MI->operands_end();
MOI != MOE; ++MOI) {
const MachineOperand& MO = *MOI;
assert(!MO.isRegMask() && "Can't have RegMasks in bundles.");
if (!MO.isReg() || MO.getReg() == 0)
continue;
unsigned Reg = MO.getReg();
if (!LIS.hasInterval(Reg) ||
(TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
continue;
LiveInterval* LI = &LIS.getInterval(Reg);
if (MO.readsReg()) {
LiveRange* LR = LI->getLiveRangeContaining(MIStartIdx);
if (LR != 0)
Entering.insert(std::make_pair(LI, LR));
}
if (MO.isDef()) {
assert(!MO.isEarlyClobber() && "Early clobbers not allowed in bundles.");
assert(!MO.isDead() && "Dead-defs not allowed in bundles.");
LiveRange* LR = LI->getLiveRangeContaining(MIEndIdx.getDeadSlot());
assert(LR != 0 && "Internal ranges not allowed in bundles.");
Exiting.insert(std::make_pair(LI, LR));
}
}
}
BundleRanges createBundleRanges(RangeSet& Entering, RangeSet& Internal, RangeSet& Exiting) {
BundleRanges BR;
for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
EI != EE; ++EI) {
LiveInterval* LI = EI->first;
LiveRange* LR = EI->second;
BR[LI->reg].Use = LR;
}
for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
II != IE; ++II) {
LiveInterval* LI = II->first;
LiveRange* LR = II->second;
if (LR->end.isDead()) {
BR[LI->reg].Dead = LR;
} else {
BR[LI->reg].EC = LR;
}
}
for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
EI != EE; ++EI) {
LiveInterval* LI = EI->first;
LiveRange* LR = EI->second;
BR[LI->reg].Def = LR;
}
return BR;
}
void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
if (!OldKillMI->killsRegister(reg))
return; MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
assert(!NewKillMI->killsRegister(reg) && "New kill instr is already a kill.");
OldKillMI->clearRegisterKills(reg, &TRI);
NewKillMI->addRegisterKilled(reg, &TRI);
}
void updateRegMaskSlots(SlotIndex OldIdx) {
SmallVectorImpl<SlotIndex>::iterator RI =
std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
OldIdx);
assert(*RI == OldIdx && "No RegMask at OldIdx.");
*RI = NewIdx;
assert(*prior(RI) < *RI && *RI < *next(RI) &&
"RegSlots out of order. Did you move one call across another?");
}
SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
SlotIndex LastUse = NewIdx;
for (MachineRegisterInfo::use_nodbg_iterator
UI = MRI.use_nodbg_begin(Reg),
UE = MRI.use_nodbg_end();
UI != UE; UI.skipInstruction()) {
const MachineInstr* MI = &*UI;
SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
if (InstSlot > LastUse && InstSlot < OldIdx)
LastUse = InstSlot;
}
return LastUse;
}
void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
LiveInterval* LI = P.first;
LiveRange* LR = P.second;
bool LiveThrough = LR->end > OldIdx.getRegSlot();
if (LiveThrough)
return;
SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
if (LastUse != NewIdx)
moveKillFlags(LI->reg, NewIdx, LastUse);
LR->end = LastUse.getRegSlot();
}
void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
LiveInterval* LI = P.first;
LiveRange* LR = P.second;
if (NewIdx > LR->end) {
moveKillFlags(LI->reg, LR->end, NewIdx);
LR->end = NewIdx.getRegSlot();
}
}
void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
bool GoingUp = NewIdx < OldIdx;
if (GoingUp) {
for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
EI != EE; ++EI)
moveEnteringUpFrom(OldIdx, *EI);
} else {
for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
EI != EE; ++EI)
moveEnteringDownFrom(OldIdx, *EI);
}
}
void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
LiveInterval* LI = P.first;
LiveRange* LR = P.second;
assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
LR->end <= OldIdx.getDeadSlot() &&
"Range should be internal to OldIdx.");
LiveRange Tmp(*LR);
Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
Tmp.valno->def = Tmp.start;
Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
LI->removeRange(*LR);
LI->addRange(Tmp);
}
void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
II != IE; ++II)
moveInternalFrom(OldIdx, *II);
}
void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
LiveRange* LR = P.second;
assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
"Range should start in OldIdx.");
assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
LR->start = NewStart;
LR->valno->def = NewStart;
}
void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
EI != EE; ++EI)
moveExitingFrom(OldIdx, *EI);
}
void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
BundleRanges& BR) {
LiveInterval* LI = P.first;
LiveRange* LR = P.second;
bool LiveThrough = LR->end > OldIdx.getRegSlot();
if (LiveThrough) {
assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
"Def in bundle should be def range.");
assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
"If bundle has use for this reg it should be LR.");
BR[LI->reg].Use = LR;
return;
}
SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
moveKillFlags(LI->reg, OldIdx, LastUse);
if (LR->start < NewIdx) {
assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
"Bundle shouldn't be re-defining reg mid-range.");
assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
"Bundle shouldn't have different use range for same reg.");
LR->end = LastUse.getRegSlot();
BR[LI->reg].Use = LR;
} else {
assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
"Live range starting at unexpected slot.");
assert(BR[LI->reg].Def == LR && "Reg should have def range.");
assert(BR[LI->reg].Dead == 0 &&
"Can't have def and dead def of same reg in a bundle.");
LR->end = LastUse.getDeadSlot();
BR[LI->reg].Dead = BR[LI->reg].Def;
BR[LI->reg].Def = 0;
}
}
void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
BundleRanges& BR) {
LiveInterval* LI = P.first;
LiveRange* LR = P.second;
if (NewIdx > LR->end) {
assert(BR[LI->reg].Use == 0 &&
"Bundle already has use range for reg.");
moveKillFlags(LI->reg, LR->end, NewIdx);
LR->end = NewIdx.getRegSlot();
BR[LI->reg].Use = LR;
} else {
assert(BR[LI->reg].Use != 0 &&
"Bundle should already have a use range for reg.");
}
}
void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
BundleRanges& BR) {
bool GoingUp = NewIdx < OldIdx;
if (GoingUp) {
for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
EI != EE; ++EI)
moveEnteringUpFromInto(OldIdx, *EI, BR);
} else {
for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
EI != EE; ++EI)
moveEnteringDownFromInto(OldIdx, *EI, BR);
}
}
void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
BundleRanges& BR) {
}
void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
BundleRanges& BR) {
for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
II != IE; ++II)
moveInternalFromInto(OldIdx, *II, BR);
}
void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
BundleRanges& BR) {
LiveInterval* LI = P.first;
LiveRange* LR = P.second;
assert(LR->start.isRegister() &&
"Don't know how to merge exiting ECs into bundles yet.");
if (LR->end > NewIdx.getDeadSlot()) {
if (BR[LI->reg].Dead != 0) {
LI->removeRange(*BR[LI->reg].Dead);
BR[LI->reg].Dead = 0;
}
assert(BR[LI->reg].Def == 0 &&
"Can't have two defs for the same variable exiting a bundle.");
LR->start = NewIdx.getRegSlot();
LR->valno->def = LR->start;
BR[LI->reg].Def = LR;
} else {
assert(LR->end == NewIdx.getRegSlot() &&
"Can't bundle def whose kill is before the bundle");
if (BR[LI->reg].Dead || BR[LI->reg].Def) {
LI->removeRange(*LR);
} else {
LR->end = NewIdx.getDeadSlot();
BR[LI->reg].Dead = LR;
assert(BR[LI->reg].Use == LR &&
"Range becoming dead should currently be use.");
}
BR[LI->reg].Use = 0;
}
}
void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
BundleRanges& BR) {
for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
EI != EE; ++EI)
moveExitingFromInto(OldIdx, *EI, BR);
}
};
void LiveIntervals::handleMove(MachineInstr* MI) {
SlotIndex OldIndex = indexes_->getInstructionIndex(MI);
indexes_->removeMachineInstrFromMaps(MI);
SlotIndex NewIndex = MI->isInsideBundle() ?
indexes_->getInstructionIndex(MI) :
indexes_->insertMachineInstrInMaps(MI);
assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
OldIndex < getMBBEndIdx(MI->getParent()) &&
"Cannot handle moves across basic block boundaries.");
assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
HMEditor HME(*this, *mri_, *tri_, NewIndex);
HME.moveAllRangesFrom(MI, OldIndex);
}
void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart) {
SlotIndex NewIndex = indexes_->getInstructionIndex(BundleStart);
HMEditor HME(*this, *mri_, *tri_, NewIndex);
HME.moveAllRangesInto(MI, BundleStart);
}