HexagonCallingConvLower.h [plain text]
#ifndef LLVM_Hexagon_CODEGEN_CALLINGCONVLOWER_H
#define LLVM_Hexagon_CODEGEN_CALLINGCONVLOWER_H
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/CallingConvLower.h"
namespace llvm {
class TargetRegisterInfo;
class TargetMachine;
class Hexagon_CCState;
class SDNode;
typedef bool Hexagon_CCAssignFn(unsigned ValNo, EVT ValVT,
EVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, Hexagon_CCState &State,
int NonVarArgsParams,
int CurrentParam,
bool ForceMem);
class Hexagon_CCState {
CallingConv::ID CallingConv;
bool IsVarArg;
const TargetMachine &TM;
const TargetRegisterInfo &TRI;
SmallVector<CCValAssign, 16> &Locs;
LLVMContext &Context;
unsigned StackOffset;
SmallVector<uint32_t, 16> UsedRegs;
public:
Hexagon_CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM,
SmallVector<CCValAssign, 16> &locs, LLVMContext &c);
void addLoc(const CCValAssign &V) {
Locs.push_back(V);
}
LLVMContext &getContext() const { return Context; }
const TargetMachine &getTarget() const { return TM; }
unsigned getCallingConv() const { return CallingConv; }
bool isVarArg() const { return IsVarArg; }
unsigned getNextStackOffset() const { return StackOffset; }
bool isAllocated(unsigned Reg) const {
return UsedRegs[Reg/32] & (1 << (Reg&31));
}
void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
Hexagon_CCAssignFn Fn, unsigned SretValueInRegs);
void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
Hexagon_CCAssignFn Fn, unsigned SretValueInRegs);
void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
Hexagon_CCAssignFn Fn, int NonVarArgsParams,
unsigned SretValueSize);
void AnalyzeCallOperands(SmallVectorImpl<EVT> &ArgVTs,
SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
Hexagon_CCAssignFn Fn);
void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
Hexagon_CCAssignFn Fn, unsigned SretValueInRegs);
void AnalyzeCallResult(EVT VT, Hexagon_CCAssignFn Fn);
unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
for (unsigned i = 0; i != NumRegs; ++i)
if (!isAllocated(Regs[i]))
return i;
return NumRegs;
}
unsigned AllocateReg(unsigned Reg) {
if (isAllocated(Reg)) return 0;
MarkAllocated(Reg);
return Reg;
}
unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
if (isAllocated(Reg)) return 0;
MarkAllocated(Reg);
MarkAllocated(ShadowReg);
return Reg;
}
unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
if (FirstUnalloc == NumRegs)
return 0;
unsigned Reg = Regs[FirstUnalloc];
MarkAllocated(Reg);
return Reg;
}
unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs,
unsigned NumRegs) {
unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
if (FirstUnalloc == NumRegs)
return 0;
unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
MarkAllocated(Reg);
MarkAllocated(ShadowReg);
return Reg;
}
unsigned AllocateStack(unsigned Size, unsigned Align) {
assert(Align && ((Align-1) & Align) == 0); StackOffset = ((StackOffset + Align-1) & ~(Align-1));
unsigned Result = StackOffset;
StackOffset += Size;
return Result;
}
void HandleByVal(unsigned ValNo, EVT ValVT,
EVT LocVT, CCValAssign::LocInfo LocInfo,
int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
private:
void MarkAllocated(unsigned Reg);
};
}
#endif