LLVMTargetMachine.cpp [plain text]
#include "llvm/Target/TargetMachine.h"
#include "llvm/PassManager.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/Analysis/Verifier.h"
#include "llvm/Assembly/PrintModulePass.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/ADT/OwningPtr.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
cl::desc("Disable Post Regalloc"));
static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
cl::desc("Disable branch folding"));
static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
cl::desc("Disable tail duplication"));
static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
cl::desc("Disable pre-register allocation tail duplication"));
static cl::opt<bool> EnableBlockPlacement("enable-block-placement",
cl::Hidden, cl::desc("Enable probability-driven block placement"));
static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
cl::desc("Disable code placement"));
static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
cl::desc("Disable Stack Slot Coloring"));
static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
cl::desc("Disable Machine Dead Code Elimination"));
static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
cl::desc("Disable Machine LICM"));
static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
cl::desc("Disable Machine Common Subexpression Elimination"));
static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
cl::Hidden,
cl::desc("Disable Machine LICM"));
static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
cl::desc("Disable Machine Sinking"));
static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
cl::desc("Disable Loop Strength Reduction Pass"));
static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
cl::desc("Disable Codegen Prepare"));
static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
cl::desc("Print LLVM IR produced by the loop-reduce pass"));
static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
cl::desc("Print LLVM IR input to isel pass"));
static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
cl::desc("Dump garbage collector data"));
static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
cl::desc("Show encoding in .s output"));
static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
cl::desc("Show instruction structure in .s output"));
static cl::opt<bool> EnableMCLogging("enable-mc-api-logging", cl::Hidden,
cl::desc("Enable MC API logging"));
static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
cl::desc("Verify generated machine code"),
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
static cl::opt<cl::boolOrDefault>
AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
cl::init(cl::BOU_UNSET));
static bool getVerboseAsm() {
switch (AsmVerbose) {
default:
case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
case cl::BOU_TRUE: return true;
case cl::BOU_FALSE: return false;
}
}
static cl::opt<cl::boolOrDefault>
EnableFastISelOption("fast-isel", cl::Hidden,
cl::desc("Enable the \"fast\" instruction selector"));
LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
StringRef CPU, StringRef FS,
TargetOptions Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: TargetMachine(T, Triple, CPU, FS, Options) {
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
AsmInfo = T.createMCAsmInfo(Triple);
assert(AsmInfo && "MCAsmInfo not initialized."
"Make sure you include the correct TargetSelect.h"
"and that InitializeAllTargetMCs() is being invoked!");
}
bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
formatted_raw_ostream &Out,
CodeGenFileType FileType,
bool DisableVerify) {
MCContext *Context = 0;
if (addCommonCodeGenPasses(PM, DisableVerify, Context))
return true;
assert(Context != 0 && "Failed to get MCContext");
if (hasMCSaveTempLabels())
Context->setAllowTemporaryLabels(false);
const MCAsmInfo &MAI = *getMCAsmInfo();
const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
OwningPtr<MCStreamer> AsmStreamer;
switch (FileType) {
default: return true;
case CGFT_AssemblyFile: {
MCInstPrinter *InstPrinter =
getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, STI);
MCCodeEmitter *MCE = 0;
MCAsmBackend *MAB = 0;
if (ShowMCEncoding) {
const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, *Context);
MAB = getTarget().createMCAsmBackend(getTargetTriple());
}
MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
getVerboseAsm(),
hasMCUseLoc(),
hasMCUseCFI(),
hasMCUseDwarfDirectory(),
InstPrinter,
MCE, MAB,
ShowMCInst);
AsmStreamer.reset(S);
break;
}
case CGFT_ObjectFile: {
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI,
*Context);
MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
if (MCE == 0 || MAB == 0)
return true;
AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(),
*Context, *MAB, Out,
MCE, hasMCRelaxAll(),
hasMCNoExecStack()));
AsmStreamer.get()->InitSections();
break;
}
case CGFT_Null:
AsmStreamer.reset(createNullStreamer(*Context));
break;
}
if (EnableMCLogging)
AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
if (Printer == 0)
return true;
AsmStreamer.take();
PM.add(Printer);
PM.add(createGCInfoDeleter());
return false;
}
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
JITCodeEmitter &JCE,
bool DisableVerify) {
MCContext *Ctx = 0;
if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
return true;
addCodeEmitter(PM, JCE);
PM.add(createGCInfoDeleter());
return false; }
bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
MCContext *&Ctx,
raw_ostream &Out,
bool DisableVerify) {
if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
return true;
if (hasMCSaveTempLabels())
Ctx->setAllowTemporaryLabels(false);
const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(),STI, *Ctx);
MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
if (MCE == 0 || MAB == 0)
return true;
OwningPtr<MCStreamer> AsmStreamer;
AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(), *Ctx,
*MAB, Out, MCE,
hasMCRelaxAll(),
hasMCNoExecStack()));
AsmStreamer.get()->InitSections();
FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
if (Printer == 0)
return true;
AsmStreamer.take();
PM.add(Printer);
return false; }
void LLVMTargetMachine::printNoVerify(PassManagerBase &PM,
const char *Banner) const {
if (Options.PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
}
void LLVMTargetMachine::printAndVerify(PassManagerBase &PM,
const char *Banner) const {
if (Options.PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
if (VerifyMachineCode)
PM.add(createMachineVerifierPass(Banner));
}
bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
bool DisableVerify,
MCContext *&OutContext) {
PM.add(createTypeBasedAliasAnalysisPass());
PM.add(createBasicAliasAnalysisPass());
if (!DisableVerify)
PM.add(createVerifierPass());
if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
}
PM.add(createGCLoweringPass());
PM.add(createUnreachableBlockEliminationPass());
switch (getMCAsmInfo()->getExceptionHandlingType()) {
case ExceptionHandling::SjLj:
PM.add(createSjLjEHPass(getTargetLowering()));
case ExceptionHandling::DwarfCFI:
case ExceptionHandling::ARM:
case ExceptionHandling::Win64:
PM.add(createDwarfEHPass(this));
break;
case ExceptionHandling::None:
PM.add(createLowerInvokePass(getTargetLowering()));
PM.add(createUnreachableBlockEliminationPass());
break;
}
if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering()));
addPreISel(PM);
if (PrintISelInput)
PM.add(createPrintFunctionPass("\n\n"
"*** Final LLVM Code input to ISel ***\n",
&dbgs()));
if (!DisableVerify)
PM.add(createVerifierPass());
MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(),
*getRegisterInfo(),
&getTargetLowering()->getObjFileLowering());
PM.add(MMI);
OutContext = &MMI->getContext();
PM.add(new MachineFunctionAnalysis(*this));
if (EnableFastISelOption == cl::BOU_TRUE ||
(getOptLevel() == CodeGenOpt::None &&
EnableFastISelOption != cl::BOU_FALSE))
Options.EnableFastISel = true;
if (addInstSelector(PM))
return true;
printAndVerify(PM, "After Instruction Selection");
PM.add(createExpandISelPseudosPass());
if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
PM.add(createTailDuplicatePass(true));
printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
}
if (getOptLevel() != CodeGenOpt::None)
PM.add(createOptimizePHIsPass());
PM.add(createLocalStackSlotAllocationPass());
if (getOptLevel() != CodeGenOpt::None) {
if (!DisableMachineDCE)
PM.add(createDeadMachineInstructionElimPass());
printAndVerify(PM, "After codegen DCE pass");
if (!DisableMachineLICM)
PM.add(createMachineLICMPass());
if (!DisableMachineCSE)
PM.add(createMachineCSEPass());
if (!DisableMachineSink)
PM.add(createMachineSinkingPass());
printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
PM.add(createPeepholeOptimizerPass());
printAndVerify(PM, "After codegen peephole optimization pass");
}
if (addPreRegAlloc(PM))
printAndVerify(PM, "After PreRegAlloc passes");
PM.add(createRegisterAllocator(getOptLevel()));
printAndVerify(PM, "After Register Allocation");
if (getOptLevel() != CodeGenOpt::None) {
if (!DisableSSC)
PM.add(createStackSlotColoringPass(false));
if (!DisablePostRAMachineLICM)
PM.add(createMachineLICMPass(false));
printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
}
if (addPostRegAlloc(PM))
printAndVerify(PM, "After PostRegAlloc passes");
PM.add(createExpandPostRAPseudosPass());
printAndVerify(PM, "After ExpandPostRAPseudos");
PM.add(createPrologEpilogCodeInserter());
printAndVerify(PM, "After PrologEpilogCodeInserter");
if (addPreSched2(PM))
printAndVerify(PM, "After PreSched2 passes");
if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
PM.add(createPostRAScheduler(getOptLevel()));
printAndVerify(PM, "After PostRAScheduler");
}
if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
printNoVerify(PM, "After BranchFolding");
}
if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
PM.add(createTailDuplicatePass(false));
printNoVerify(PM, "After TailDuplicate");
}
PM.add(createGCMachineCodeAnalysisPass());
if (PrintGCInfo)
PM.add(createGCInfoPrinter(dbgs()));
if (getOptLevel() != CodeGenOpt::None && !DisableCodePlace) {
if (EnableBlockPlacement) {
PM.add(createMachineBlockPlacementPass());
printNoVerify(PM, "After MachineBlockPlacement");
} else {
PM.add(createCodePlacementOptPass());
printNoVerify(PM, "After CodePlacementOpt");
}
if (EnableBlockPlacementStats) {
PM.add(createMachineBlockPlacementStatsPass());
printNoVerify(PM, "After MachineBlockPlacementStats");
}
}
if (addPreEmitPass(PM))
printNoVerify(PM, "After PreEmit passes");
return false;
}