extern int target_flags;
enum processor_type {
PROCESSOR_DEFAULT,
PROCESSOR_4KC,
PROCESSOR_5KC,
PROCESSOR_20KC,
PROCESSOR_M4K,
PROCESSOR_R3000,
PROCESSOR_R3900,
PROCESSOR_R6000,
PROCESSOR_R4000,
PROCESSOR_R4100,
PROCESSOR_R4111,
PROCESSOR_R4120,
PROCESSOR_R4130,
PROCESSOR_R4300,
PROCESSOR_R4600,
PROCESSOR_R4650,
PROCESSOR_R5000,
PROCESSOR_R5400,
PROCESSOR_R5500,
PROCESSOR_R7000,
PROCESSOR_R8000,
PROCESSOR_R9000,
PROCESSOR_SB1,
PROCESSOR_SR71000
};
#define ABI_32 0
#define ABI_N32 1
#define ABI_64 2
#define ABI_EABI 3
#define ABI_O64 4
struct mips_cpu_info {
const char *name;
enum processor_type cpu;
int isa;
};
extern char mips_print_operand_punct[256];
extern const char *current_function_file;
extern int num_source_filenames;
extern int mips_section_threshold;
extern int sym_lineno;
extern int set_noreorder;
extern int set_nomacro;
extern int set_noat;
extern int set_volatile;
extern int mips_branch_likely;
extern int mips_dbx_regno[];
extern GTY(()) rtx cmp_operands[2];
extern enum processor_type mips_arch;
extern enum processor_type mips_tune;
extern int mips_isa;
extern int mips_abi;
extern int mips16_hard_float;
extern const char *mips_arch_string;
extern const char *mips_tune_string;
extern const char *mips_isa_string;
extern const char *mips_abi_string;
extern const char *mips_cache_flush_func;
extern const char *mips_fix_vr4130_string;
extern const struct mips_cpu_info mips_cpu_info_table[];
extern const struct mips_cpu_info *mips_arch_info;
extern const struct mips_cpu_info *mips_tune_info;
#define BITMASK_HIGH (((unsigned long)1) << 31)
#define BITMASK_UPPER16 ((unsigned long)0xffff << 16)
#define BITMASK_LOWER16 ((unsigned long)0xffff)
#define MASK_INT64 0x00000001
#define MASK_LONG64 0x00000002
#define MASK_SPLIT_ADDR 0x00000004
#define MASK_NO_FUSED_MADD 0x00000008
#define MASK_EXPLICIT_RELOCS 0x00000010
#define MASK_MEMCPY 0x00000020
#define MASK_SOFT_FLOAT 0x00000040
#define MASK_FLOAT64 0x00000080
#define MASK_ABICALLS 0x00000100
#define MASK_XGOT 0x00000200
#define MASK_LONG_CALLS 0x00000400
#define MASK_64BIT 0x00000800
#define MASK_EMBEDDED_DATA 0x00001000
#define MASK_BIG_ENDIAN 0x00002000
#define MASK_SINGLE_FLOAT 0x00004000
#define MASK_MAD 0x00008000
#define MASK_4300_MUL_FIX 0x00010000
#define MASK_MIPS16 0x00020000
#define MASK_NO_CHECK_ZERO_DIV \
0x00040000
#define MASK_BRANCHLIKELY 0x00080000
#define MASK_UNINIT_CONST_IN_RODATA \
0x00100000
#define MASK_FIX_R4000 0x00200000
#define MASK_FIX_R4400 0x00400000
#define MASK_FIX_SB1 0x00800000
#define MASK_FIX_VR4120 0x01000000
#define MASK_VR4130_ALIGN 0x02000000
#define MASK_FP_EXCEPTIONS 0x04000000
#define MASK_DIVIDE_BREAKS 0x08000000
#define MASK_PAIRED_SINGLE 0x10000000
#define MASK_MIPS3D 0x20000000
#define MASK_SYM32 0x40000000
#define MASK_DEBUG 0
#define MASK_DEBUG_D 0
#define MASK_MIPS_TFILE 0
#define TARGET_INT64 ((target_flags & MASK_INT64) != 0)
#define TARGET_LONG64 ((target_flags & MASK_LONG64) != 0)
#define TARGET_FLOAT64 ((target_flags & MASK_FLOAT64) != 0)
#define TARGET_64BIT ((target_flags & MASK_64BIT) != 0)
#define TARGET_SPLIT_ADDRESSES ((target_flags & MASK_SPLIT_ADDR) != 0)
#define TARGET_DEBUG_MODE ((target_flags & MASK_DEBUG) != 0)
#define TARGET_DEBUG_D_MODE ((target_flags & MASK_DEBUG_D) != 0)
#define TARGET_MEMCPY ((target_flags & MASK_MEMCPY) != 0)
#define TARGET_ABICALLS ((target_flags & MASK_ABICALLS) != 0)
#define TARGET_XGOT ((target_flags & MASK_XGOT) != 0)
#define TARGET_SOFT_FLOAT ((target_flags & MASK_SOFT_FLOAT) != 0)
#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
#define TARGET_LONG_CALLS ((target_flags & MASK_LONG_CALLS) != 0)
#define TARGET_EMBEDDED_DATA ((target_flags & MASK_EMBEDDED_DATA) != 0)
#define TARGET_UNINIT_CONST_IN_RODATA \
((target_flags & MASK_UNINIT_CONST_IN_RODATA) != 0)
#define TARGET_BIG_ENDIAN ((target_flags & MASK_BIG_ENDIAN) != 0)
#define TARGET_SINGLE_FLOAT ((target_flags & MASK_SINGLE_FLOAT) != 0)
#define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
#define TARGET_MAD ((target_flags & MASK_MAD) != 0)
#define TARGET_FUSED_MADD ((target_flags & MASK_NO_FUSED_MADD) == 0)
#define TARGET_4300_MUL_FIX ((target_flags & MASK_4300_MUL_FIX) != 0)
#define TARGET_CHECK_ZERO_DIV ((target_flags & MASK_NO_CHECK_ZERO_DIV) == 0)
#define TARGET_DIVIDE_TRAPS ((target_flags & MASK_DIVIDE_BREAKS) == 0)
#define TARGET_BRANCHLIKELY ((target_flags & MASK_BRANCHLIKELY) != 0)
#define TARGET_FIX_SB1 ((target_flags & MASK_FIX_SB1) != 0)
#define TARGET_FIX_R4000 ((target_flags & MASK_FIX_R4000) != 0)
#define TARGET_FIX_R4400 ((target_flags & MASK_FIX_R4400) != 0)
#define TARGET_FIX_VR4120 ((target_flags & MASK_FIX_VR4120) != 0)
#define TARGET_FIX_VR4130 (mips_fix_vr4130_string != 0)
#define TARGET_VR4130_ALIGN ((target_flags & MASK_VR4130_ALIGN) != 0)
#define TARGET_FP_EXCEPTIONS ((target_flags & MASK_FP_EXCEPTIONS) != 0)
#define TARGET_PAIRED_SINGLE_FLOAT \
((target_flags & MASK_PAIRED_SINGLE) != 0)
#define TARGET_MIPS3D ((target_flags & MASK_MIPS3D) != 0)
#define TARGET_SYM32 ((target_flags & MASK_SYM32) != 0)
#define TARGET_EXPLICIT_RELOCS ((target_flags & MASK_EXPLICIT_RELOCS) != 0)
#define TARGET_SPLIT_CALLS \
(TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
#define TARGET_SIBCALLS \
(!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
#define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
#define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
#define ISA_MIPS1 (mips_isa == 1)
#define ISA_MIPS2 (mips_isa == 2)
#define ISA_MIPS3 (mips_isa == 3)
#define ISA_MIPS4 (mips_isa == 4)
#define ISA_MIPS32 (mips_isa == 32)
#define ISA_MIPS32R2 (mips_isa == 33)
#define ISA_MIPS64 (mips_isa == 64)
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
#define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
#define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
#define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
#define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
|| TUNE_MIPS4120 \
|| TUNE_MIPS4130)
#define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
#define TARGET_IRIX 0
#define TARGET_IRIX6 0
#define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
do \
{ \
char *macro, *p; \
\
macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
for (p = macro; *p != 0; p++) \
*p = TOUPPER (*p); \
\
builtin_define (macro); \
builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
free (macro); \
} \
while (0)
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
\
if (!TARGET_IRIX) \
builtin_assert ("machine=mips"); \
\
builtin_assert ("cpu=mips"); \
builtin_define ("__mips__"); \
builtin_define ("_mips"); \
\
\
if (!flag_iso) \
builtin_define ("mips"); \
\
if (TARGET_64BIT) \
builtin_define ("__mips64"); \
\
if (!TARGET_IRIX) \
{ \
\
if (TARGET_64BIT) \
{ \
builtin_define_std ("R4000"); \
builtin_define ("_R4000"); \
} \
else \
{ \
builtin_define_std ("R3000"); \
builtin_define ("_R3000"); \
} \
} \
if (TARGET_FLOAT64) \
builtin_define ("__mips_fpr=64"); \
else \
builtin_define ("__mips_fpr=32"); \
\
if (TARGET_MIPS16) \
builtin_define ("__mips16"); \
\
if (TARGET_MIPS3D) \
builtin_define ("__mips3d"); \
\
MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
\
if (ISA_MIPS1) \
{ \
builtin_define ("__mips=1"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
} \
else if (ISA_MIPS2) \
{ \
builtin_define ("__mips=2"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
} \
else if (ISA_MIPS3) \
{ \
builtin_define ("__mips=3"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
} \
else if (ISA_MIPS4) \
{ \
builtin_define ("__mips=4"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
} \
else if (ISA_MIPS32) \
{ \
builtin_define ("__mips=32"); \
builtin_define ("__mips_isa_rev=1"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
} \
else if (ISA_MIPS32R2) \
{ \
builtin_define ("__mips=32"); \
builtin_define ("__mips_isa_rev=2"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
} \
else if (ISA_MIPS64) \
{ \
builtin_define ("__mips=64"); \
builtin_define ("__mips_isa_rev=1"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
} \
\
if (TARGET_HARD_FLOAT) \
builtin_define ("__mips_hard_float"); \
else if (TARGET_SOFT_FLOAT) \
builtin_define ("__mips_soft_float"); \
\
if (TARGET_SINGLE_FLOAT) \
builtin_define ("__mips_single_float"); \
\
if (TARGET_PAIRED_SINGLE_FLOAT) \
builtin_define ("__mips_paired_single_float"); \
\
if (TARGET_BIG_ENDIAN) \
{ \
builtin_define_std ("MIPSEB"); \
builtin_define ("_MIPSEB"); \
} \
else \
{ \
builtin_define_std ("MIPSEL"); \
builtin_define ("_MIPSEL"); \
} \
\
\
if (preprocessing_asm_p ()) \
{ \
builtin_define_std ("LANGUAGE_ASSEMBLY"); \
builtin_define ("_LANGUAGE_ASSEMBLY"); \
} \
else if (c_dialect_cxx ()) \
{ \
builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
} \
else \
{ \
builtin_define_std ("LANGUAGE_C"); \
builtin_define ("_LANGUAGE_C"); \
} \
if (c_dialect_objc ()) \
{ \
builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
\
builtin_define_std ("LANGUAGE_C"); \
builtin_define ("_LANGUAGE_C"); \
} \
\
if (mips_abi == ABI_EABI) \
builtin_define ("__mips_eabi"); \
\
} while (0)
#define TARGET_SWITCHES \
{ \
SUBTARGET_TARGET_SWITCHES \
{"int64", MASK_INT64 | MASK_LONG64, \
N_("Use 64-bit int type")}, \
{"long64", MASK_LONG64, \
N_("Use 64-bit long type")}, \
{"long32", -(MASK_LONG64 | MASK_INT64), \
N_("Use 32-bit long type")}, \
{"split-addresses", MASK_SPLIT_ADDR, \
N_("Optimize lui/addiu address loads")}, \
{"no-split-addresses", -MASK_SPLIT_ADDR, \
N_("Don't optimize lui/addiu address loads")}, \
{"gas", 0, \
N_("Use GNU as (now ignored)")}, \
{"gpOPT", 0, \
N_("Use GP relative sdata/sbss sections (now ignored)")}, \
{"gpopt", 0, \
N_("Use GP relative sdata/sbss sections (now ignored)")}, \
{"no-gpOPT", 0, \
N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
{"no-gpopt", 0, \
N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
{"stats", 0, \
N_("Output compiler statistics (now ignored)")}, \
{"no-stats", 0, \
N_("Don't output compiler statistics")}, \
{"memcpy", MASK_MEMCPY, \
N_("Don't optimize block moves")}, \
{"no-memcpy", -MASK_MEMCPY, \
N_("Optimize block moves")}, \
{"mips-tfile", MASK_MIPS_TFILE, \
N_("Use mips-tfile asm postpass")}, \
{"no-mips-tfile", -MASK_MIPS_TFILE, \
N_("Don't use mips-tfile asm postpass")}, \
{"soft-float", MASK_SOFT_FLOAT, \
N_("Use software floating point")}, \
{"hard-float", -MASK_SOFT_FLOAT, \
N_("Use hardware floating point")}, \
{"fp64", MASK_FLOAT64, \
N_("Use 64-bit FP registers")}, \
{"fp32", -MASK_FLOAT64, \
N_("Use 32-bit FP registers")}, \
{"gp64", MASK_64BIT, \
N_("Use 64-bit general registers")}, \
{"gp32", -MASK_64BIT, \
N_("Use 32-bit general registers")}, \
{"abicalls", MASK_ABICALLS, \
N_("Use Irix PIC")}, \
{"no-abicalls", -MASK_ABICALLS, \
N_("Don't use Irix PIC")}, \
{"long-calls", MASK_LONG_CALLS, \
N_("Use indirect calls")}, \
{"no-long-calls", -MASK_LONG_CALLS, \
N_("Don't use indirect calls")}, \
{"embedded-data", MASK_EMBEDDED_DATA, \
N_("Use ROM instead of RAM")}, \
{"no-embedded-data", -MASK_EMBEDDED_DATA, \
N_("Don't use ROM instead of RAM")}, \
{"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
{"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
N_("Don't put uninitialized constants in ROM")}, \
{"eb", MASK_BIG_ENDIAN, \
N_("Use big-endian byte order")}, \
{"el", -MASK_BIG_ENDIAN, \
N_("Use little-endian byte order")}, \
{"single-float", MASK_SINGLE_FLOAT, \
N_("Use single (32-bit) FP only")}, \
{"double-float", -MASK_SINGLE_FLOAT, \
N_("Don't use single (32-bit) FP only")}, \
{"paired-single", MASK_PAIRED_SINGLE, \
N_("Use paired-single floating point instructions")}, \
{"no-paired-single", -MASK_PAIRED_SINGLE, \
N_("Use paired-single floating point instructions")}, \
{"ips3d", MASK_MIPS3D, \
N_("Use MIPS-3D instructions")}, \
{"no-mips3d", -MASK_MIPS3D, \
N_("Use MIPS-3D instructions")}, \
{"mad", MASK_MAD, \
N_("Use multiply accumulate")}, \
{"no-mad", -MASK_MAD, \
N_("Don't use multiply accumulate")}, \
{"no-fused-madd", MASK_NO_FUSED_MADD, \
N_("Don't generate fused multiply/add instructions")}, \
{"fused-madd", -MASK_NO_FUSED_MADD, \
N_("Generate fused multiply/add instructions")}, \
{"vr4130-align", MASK_VR4130_ALIGN, \
N_("Perform VR4130-specific alignment optimizations")}, \
{"no-vr4130-align", -MASK_VR4130_ALIGN, \
N_("Don't perform VR4130-specific alignment optimizations")}, \
{"fix4300", MASK_4300_MUL_FIX, \
N_("Work around early 4300 hardware bug")}, \
{"no-fix4300", -MASK_4300_MUL_FIX, \
N_("Don't work around early 4300 hardware bug")}, \
{"fix-sb1", MASK_FIX_SB1, \
N_("Work around errata for early SB-1 revision 2 cores")}, \
{"no-fix-sb1", -MASK_FIX_SB1, \
N_("Don't work around errata for early SB-1 revision 2 cores")}, \
{"fix-r4000", MASK_FIX_R4000, \
N_("Work around R4000 errata")}, \
{"no-fix-r4000", -MASK_FIX_R4000, \
N_("Don't work around R4000 errata")}, \
{"fix-r4400", MASK_FIX_R4400, \
N_("Work around R4400 errata")}, \
{"no-fix-r4400", -MASK_FIX_R4400, \
N_("Don't work around R4400 errata")}, \
{"fix-vr4120", MASK_FIX_VR4120, \
N_("Work around certain VR4120 errata")}, \
{"no-fix-vr4120", -MASK_FIX_VR4120, \
N_("Don't work around certain VR4120 errata")}, \
{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
N_("Trap on integer divide by zero")}, \
{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
N_("Don't trap on integer divide by zero")}, \
{"divide-traps", -MASK_DIVIDE_BREAKS, \
N_("Use trap to check for integer divide by zero")}, \
{"divide-breaks", MASK_DIVIDE_BREAKS, \
N_("Use break to check for integer divide by zero")}, \
{ "branch-likely", MASK_BRANCHLIKELY, \
N_("Use Branch Likely instructions, overriding default for arch")}, \
{ "no-branch-likely", -MASK_BRANCHLIKELY, \
N_("Don't use Branch Likely instructions, overriding default for arch")}, \
{"explicit-relocs", MASK_EXPLICIT_RELOCS, \
N_("Use NewABI-style %reloc() assembly operators")}, \
{"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
N_("Use assembler macros instead of relocation operators")}, \
{"ips16", MASK_MIPS16, \
N_("Generate mips16 code") }, \
{"no-mips16", -MASK_MIPS16, \
N_("Generate normal-mode code") }, \
{"xgot", MASK_XGOT, \
N_("Lift restrictions on GOT size") }, \
{"no-xgot", -MASK_XGOT, \
N_("Do not lift restrictions on GOT size") }, \
{"fp-exceptions", MASK_FP_EXCEPTIONS, \
N_("FP exceptions are enabled") }, \
{"no-fp-exceptions", -MASK_FP_EXCEPTIONS, \
N_("FP exceptions are not enabled") }, \
{"sym32", MASK_SYM32, \
N_("Assume all symbols have 32-bit values") }, \
{"no-sym32", -MASK_SYM32, \
N_("Don't assume all symbols have 32-bit values") }, \
{"debug", MASK_DEBUG, \
NULL}, \
{"debugd", MASK_DEBUG_D, \
NULL}, \
{"", (TARGET_DEFAULT \
| TARGET_CPU_DEFAULT \
| TARGET_ENDIAN_DEFAULT \
| TARGET_FP_EXCEPTIONS_DEFAULT), \
NULL}, \
}
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#endif
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT 0
#endif
#ifndef TARGET_ENDIAN_DEFAULT
#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
#endif
#ifndef TARGET_FP_EXCEPTIONS_DEFAULT
#define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
#endif
#ifndef MIPS_ISA_DEFAULT
#ifndef MIPS_CPU_STRING_DEFAULT
#define MIPS_CPU_STRING_DEFAULT "from-abi"
#endif
#endif
#ifdef IN_LIBGCC2
#undef TARGET_64BIT
#ifdef __mips64
#define TARGET_64BIT 1
#else
#define TARGET_64BIT 0
#endif
#endif
#ifndef MULTILIB_ENDIAN_DEFAULT
#if TARGET_ENDIAN_DEFAULT == 0
#define MULTILIB_ENDIAN_DEFAULT "EL"
#else
#define MULTILIB_ENDIAN_DEFAULT "EB"
#endif
#endif
#ifndef MULTILIB_ISA_DEFAULT
# if MIPS_ISA_DEFAULT == 1
# define MULTILIB_ISA_DEFAULT "mips1"
# else
# if MIPS_ISA_DEFAULT == 2
# define MULTILIB_ISA_DEFAULT "mips2"
# else
# if MIPS_ISA_DEFAULT == 3
# define MULTILIB_ISA_DEFAULT "mips3"
# else
# if MIPS_ISA_DEFAULT == 4
# define MULTILIB_ISA_DEFAULT "mips4"
# else
# if MIPS_ISA_DEFAULT == 32
# define MULTILIB_ISA_DEFAULT "mips32"
# else
# if MIPS_ISA_DEFAULT == 33
# define MULTILIB_ISA_DEFAULT "mips32r2"
# else
# if MIPS_ISA_DEFAULT == 64
# define MULTILIB_ISA_DEFAULT "mips64"
# else
# define MULTILIB_ISA_DEFAULT "mips1"
# endif
# endif
# endif
# endif
# endif
# endif
# endif
#endif
#ifndef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS \
{ MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
#endif
#ifndef ENDIAN_SPEC
#if TARGET_ENDIAN_DEFAULT == 0
#define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
#else
#define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
#endif
#endif
#define TARGET_OPTIONS \
{ \
SUBTARGET_TARGET_OPTIONS \
{ "tune=", &mips_tune_string, \
N_("Specify CPU for scheduling purposes"), 0}, \
{ "arch=", &mips_arch_string, \
N_("Specify CPU for code generation purposes"), 0}, \
{ "abi=", &mips_abi_string, \
N_("Specify an ABI"), 0}, \
{ "ips", &mips_isa_string, \
N_("Specify a Standard MIPS ISA"), 0}, \
{ "no-flush-func", &mips_cache_flush_func, \
N_("Don't call any cache flush functions"), 0}, \
{ "flush-func=", &mips_cache_flush_func, \
N_("Specify cache flush function"), 0}, \
{ "fix-vr4130", &mips_fix_vr4130_string, \
N_("Work around VR4130 mflo/mfhi errata"), 0}, \
}
#define SUBTARGET_TARGET_OPTIONS
#define OPTION_DEFAULT_SPECS \
{"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
{"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
{"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
{"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
{"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
#define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
&& ISA_HAS_COND_TRAP)
#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
&& !TARGET_SR71K \
&& !TARGET_MIPS16)
#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_MIPS7000 \
|| TARGET_MIPS9000 \
|| TARGET_MAD \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
#define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
&& !TARGET_MIPS16)
#define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
#define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
#define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
|| ISA_MIPS4 \
|| ISA_MIPS64)
#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
#define ISA_HAS_8CC (ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64)
#define ISA_HAS_FP4 ((ISA_MIPS4 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
&& !TARGET_MIPS16)
#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
) && !TARGET_MIPS16)
#define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
|| ISA_MIPS64) \
&& (!TARGET_MIPS5400 || TARGET_MAD) \
&& ! TARGET_MIPS16)
#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
) && !TARGET_MIPS16)
#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
&& !TARGET_MIPS16)
#define ISA_HAS_MULHI (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
#define ISA_HAS_MULS (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
#define ISA_HAS_MSAC (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
#define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
|| (TARGET_MIPS4130 && !TARGET_MIPS16) \
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
#define ISA_HAS_MACCHI (!TARGET_MIPS16 \
&& (TARGET_MIPS4120 \
|| TARGET_MIPS4130))
#define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
))
#define ISA_HAS_ROTR_DI (TARGET_64BIT \
&& !TARGET_MIPS16 \
&& (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
))
#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
#define ISA_HAS_TRUNC_W (!ISA_MIPS1)
#define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
))
#define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
&& !TARGET_MIPS3900 \
&& !TARGET_MIPS16)
#define ISA_HAS_XFER_DELAY (mips_isa <= 3)
#define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
|| TARGET_MIPS5500)
#undef SWITCH_TAKES_ARG
#define SWITCH_TAKES_ARG(CHAR) \
(DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
#define OVERRIDE_OPTIONS override_options ()
#define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
#define CAN_DEBUG_WITHOUT_FP
#ifndef NM_FLAGS
#define NM_FLAGS "-Bn"
#endif
#define SUBTARGET_TARGET_SWITCHES
#ifndef MIPS_ABI_DEFAULT
#define MIPS_ABI_DEFAULT ABI_32
#endif
#if MIPS_ABI_DEFAULT == ABI_32
#define MULTILIB_ABI_DEFAULT "mabi=32"
#endif
#if MIPS_ABI_DEFAULT == ABI_O64
#define MULTILIB_ABI_DEFAULT "mabi=o64"
#endif
#if MIPS_ABI_DEFAULT == ABI_N32
#define MULTILIB_ABI_DEFAULT "mabi=n32"
#endif
#if MIPS_ABI_DEFAULT == ABI_64
#define MULTILIB_ABI_DEFAULT "mabi=64"
#endif
#if MIPS_ABI_DEFAULT == ABI_EABI
#define MULTILIB_ABI_DEFAULT "mabi=eabi"
#endif
#ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
#define SUBTARGET_ASM_OPTIMIZING_SPEC "\
%{noasmopt:-O0} \
%{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
#endif
#ifndef SUBTARGET_ASM_DEBUGGING_SPEC
#define SUBTARGET_ASM_DEBUGGING_SPEC "\
%{g} %{g0} %{g1} %{g2} %{g3} \
%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
%{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
#endif
#ifndef SUBTARGET_ASM_SPEC
#define SUBTARGET_ASM_SPEC ""
#endif
#undef ASM_SPEC
#define ASM_SPEC "\
%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
%{mips32} %{mips32r2} %{mips64} \
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
%{mips3d:-mips3d} \
%{mfix-vr4120} %{mfix-vr4130} \
%(subtarget_asm_optimizing_spec) \
%(subtarget_asm_debugging_spec) \
%{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
%{msym32} %{mno-sym32} \
%{mtune=*} %{v} \
%(subtarget_asm_spec)"
#ifndef LINK_SPEC
#define LINK_SPEC "\
%(endian_spec) \
%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
%{bestGnum} %{shared} %{non_shared}"
#endif
#ifndef SUBTARGET_CC1_SPEC
#define SUBTARGET_CC1_SPEC ""
#endif
#ifndef CC1_SPEC
#define CC1_SPEC "\
%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
%{save-temps: } \
%(subtarget_cc1_spec)"
#endif
#ifndef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC ""
#endif
#define CPP_SPEC "%(subtarget_cpp_spec)"
#define EXTRA_SPECS \
{ "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
{ "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
{ "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
{ "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
{ "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
{ "endian_spec", ENDIAN_SPEC }, \
SUBTARGET_EXTRA_SPECS
#ifndef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#endif
#define DBX_DEBUGGING_INFO 1
#define MIPS_DEBUGGING_INFO 1
#define DWARF2_DEBUGGING_INFO 1
#ifndef PREFERRED_DEBUGGING_TYPE
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
#endif
#define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
#define DEFAULT_GDB_EXTENSIONS 1
#ifndef LOCAL_LABEL_PREFIX
#define LOCAL_LABEL_PREFIX "$"
#endif
#ifndef USER_LABEL_PREFIX
#define USER_LABEL_PREFIX ""
#endif
#undef DBX_CONTIN_LENGTH
#define DBX_CONTIN_LENGTH 1500
#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
#define DWARF_FRAME_REGNUM(REG) (REG)
#define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
#define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
#define EH_RETURN_DATA_REGNO(N) \
((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
#define DWARF_CIE_DATA_ALIGNMENT -4
#define DEBUGGER_AUTO_OFFSET(X) \
mips_debugger_offset (X, (HOST_WIDE_INT) 0)
#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
#if !defined(MIPSEL) && !defined(__MIPSEL__)
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#else
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#endif
#define MAX_BITS_PER_WORD 64
#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
#define MIN_UNITS_PER_WORD 4
#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
#define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
#define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
#define UNITS_PER_FPVALUE \
(TARGET_SOFT_FLOAT ? 0 \
: TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
: LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
#define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : 0)
#define SHORT_TYPE_SIZE 16
#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
#define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
#ifdef IN_LIBGCC2
#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
|| (defined _ABI64 && _MIPS_SIM == _ABI64)
# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
# else
# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
# endif
#endif
#ifndef POINTER_SIZE
#define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
#endif
#define PARM_BOUNDARY BITS_PER_WORD
#define FUNCTION_BOUNDARY 32
#define EMPTY_FIELD_BOUNDARY 32
#define STRUCTURE_SIZE_BOUNDARY 8
#define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
#define STRICT_ALIGNMENT 1
#define PCC_BITFIELD_TYPE_MATTERS 1
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
#undef DATA_ALIGNMENT
#define DATA_ALIGNMENT(TYPE, ALIGN) \
((((ALIGN) < BITS_PER_WORD) \
&& (TREE_CODE (TYPE) == ARRAY_TYPE \
|| TREE_CODE (TYPE) == UNION_TYPE \
|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
#define PAD_VARARGS_DOWN \
(FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
#define WORD_REGISTER_OPERATIONS
#define LOAD_EXTEND_OP(MODE) \
(TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
? SIGN_EXTEND : ZERO_EXTEND)
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
{ \
if ((MODE) == SImode) \
(UNSIGNEDP) = 0; \
(MODE) = Pmode; \
}
#define SHORT_IMMEDIATES_SIGN_EXTEND
#define FIRST_PSEUDO_REGISTER 176
#define FIXED_REGISTERS \
{ \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
}
#define CALL_USED_REGISTERS \
{ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
}
#define CALL_REALLY_USED_REGISTERS \
{ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
}
#define GP_REG_FIRST 0
#define GP_REG_LAST 31
#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
#define GP_DBX_FIRST 0
#define FP_REG_FIRST 32
#define FP_REG_LAST 63
#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
#define MD_REG_FIRST 64
#define MD_REG_LAST 65
#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
#define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
#define ST_REG_FIRST 67
#define ST_REG_LAST 74
#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
#define COP0_REG_FIRST 80
#define COP0_REG_LAST 111
#define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
#define COP2_REG_FIRST 112
#define COP2_REG_LAST 143
#define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
#define COP3_REG_FIRST 144
#define COP3_REG_LAST 175
#define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
#define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
#define AT_REGNUM (GP_REG_FIRST + 1)
#define HI_REGNUM (MD_REG_FIRST + 0)
#define LO_REGNUM (MD_REG_FIRST + 1)
#define FPSW_REGNUM ST_REG_FIRST
#define GP_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
#define M16_REG_P(REGNO) \
(((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
#define FP_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
#define MD_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
#define ST_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
#define COP0_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
#define COP2_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
#define COP3_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
#define ALL_COP_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
#define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
#define CONST_GP_P(X) \
(GET_CODE (X) == CONST \
&& GET_CODE (XEXP (X, 0)) == UNSPEC \
&& XINT (XEXP (X, 0), 1) == UNSPEC_GP)
#define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
(COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
: COP3_REG_P (REGNO) ? '3' : '?')
#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
#define MODES_TIEABLE_P(MODE1, MODE2) \
((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
== (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
#define ARG_POINTER_REGNUM 77
#define FRAME_POINTER_REGNUM 78
#define HARD_FRAME_POINTER_REGNUM \
(TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
#define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
#define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
#define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
#define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
#define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
#define NO_FUNCTION_CSE 1
#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
#define PIC_OFFSET_TABLE_REGNUM \
(reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
#define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
enum reg_class
{
NO_REGS,
M16_NA_REGS,
M16_REGS,
T_REG,
M16_T_REGS,
PIC_FN_ADDR_REG,
LEA_REGS,
GR_REGS,
FP_REGS,
HI_REG,
LO_REG,
MD_REGS,
COP0_REGS,
COP2_REGS,
COP3_REGS,
HI_AND_GR_REGS,
LO_AND_GR_REGS,
HI_AND_FP_REGS,
COP0_AND_GR_REGS,
COP2_AND_GR_REGS,
COP3_AND_GR_REGS,
ALL_COP_REGS,
ALL_COP_AND_GR_REGS,
ST_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define GENERAL_REGS GR_REGS
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"M16_NA_REGS", \
"M16_REGS", \
"T_REG", \
"M16_T_REGS", \
"PIC_FN_ADDR_REG", \
"LEA_REGS", \
"GR_REGS", \
"FP_REGS", \
"HI_REG", \
"LO_REG", \
"MD_REGS", \
\
"COP0_REGS", \
"COP2_REGS", \
"COP3_REGS", \
"HI_AND_GR_REGS", \
"LO_AND_GR_REGS", \
"HI_AND_FP_REGS", \
"COP0_AND_GR_REGS", \
"COP2_AND_GR_REGS", \
"COP3_AND_GR_REGS", \
"ALL_COP_REGS", \
"ALL_COP_AND_GR_REGS", \
"ST_REGS", \
"ALL_REGS" \
}
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
{ 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
{ 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
{ 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
{ 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } \
}
extern const enum reg_class mips_regno_to_class[];
#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
#define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
#define INDEX_REG_CLASS NO_REGS
#define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
#define GR_REG_CLASS_P(CLASS) \
((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
|| (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
|| (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
#define COP_REG_CLASS_P(CLASS) \
((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
#define REG_ALLOC_ORDER \
{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
}
#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
extern enum reg_class mips_char_to_class[256];
#define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
#define SMALL_OPERAND(VALUE) \
((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
#define SMALL_OPERAND_UNSIGNED(VALUE) \
(((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
#define LUI_OPERAND(VALUE) \
(((VALUE) | 0x7fff0000) == 0x7fff0000 \
|| ((VALUE) | 0x7fff0000) + 0x10000 == 0)
#define CONST_HIGH_PART(VALUE) \
(((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
#define CONST_LOW_PART(VALUE) \
((VALUE) - CONST_HIGH_PART (VALUE))
#define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
#define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
#define LUI_INT(X) LUI_OPERAND (INTVAL (X))
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'I' ? SMALL_OPERAND (VALUE) \
: (C) == 'J' ? ((VALUE) == 0) \
: (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
: (C) == 'L' ? LUI_OPERAND (VALUE) \
: (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
&& !SMALL_OPERAND_UNSIGNED (VALUE) \
&& !LUI_OPERAND (VALUE)) \
: (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
: (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
: (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
: 0)
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'G' \
&& (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
#define EXTRA_CONSTRAINT_Y(OP,STR) \
(((STR)[1] == 'G') ? (GET_CODE (OP) == CONST_VECTOR \
&& (OP) == CONST0_RTX (GET_MODE (OP))) \
: FALSE)
#define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \
(((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
: ((CODE) == 'R') ? (MEM_P (OP) \
&& mips_fetch_insns (OP) == 1) \
: ((CODE) == 'S') ? (CONSTANT_P (OP) \
&& call_insn_operand (OP, VOIDmode)) \
: ((CODE) == 'T') ? (CONSTANT_P (OP) \
&& move_operand (OP, VOIDmode) \
&& mips_dangerous_for_la25_p (OP)) \
: ((CODE) == 'U') ? (CONSTANT_P (OP) \
&& move_operand (OP, VOIDmode) \
&& !mips_dangerous_for_la25_p (OP)) \
: ((CODE) == 'W') ? (MEM_P (OP) \
&& memory_operand (OP, VOIDmode) \
&& (!TARGET_MIPS16 \
|| (!stack_operand (OP, VOIDmode) \
&& !CONSTANT_P (XEXP (OP, 0))))) \
: ((CODE) == 'Y') ? EXTRA_CONSTRAINT_Y (OP, STR) \
: FALSE)
#define CONSTRAINT_LEN(C,STR) \
(((C) == 'Y') ? 2 \
: DEFAULT_CONSTRAINT_LEN (C, STR))
#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
mips_preferred_reload_class (X, CLASS)
#if 0
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
((!TARGET_DEBUG_H_MODE \
&& GET_MODE_CLASS (MODE) == MODE_INT \
&& ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
|| (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
|| (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
&& ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
|| (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
#endif
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
mips_secondary_reload_class (CLASS, MODE, X, 1)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
mips_secondary_reload_class (CLASS, MODE, X, 0)
#define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
mips_cannot_change_mode_class (FROM, TO, CLASS)
#define STACK_GROWS_DOWNWARD
#define STARTING_FRAME_OFFSET \
((flag_profile_values && ! TARGET_64BIT \
? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
: current_function_outgoing_args_size) \
+ (TARGET_ABICALLS && !TARGET_NEWABI \
? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
#define RETURN_ADDR_RTX mips_return_addr
#define MASK_RETURN_ADDR GEN_INT (-2)
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
{ ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
{ FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
#define CAN_ELIMINATE(FROM, TO) \
((TO) == HARD_FRAME_POINTER_REGNUM \
|| ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
&& (!TARGET_MIPS16 \
|| compute_frame_size (get_frame_size ()) < 32768)))
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
(OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
#define ACCUMULATE_OUTGOING_ARGS 1
#define FIRST_PARM_OFFSET(FNDECL) 0
#define REG_PARM_STACK_SPACE(FNDECL) \
(TARGET_OLDABI \
? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
: 0)
#define OUTGOING_REG_PARM_STACK_SPACE
#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
#define GP_RETURN (GP_REG_FIRST + 2)
#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
#define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
#define GP_ARG_FIRST (GP_REG_FIRST + 4)
#define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
#define FP_ARG_FIRST (FP_REG_FIRST + 12)
#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
#define LIBCALL_VALUE(MODE) \
mips_function_value (NULL_TREE, NULL, (MODE))
#define FUNCTION_VALUE(VALTYPE, FUNC) \
mips_function_value ((VALTYPE), (FUNC), VOIDmode)
#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
|| (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
&& (N) == FP_RETURN + 2))
#define FUNCTION_ARG_REGNO_P(N) \
((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
|| (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
&& !fixed_regs[N])
typedef struct mips_args {
int gp_reg_found;
unsigned int arg_number;
unsigned int num_gprs;
unsigned int num_fprs;
unsigned int stack_words;
int fp_code;
int prototype;
} CUMULATIVE_ARGS;
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
function_arg_advance (&CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
function_arg( &CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG_BOUNDARY function_arg_boundary
#define FUNCTION_ARG_PADDING(MODE, TYPE) \
(mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
(mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
#define EABI_FLOAT_VARARGS_P \
(mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
#define EPILOGUE_USES(REGNO) ((REGNO) == 31)
#define MIPS_STACK_ALIGN(LOC) \
(TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
mips_va_start (valist, nextarg)
#define FUNCTION_PROFILER(FILE, LABELNO) \
{ \
if (TARGET_MIPS16) \
sorry ("mips16 function profiling"); \
fprintf (FILE, "\t.set\tnoat\n"); \
fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
if (!TARGET_NEWABI) \
{ \
fprintf (FILE, \
"\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
TARGET_64BIT ? "dsubu" : "subu", \
reg_names[STACK_POINTER_REGNUM], \
reg_names[STACK_POINTER_REGNUM], \
Pmode == DImode ? 16 : 8); \
} \
fprintf (FILE, "\tjal\t_mcount\n"); \
fprintf (FILE, "\t.set\tat\n"); \
}
#define EXIT_IGNORE_STACK 1
#define TRAMPOLINE_TEMPLATE(STREAM) \
{ \
fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
if (ptr_mode == DImode) \
{ \
fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
} \
else \
{ \
fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
} \
fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
if (ptr_mode == DImode) \
{ \
fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
} \
else \
{ \
fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
} \
}
#define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
#define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
#ifndef CACHE_FLUSH_FUNC
#define CACHE_FLUSH_FUNC "_flush_cache"
#endif
#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
{ \
rtx func_addr, chain_addr; \
\
func_addr = plus_constant (ADDR, 32); \
chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
\
\
\
if (mips_cache_flush_func && mips_cache_flush_func[0]) \
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
0, VOIDmode, 3, ADDR, Pmode, \
GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
GEN_INT (3), TYPE_MODE (integer_type_node)); \
}
#define REGNO_OK_FOR_INDEX_P(REGNO) 0
#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
#ifndef REG_OK_STRICT
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
#else
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
#endif
#define REG_OK_FOR_INDEX_P(X) 0
#define MAX_REGS_PER_ADDRESS 1
#ifdef REG_OK_STRICT
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ \
if (mips_legitimate_address_p (MODE, X, 1)) \
goto ADDR; \
}
#else
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ \
if (mips_legitimate_address_p (MODE, X, 0)) \
goto ADDR; \
}
#endif
#define CONSTANT_ADDRESS_P(X) \
(CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
#define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
do { \
if (mips_legitimize_address (&(X), MODE)) \
goto WIN; \
} while (0)
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
#define ASM_OUTPUT_LABELREF(FILE,NAME) \
if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
asm_fprintf ((FILE), "%U%s", \
XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
else \
asm_fprintf ((FILE), "%U%s", (NAME))
#define CASE_VECTOR_MODE \
(TARGET_MIPS16 ? HImode : ptr_mode)
#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
#ifndef DEFAULT_SIGNED_CHAR
#define DEFAULT_SIGNED_CHAR 1
#endif
#define MOVE_MAX (TARGET_64BIT ? 8 : 4)
#define MAX_MOVE_MAX 8
#define SLOW_BYTE_ACCESS 1
#define SHIFT_COUNT_TRUNCATED 1
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
(TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
#ifndef Pmode
#define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
#endif
#define FUNCTION_MODE SImode
#define CONSTANT_POOL_COST COSTS_N_INSNS (8)
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
mips_register_move_cost (MODE, FROM, TO)
#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
(((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
+ memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
#define AVOID_CCMODE_COPIES
#define BRANCH_COST \
((! TARGET_MIPS16 \
&& (TUNE_MIPS4000 || TUNE_MIPS6000)) \
? 2 : 1)
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
#ifndef ASM_APP_ON
#define ASM_APP_ON " #APP\n"
#endif
#ifndef ASM_APP_OFF
#define ASM_APP_OFF " #NO_APP\n"
#endif
#define REGISTER_NAMES \
{ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
"$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
"hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
"$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
"$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
"$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
"$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
"$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
"$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
"$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
"$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
"$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
"$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
"$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
"$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
"$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31" }
#define ADDITIONAL_REGISTER_NAMES \
{ \
{ "$29", 29 + GP_REG_FIRST }, \
{ "$30", 30 + GP_REG_FIRST }, \
{ "at", 1 + GP_REG_FIRST }, \
{ "v0", 2 + GP_REG_FIRST }, \
{ "v1", 3 + GP_REG_FIRST }, \
{ "a0", 4 + GP_REG_FIRST }, \
{ "a1", 5 + GP_REG_FIRST }, \
{ "a2", 6 + GP_REG_FIRST }, \
{ "a3", 7 + GP_REG_FIRST }, \
{ "t0", 8 + GP_REG_FIRST }, \
{ "t1", 9 + GP_REG_FIRST }, \
{ "t2", 10 + GP_REG_FIRST }, \
{ "t3", 11 + GP_REG_FIRST }, \
{ "t4", 12 + GP_REG_FIRST }, \
{ "t5", 13 + GP_REG_FIRST }, \
{ "t6", 14 + GP_REG_FIRST }, \
{ "t7", 15 + GP_REG_FIRST }, \
{ "s0", 16 + GP_REG_FIRST }, \
{ "s1", 17 + GP_REG_FIRST }, \
{ "s2", 18 + GP_REG_FIRST }, \
{ "s3", 19 + GP_REG_FIRST }, \
{ "s4", 20 + GP_REG_FIRST }, \
{ "s5", 21 + GP_REG_FIRST }, \
{ "s6", 22 + GP_REG_FIRST }, \
{ "s7", 23 + GP_REG_FIRST }, \
{ "t8", 24 + GP_REG_FIRST }, \
{ "t9", 25 + GP_REG_FIRST }, \
{ "k0", 26 + GP_REG_FIRST }, \
{ "k1", 27 + GP_REG_FIRST }, \
{ "gp", 28 + GP_REG_FIRST }, \
{ "sp", 29 + GP_REG_FIRST }, \
{ "fp", 30 + GP_REG_FIRST }, \
{ "ra", 31 + GP_REG_FIRST }, \
ALL_COP_ADDITIONAL_REGISTER_NAMES \
}
#define ALL_COP_ADDITIONAL_REGISTER_NAMES
#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
#define DBR_OUTPUT_SEQEND(STREAM) \
do \
{ \
if (set_nomacro > 0 && --set_nomacro == 0) \
fputs ("\t.set\tmacro\n", STREAM); \
\
if (set_noreorder > 0 && --set_noreorder == 0) \
fputs ("\t.set\treorder\n", STREAM); \
\
fputs ("\n", STREAM); \
} \
while (0)
#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
mips_output_filename (STREAM, NAME)
#define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
dbxout_begin_stabn_sline (LINE); \
dbxout_stab_value_internal_label ("LM", &COUNTER); \
} while (0)
#define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
#undef ASM_DECLARE_OBJECT_NAME
#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
mips_declare_object (STREAM, NAME, "", ":\n", 0)
#define GLOBAL_ASM_OP "\t.globl\t"
#define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
#ifndef ASM_OUTPUT_ALIGNED_LOCAL
#define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
#endif
#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
mips_output_external(STREAM,DECL,NAME)
#undef ASM_DECLARE_FUNCTION_NAME
#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
#ifndef FUNCTION_NAME_ALREADY_DECLARED
#define FUNCTION_NAME_ALREADY_DECLARED 0
#endif
#undef ASM_GENERATE_INTERNAL_LABEL
#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
fprintf (STREAM, "\t%s\t%sL%d\n", \
ptr_mode == DImode ? ".dword" : ".word", \
LOCAL_LABEL_PREFIX, \
VALUE)
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
do { \
if (TARGET_MIPS16) \
fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
else if (TARGET_GPWORD) \
fprintf (STREAM, "\t%s\t%sL%d\n", \
ptr_mode == DImode ? ".gpdword" : ".gpword", \
LOCAL_LABEL_PREFIX, VALUE); \
else \
fprintf (STREAM, "\t%s\t%sL%d\n", \
ptr_mode == DImode ? ".dword" : ".word", \
LOCAL_LABEL_PREFIX, VALUE); \
} while (0)
#define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
#define ASM_OUTPUT_ALIGN(STREAM,LOG) \
fprintf (STREAM, "\t.align\t%d\n", (LOG))
#undef ASM_OUTPUT_SKIP
#define ASM_OUTPUT_SKIP(STREAM,SIZE) \
fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
#undef ASM_OUTPUT_ASCII
#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
#undef ASM_OUTPUT_IDENT
#define ASM_OUTPUT_IDENT(FILE, STRING) \
{ \
const char *p = STRING; \
int size = strlen (p) + 1; \
readonly_data_section (); \
assemble_string (p, size); \
}
#ifndef MIPS_DEFAULT_GVALUE
#define MIPS_DEFAULT_GVALUE 8
#endif
#define TEXT_SECTION_ASM_OP "\t.text"
#define DATA_SECTION_ASM_OP "\t.data"
#define SDATA_SECTION_ASM_OP "\t.sdata"
#undef READONLY_DATA_SECTION_ASM_OP
#define READONLY_DATA_SECTION_ASM_OP "\t.rdata"
#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
do \
{ \
fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
TARGET_64BIT ? "dsubu" : "subu", \
reg_names[STACK_POINTER_REGNUM], \
reg_names[STACK_POINTER_REGNUM], \
TARGET_64BIT ? "sd" : "sw", \
reg_names[REGNO], \
reg_names[STACK_POINTER_REGNUM]); \
} \
while (0)
#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
do \
{ \
if (! set_noreorder) \
fprintf (STREAM, "\t.set\tnoreorder\n"); \
\
fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
TARGET_64BIT ? "ld" : "lw", \
reg_names[REGNO], \
reg_names[STACK_POINTER_REGNUM], \
TARGET_64BIT ? "daddu" : "addu", \
reg_names[STACK_POINTER_REGNUM], \
reg_names[STACK_POINTER_REGNUM]); \
\
if (! set_noreorder) \
fprintf (STREAM, "\t.set\treorder\n"); \
} \
while (0)
#ifndef ASM_COMMENT_START
#define ASM_COMMENT_START " #"
#endif
#undef SIZE_TYPE
#define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
#ifndef __mips16
#if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm (SECTION_OP "\n\
.set noreorder\n\
bal 1f\n\
nop\n\
1: .cpload $31\n\
.set reorder\n\
jal " USER_LABEL_PREFIX #FUNC "\n\
" TEXT_SECTION_ASM_OP);
#endif
#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
|| (defined _ABI64 && _MIPS_SIM == _ABI64)
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm (SECTION_OP "\n\
.set noreorder\n\
bal 1f\n\
nop\n\
1: .set reorder\n\
.cpsetup $31, $2, 1b\n\
jal " USER_LABEL_PREFIX #FUNC "\n\
" TEXT_SECTION_ASM_OP);
#endif
#endif