#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include <signal.h>
#include "rtl.h"
#include "regs.h"
#include "hard-reg-set.h"
#include "real.h"
#include "insn-config.h"
#include "conditions.h"
#include "insn-attr.h"
#include "recog.h"
#include "toplev.h"
#include "output.h"
#include "tree.h"
#include "function.h"
#include "expr.h"
#include "optabs.h"
#include "flags.h"
#include "reload.h"
#include "tm_p.h"
#include "ggc.h"
#include "gstab.h"
#include "hashtab.h"
#include "debug.h"
#include "target.h"
#include "target-def.h"
#include "integrate.h"
#include "langhooks.h"
#include "cfglayout.h"
#include "sched-int.h"
#include "tree-gimple.h"
#define UNSPEC_ADDRESS_P(X) \
(GET_CODE (X) == UNSPEC \
&& XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
&& XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
#define UNSPEC_ADDRESS(X) \
XVECEXP (X, 0, 0)
#define UNSPEC_ADDRESS_TYPE(X) \
((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
#define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
#define USEFUL_INSN_P(INSN) \
(INSN_P (INSN) \
&& GET_CODE (PATTERN (INSN)) != USE \
&& GET_CODE (PATTERN (INSN)) != CLOBBER \
&& GET_CODE (PATTERN (INSN)) != ADDR_VEC \
&& GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
#define SEQ_BEGIN(INSN) \
(INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
? XVECEXP (PATTERN (INSN), 0, 0) \
: (INSN))
#define SEQ_END(INSN) \
(INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
: (INSN))
#define FOR_EACH_SUBINSN(SUBINSN, INSN) \
for ((SUBINSN) = SEQ_BEGIN (INSN); \
(SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
(SUBINSN) = NEXT_INSN (SUBINSN))
enum mips_address_type {
ADDRESS_REG,
ADDRESS_LO_SUM,
ADDRESS_CONST_INT,
ADDRESS_SYMBOLIC
};
enum mips_function_type
{
MIPS_V2SF_FTYPE_V2SF,
MIPS_V2SF_FTYPE_V2SF_V2SF,
MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
MIPS_V2SF_FTYPE_SF_SF,
MIPS_INT_FTYPE_V2SF_V2SF,
MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
MIPS_INT_FTYPE_SF_SF,
MIPS_INT_FTYPE_DF_DF,
MIPS_SF_FTYPE_V2SF,
MIPS_SF_FTYPE_SF,
MIPS_SF_FTYPE_SF_SF,
MIPS_DF_FTYPE_DF,
MIPS_DF_FTYPE_DF_DF,
MIPS_MAX_FTYPE_MAX
};
enum mips_builtin_type
{
MIPS_BUILTIN_DIRECT,
MIPS_BUILTIN_MOVF,
MIPS_BUILTIN_MOVT,
MIPS_BUILTIN_CMP_ANY,
MIPS_BUILTIN_CMP_ALL,
MIPS_BUILTIN_CMP_UPPER,
MIPS_BUILTIN_CMP_LOWER,
MIPS_BUILTIN_CMP_SINGLE
};
#define MIPS_FP_CONDITIONS(MACRO) \
MACRO (f), \
MACRO (un), \
MACRO (eq), \
MACRO (ueq), \
MACRO (olt), \
MACRO (ult), \
MACRO (ole), \
MACRO (ule), \
MACRO (sf), \
MACRO (ngle), \
MACRO (seq), \
MACRO (ngl), \
MACRO (lt), \
MACRO (nge), \
MACRO (le), \
MACRO (ngt)
#define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
enum mips_fp_condition {
MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
};
#define STRINGIFY(X) #X
static const char *const mips_fp_conditions[] = {
MIPS_FP_CONDITIONS (STRINGIFY)
};
typedef void (*mips_save_restore_fn) (rtx, rtx);
struct mips16_constant;
struct mips_arg_info;
struct mips_address_info;
struct mips_integer_op;
struct mips_sim;
static enum mips_symbol_type mips_classify_symbol (rtx);
static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
static bool mips_classify_address (struct mips_address_info *, rtx,
enum machine_mode, int);
static int mips_symbol_insns (enum mips_symbol_type);
static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
static rtx mips_force_temporary (rtx, rtx);
static rtx mips_split_symbol (rtx, rtx);
static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
static unsigned int mips_build_lower (struct mips_integer_op *,
unsigned HOST_WIDE_INT);
static unsigned int mips_build_integer (struct mips_integer_op *,
unsigned HOST_WIDE_INT);
static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
static int m16_check_op (rtx, int, int, int);
static bool mips_rtx_costs (rtx, int, int, int *);
static int mips_address_cost (rtx);
static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
static void mips_load_call_address (rtx, rtx, int);
static bool mips_function_ok_for_sibcall (tree, tree);
static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
tree, int, struct mips_arg_info *);
static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
static void mips_set_architecture (const struct mips_cpu_info *);
static void mips_set_tune (const struct mips_cpu_info *);
static struct machine_function *mips_init_machine_status (void);
static void print_operand_reloc (FILE *, rtx, const char **);
#if TARGET_IRIX
static void irix_output_external_libcall (rtx);
#endif
static void mips_file_start (void);
static void mips_file_end (void);
static bool mips_rewrite_small_data_p (rtx);
static int mips_small_data_pattern_1 (rtx *, void *);
static int mips_rewrite_small_data_1 (rtx *, void *);
static bool mips_function_has_gp_insn (void);
static unsigned int mips_global_pointer (void);
static bool mips_save_reg_p (unsigned int);
static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
mips_save_restore_fn);
static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
static void mips_output_cplocal (void);
static void mips_emit_loadgp (void);
static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
static void mips_set_frame_expr (rtx);
static rtx mips_frame_set (rtx, rtx);
static void mips_save_reg (rtx, rtx);
static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
static void mips_restore_reg (rtx, rtx);
static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
HOST_WIDE_INT, tree);
static int symbolic_expression_p (rtx);
static void mips_select_rtx_section (enum machine_mode, rtx,
unsigned HOST_WIDE_INT);
static void mips_function_rodata_section (tree);
static bool mips_in_small_data_p (tree);
static int mips_fpr_return_fields (tree, tree *);
static bool mips_return_in_msb (tree);
static rtx mips_return_fpr_pair (enum machine_mode mode,
enum machine_mode mode1, HOST_WIDE_INT,
enum machine_mode mode2, HOST_WIDE_INT);
static rtx mips16_gp_pseudo_reg (void);
static void mips16_fp_args (FILE *, int, int);
static void build_mips16_function_stub (FILE *);
static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
static void dump_constants (struct mips16_constant *, rtx);
static int mips16_insn_length (rtx);
static int mips16_rewrite_pool_refs (rtx *, void *);
static void mips16_lay_out_constants (void);
static void mips_sim_reset (struct mips_sim *);
static void mips_sim_init (struct mips_sim *, state_t);
static void mips_sim_next_cycle (struct mips_sim *);
static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
static int mips_sim_wait_regs_2 (rtx *, void *);
static void mips_sim_wait_regs_1 (rtx *, void *);
static void mips_sim_wait_regs (struct mips_sim *, rtx);
static void mips_sim_wait_units (struct mips_sim *, rtx);
static void mips_sim_wait_insn (struct mips_sim *, rtx);
static void mips_sim_record_set (rtx, rtx, void *);
static void mips_sim_issue_insn (struct mips_sim *, rtx);
static void mips_sim_issue_nop (struct mips_sim *);
static void mips_sim_finish_insn (struct mips_sim *, rtx);
static void vr4130_avoid_branch_rt_conflict (rtx);
static void vr4130_align_insns (void);
static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
static void mips_avoid_hazards (void);
static void mips_reorg (void);
static bool mips_strict_matching_cpu_name_p (const char *, const char *);
static bool mips_matching_cpu_name_p (const char *, const char *);
static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
static bool mips_return_in_memory (tree, tree);
static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
static void mips_macc_chains_record (rtx);
static void mips_macc_chains_reorder (rtx *, int);
static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
static bool vr4130_true_reg_dependence_p (rtx);
static bool vr4130_swap_insns_p (rtx, rtx);
static void vr4130_reorder (rtx *, int);
static void mips_promote_ready (rtx *, int, int);
static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
static int mips_variable_issue (FILE *, int, rtx, int);
static int mips_adjust_cost (rtx, rtx, rtx, int);
static int mips_issue_rate (void);
static int mips_multipass_dfa_lookahead (void);
static void mips_init_libfuncs (void);
static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
tree, int *, int);
static tree mips_build_builtin_va_list (void);
static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
tree, bool);
static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
tree, bool);
static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
tree, bool);
static bool mips_valid_pointer_mode (enum machine_mode);
static bool mips_scalar_mode_supported_p (enum machine_mode);
static bool mips_vector_mode_supported_p (enum machine_mode);
static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
static void mips_init_builtins (void);
static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree);
static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
enum insn_code, enum mips_fp_condition,
rtx, tree);
static rtx mips_expand_builtin_compare (enum mips_builtin_type,
enum insn_code, enum mips_fp_condition,
rtx, tree);
struct mips_frame_info GTY(())
{
HOST_WIDE_INT total_size;
HOST_WIDE_INT var_size;
HOST_WIDE_INT args_size;
HOST_WIDE_INT cprestore_size;
HOST_WIDE_INT gp_reg_size;
HOST_WIDE_INT fp_reg_size;
unsigned int mask;
unsigned int fmask;
HOST_WIDE_INT gp_save_offset;
HOST_WIDE_INT fp_save_offset;
HOST_WIDE_INT gp_sp_offset;
HOST_WIDE_INT fp_sp_offset;
bool initialized;
int num_gp;
int num_fp;
};
struct machine_function GTY(()) {
rtx mips16_gp_pseudo_rtx;
struct mips_frame_info frame;
unsigned int global_pointer;
bool ignore_hazard_length_p;
bool all_noreorder_p;
bool has_gp_insn_p;
};
struct mips_arg_info
{
bool fpr_p;
unsigned int reg_words;
unsigned int reg_offset;
unsigned int stack_words;
unsigned int stack_offset;
};
struct mips_address_info
{
enum mips_address_type type;
rtx reg;
rtx offset;
enum mips_symbol_type symbol_type;
};
struct mips_integer_op {
enum rtx_code code;
unsigned HOST_WIDE_INT value;
};
#define MIPS_MAX_INTEGER_OPS 7
int mips_section_threshold = -1;
int num_source_filenames = 0;
int sdb_label_count = 0;
int sym_lineno = 0;
struct extern_list GTY (())
{
struct extern_list *next;
const char *name;
int size;
};
static GTY (()) struct extern_list *extern_head = 0;
const char *current_function_file = "";
int set_noreorder;
int set_noat;
int set_nomacro;
int set_volatile;
int mips_branch_likely;
rtx cmp_operands[2];
enum processor_type mips_arch;
const struct mips_cpu_info *mips_arch_info;
enum processor_type mips_tune;
const struct mips_cpu_info *mips_tune_info;
int mips_isa;
int mips_abi;
const char *mips_arch_string;
const char *mips_tune_string;
const char *mips_isa_string;
const char *mips_abi_string;
int mips16_hard_float;
const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
const char *mips_fix_vr4130_string;
int mips_split_addresses;
static enum machine_mode gpr_mode;
char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
char mips_print_operand_punct[256];
int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
static int mips_flag_delayed_branch;
static GTY (()) int mips_output_filename_first_time = 1;
static bool mips_split_p[NUM_SYMBOL_TYPES];
static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
const enum reg_class mips_regno_to_class[] =
{
LEA_REGS, LEA_REGS, M16_NA_REGS, M16_NA_REGS,
M16_REGS, M16_REGS, M16_REGS, M16_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
HI_REG, LO_REG, NO_REGS, ST_REGS,
ST_REGS, ST_REGS, ST_REGS, ST_REGS,
ST_REGS, ST_REGS, ST_REGS, NO_REGS,
NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
};
enum reg_class mips_char_to_class[256];
const struct mips_cpu_info mips_cpu_info_table[] = {
{ "mips1", PROCESSOR_R3000, 1 },
{ "mips2", PROCESSOR_R6000, 2 },
{ "mips3", PROCESSOR_R4000, 3 },
{ "mips4", PROCESSOR_R8000, 4 },
{ "mips32", PROCESSOR_4KC, 32 },
{ "mips32r2", PROCESSOR_M4K, 33 },
{ "mips64", PROCESSOR_5KC, 64 },
{ "r3000", PROCESSOR_R3000, 1 },
{ "r2000", PROCESSOR_R3000, 1 },
{ "r3900", PROCESSOR_R3900, 1 },
{ "r6000", PROCESSOR_R6000, 2 },
{ "r4000", PROCESSOR_R4000, 3 },
{ "vr4100", PROCESSOR_R4100, 3 },
{ "vr4111", PROCESSOR_R4111, 3 },
{ "vr4120", PROCESSOR_R4120, 3 },
{ "vr4130", PROCESSOR_R4130, 3 },
{ "vr4300", PROCESSOR_R4300, 3 },
{ "r4400", PROCESSOR_R4000, 3 },
{ "r4600", PROCESSOR_R4600, 3 },
{ "orion", PROCESSOR_R4600, 3 },
{ "r4650", PROCESSOR_R4650, 3 },
{ "r8000", PROCESSOR_R8000, 4 },
{ "vr5000", PROCESSOR_R5000, 4 },
{ "vr5400", PROCESSOR_R5400, 4 },
{ "vr5500", PROCESSOR_R5500, 4 },
{ "rm7000", PROCESSOR_R7000, 4 },
{ "rm9000", PROCESSOR_R9000, 4 },
{ "4kc", PROCESSOR_4KC, 32 },
{ "4kp", PROCESSOR_4KC, 32 },
{ "m4k", PROCESSOR_M4K, 33 },
{ "5kc", PROCESSOR_5KC, 64 },
{ "20kc", PROCESSOR_20KC, 64 },
{ "sb1", PROCESSOR_SB1, 64 },
{ "sr71000", PROCESSOR_SR71000, 64 },
{ 0, 0, 0 }
};
#ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
#define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
#endif
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
#undef TARGET_ASM_ALIGNED_SI_OP
#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
#undef TARGET_ASM_ALIGNED_DI_OP
#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
#undef TARGET_ASM_FUNCTION_PROLOGUE
#define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
#undef TARGET_ASM_FUNCTION_EPILOGUE
#define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
#undef TARGET_ASM_SELECT_RTX_SECTION
#define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
#undef TARGET_ASM_FUNCTION_RODATA_SECTION
#define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
#undef TARGET_SCHED_REORDER
#define TARGET_SCHED_REORDER mips_sched_reorder
#undef TARGET_SCHED_VARIABLE_ISSUE
#define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST mips_adjust_cost
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
mips_multipass_dfa_lookahead
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
#undef TARGET_VALID_POINTER_MODE
#define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS mips_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST mips_address_cost
#undef TARGET_IN_SMALL_DATA_P
#define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
#undef TARGET_ASM_FILE_START
#undef TARGET_ASM_FILE_END
#define TARGET_ASM_FILE_START mips_file_start
#define TARGET_ASM_FILE_END mips_file_end
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS mips_init_libfuncs
#undef TARGET_BUILD_BUILTIN_VA_LIST
#define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
#undef TARGET_GIMPLIFY_VA_ARG_EXPR
#define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
#undef TARGET_PROMOTE_FUNCTION_ARGS
#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
#undef TARGET_PROMOTE_FUNCTION_RETURN
#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
#undef TARGET_PROMOTE_PROTOTYPES
#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
#undef TARGET_RETURN_IN_MEMORY
#define TARGET_RETURN_IN_MEMORY mips_return_in_memory
#undef TARGET_RETURN_IN_MSB
#define TARGET_RETURN_IN_MSB mips_return_in_msb
#undef TARGET_ASM_OUTPUT_MI_THUNK
#define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
#undef TARGET_STRICT_ARGUMENT_NAMING
#define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
#undef TARGET_MUST_PASS_IN_STACK
#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
#undef TARGET_PASS_BY_REFERENCE
#define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
#undef TARGET_CALLEE_COPIES
#define TARGET_CALLEE_COPIES mips_callee_copies
#undef TARGET_ARG_PARTIAL_BYTES
#define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
#undef TARGET_VECTOR_MODE_SUPPORTED_P
#define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
#undef TARGET_SCALAR_MODE_SUPPORTED_P
#define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS mips_init_builtins
#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN mips_expand_builtin
struct gcc_target targetm = TARGET_INITIALIZER;
static enum mips_symbol_type
mips_classify_symbol (rtx x)
{
if (GET_CODE (x) == LABEL_REF)
{
if (TARGET_MIPS16)
return SYMBOL_CONSTANT_POOL;
if (TARGET_ABICALLS)
return SYMBOL_GOT_LOCAL;
return SYMBOL_GENERAL;
}
gcc_assert (GET_CODE (x) == SYMBOL_REF);
if (CONSTANT_POOL_ADDRESS_P (x))
{
if (TARGET_MIPS16)
return SYMBOL_CONSTANT_POOL;
if (TARGET_ABICALLS)
return SYMBOL_GOT_LOCAL;
if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
return SYMBOL_SMALL_DATA;
return SYMBOL_GENERAL;
}
if (SYMBOL_REF_SMALL_P (x))
return SYMBOL_SMALL_DATA;
if (TARGET_ABICALLS)
{
if (SYMBOL_REF_DECL (x) == 0)
return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
return SYMBOL_GOT_GLOBAL;
return SYMBOL_GOT_LOCAL;
}
return SYMBOL_GENERAL;
}
static void
mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
{
*offset = 0;
if (GET_CODE (x) == CONST)
x = XEXP (x, 0);
if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
{
*offset += INTVAL (XEXP (x, 1));
x = XEXP (x, 0);
}
*base = x;
}
static bool
mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
{
if (GET_CODE (symbol) != SYMBOL_REF)
return false;
if (CONSTANT_POOL_ADDRESS_P (symbol)
&& offset >= 0
&& offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
return true;
if (SYMBOL_REF_DECL (symbol) != 0
&& offset >= 0
&& offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
return true;
return false;
}
bool
mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
{
HOST_WIDE_INT offset;
mips_split_const (x, &x, &offset);
if (UNSPEC_ADDRESS_P (x))
*symbol_type = UNSPEC_ADDRESS_TYPE (x);
else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
*symbol_type = mips_classify_symbol (x);
else
return false;
if (offset == 0)
return true;
switch (*symbol_type)
{
case SYMBOL_GENERAL:
case SYMBOL_64_HIGH:
case SYMBOL_64_MID:
case SYMBOL_64_LOW:
if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
return mips_offset_within_object_p (x, offset);
return true;
case SYMBOL_CONSTANT_POOL:
if (GET_CODE (x) == LABEL_REF)
return true;
case SYMBOL_SMALL_DATA:
return mips_offset_within_object_p (x, offset);
case SYMBOL_GOT_LOCAL:
case SYMBOL_GOTOFF_PAGE:
return SMALL_OPERAND (offset);
case SYMBOL_GOT_GLOBAL:
case SYMBOL_GOTOFF_GLOBAL:
case SYMBOL_GOTOFF_CALL:
case SYMBOL_GOTOFF_LOADGP:
return false;
}
gcc_unreachable ();
}
bool
mips_atomic_symbolic_constant_p (rtx x)
{
enum mips_symbol_type type;
return mips_symbolic_constant_p (x, &type) && !mips_split_p[type];
}
int
mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
{
if (regno >= FIRST_PSEUDO_REGISTER)
{
if (!strict)
return true;
regno = reg_renumber[regno];
}
if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
return true;
if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
}
static bool
mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
{
if (!strict && GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
return (REG_P (x)
&& mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
}
static bool
mips_symbolic_address_p (enum mips_symbol_type symbol_type,
enum machine_mode mode)
{
switch (symbol_type)
{
case SYMBOL_GENERAL:
return !TARGET_MIPS16;
case SYMBOL_SMALL_DATA:
return true;
case SYMBOL_CONSTANT_POOL:
return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
case SYMBOL_GOT_LOCAL:
return true;
case SYMBOL_GOT_GLOBAL:
return false;
case SYMBOL_GOTOFF_PAGE:
case SYMBOL_GOTOFF_GLOBAL:
case SYMBOL_GOTOFF_CALL:
case SYMBOL_GOTOFF_LOADGP:
case SYMBOL_64_HIGH:
case SYMBOL_64_MID:
case SYMBOL_64_LOW:
return true;
}
gcc_unreachable ();
}
static bool
mips_classify_address (struct mips_address_info *info, rtx x,
enum machine_mode mode, int strict)
{
switch (GET_CODE (x))
{
case REG:
case SUBREG:
info->type = ADDRESS_REG;
info->reg = x;
info->offset = const0_rtx;
return mips_valid_base_register_p (info->reg, mode, strict);
case PLUS:
info->type = ADDRESS_REG;
info->reg = XEXP (x, 0);
info->offset = XEXP (x, 1);
return (mips_valid_base_register_p (info->reg, mode, strict)
&& const_arith_operand (info->offset, VOIDmode));
case LO_SUM:
info->type = ADDRESS_LO_SUM;
info->reg = XEXP (x, 0);
info->offset = XEXP (x, 1);
return (mips_valid_base_register_p (info->reg, mode, strict)
&& mips_symbolic_constant_p (info->offset, &info->symbol_type)
&& mips_symbolic_address_p (info->symbol_type, mode)
&& mips_lo_relocs[info->symbol_type] != 0);
case CONST_INT:
info->type = ADDRESS_CONST_INT;
return !TARGET_MIPS16 && SMALL_INT (x);
case CONST:
case LABEL_REF:
case SYMBOL_REF:
info->type = ADDRESS_SYMBOLIC;
return (mips_symbolic_constant_p (x, &info->symbol_type)
&& mips_symbolic_address_p (info->symbol_type, mode)
&& !mips_split_p[info->symbol_type]);
default:
return false;
}
}
static int
mips_symbol_insns (enum mips_symbol_type type)
{
switch (type)
{
case SYMBOL_GENERAL:
if (TARGET_MIPS16)
return 0;
return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
case SYMBOL_SMALL_DATA:
return 1;
case SYMBOL_CONSTANT_POOL:
return 2;
case SYMBOL_GOT_LOCAL:
case SYMBOL_GOT_GLOBAL:
return 3;
case SYMBOL_GOTOFF_PAGE:
case SYMBOL_GOTOFF_GLOBAL:
case SYMBOL_GOTOFF_CALL:
case SYMBOL_GOTOFF_LOADGP:
case SYMBOL_64_HIGH:
case SYMBOL_64_MID:
case SYMBOL_64_LOW:
return mips_split_p[type] ? 2 : 1;
}
gcc_unreachable ();
}
bool
mips_stack_address_p (rtx x, enum machine_mode mode)
{
struct mips_address_info addr;
return (mips_classify_address (&addr, x, mode, false)
&& addr.type == ADDRESS_REG
&& addr.reg == stack_pointer_rtx);
}
static bool
mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
{
if (TARGET_MIPS16
&& GET_CODE (offset) == CONST_INT
&& INTVAL (offset) >= 0
&& (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
{
if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
}
return false;
}
int
mips_address_insns (rtx x, enum machine_mode mode)
{
struct mips_address_info addr;
int factor;
if (mode == BLKmode)
factor = 1;
else
factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
if (mips_classify_address (&addr, x, mode, false))
switch (addr.type)
{
case ADDRESS_REG:
if (TARGET_MIPS16
&& !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
return factor * 2;
return factor;
case ADDRESS_LO_SUM:
return (TARGET_MIPS16 ? factor * 2 : factor);
case ADDRESS_CONST_INT:
return factor;
case ADDRESS_SYMBOLIC:
return factor * mips_symbol_insns (addr.symbol_type);
}
return 0;
}
int
mips_const_insns (rtx x)
{
struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
enum mips_symbol_type symbol_type;
HOST_WIDE_INT offset;
switch (GET_CODE (x))
{
case HIGH:
if (TARGET_MIPS16
|| !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
|| !mips_split_p[symbol_type])
return 0;
return 1;
case CONST_INT:
if (TARGET_MIPS16)
return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
: SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
: INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
: SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
: 0);
return mips_build_integer (codes, INTVAL (x));
case CONST_DOUBLE:
case CONST_VECTOR:
return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
case CONST:
if (CONST_GP_P (x))
return 1;
if (mips_symbolic_constant_p (x, &symbol_type))
return mips_symbol_insns (symbol_type);
mips_split_const (x, &x, &offset);
if (offset != 0)
{
int n = mips_const_insns (x);
if (n != 0)
{
if (SMALL_OPERAND (offset))
return n + 1;
else
return n + 1 + mips_build_integer (codes, offset);
}
}
return 0;
case SYMBOL_REF:
case LABEL_REF:
return mips_symbol_insns (mips_classify_symbol (x));
default:
return 0;
}
}
int
mips_fetch_insns (rtx x)
{
gcc_assert (MEM_P (x));
return mips_address_insns (XEXP (x, 0), GET_MODE (x));
}
int
mips_idiv_insns (void)
{
int count;
count = 1;
if (TARGET_CHECK_ZERO_DIV)
{
if (GENERATE_DIVIDE_TRAPS)
count++;
else
count += 2;
}
if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
count++;
return count;
}
bool
mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
{
struct mips_address_info addr;
return mips_classify_address (&addr, x, mode, strict);
}
static rtx
mips_force_temporary (rtx dest, rtx value)
{
if (!no_new_pseudos)
return force_reg (Pmode, value);
else
{
emit_move_insn (copy_rtx (dest), value);
return dest;
}
}
static rtx
mips_split_symbol (rtx temp, rtx addr)
{
rtx high;
if (TARGET_MIPS16)
high = mips16_gp_pseudo_reg ();
else
high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
return gen_rtx_LO_SUM (Pmode, high, addr);
}
rtx
mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
{
rtx base;
HOST_WIDE_INT offset;
mips_split_const (address, &base, &offset);
base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
UNSPEC_ADDRESS_FIRST + symbol_type);
return plus_constant (gen_rtx_CONST (Pmode, base), offset);
}
static rtx
mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
enum mips_symbol_type symbol_type)
{
if (mips_split_p[symbol_type])
{
addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
addr = mips_force_temporary (temp, addr);
return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
}
return base;
}
static rtx
mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
{
if (!SMALL_OPERAND (offset))
{
rtx high;
if (TARGET_MIPS16)
{
high = GEN_INT (offset);
offset = 0;
}
else
{
high = GEN_INT (CONST_HIGH_PART (offset));
offset = CONST_LOW_PART (offset);
}
high = mips_force_temporary (temp, high);
reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
}
return plus_constant (reg, offset);
}
bool
mips_legitimize_address (rtx *xloc, enum machine_mode mode)
{
enum mips_symbol_type symbol_type;
if (mips_symbolic_constant_p (*xloc, &symbol_type)
&& mips_symbolic_address_p (symbol_type, mode)
&& mips_split_p[symbol_type])
{
*xloc = mips_split_symbol (0, *xloc);
return true;
}
if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
{
rtx reg;
reg = XEXP (*xloc, 0);
if (!mips_valid_base_register_p (reg, mode, 0))
reg = copy_to_mode_reg (Pmode, reg);
*xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
return true;
}
return false;
}
static unsigned int
mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
{
unsigned int i, shift;
shift = 0;
while ((value & 1) == 0)
value /= 2, shift++;
i = mips_build_integer (codes, value);
codes[i].code = ASHIFT;
codes[i].value = shift;
return i + 1;
}
static unsigned int
mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
{
unsigned HOST_WIDE_INT high;
unsigned int i;
high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
{
i = mips_build_integer (codes, CONST_HIGH_PART (value));
codes[i].code = PLUS;
codes[i].value = CONST_LOW_PART (value);
}
else
{
i = mips_build_integer (codes, high);
codes[i].code = IOR;
codes[i].value = value & 0xffff;
}
return i + 1;
}
static unsigned int
mips_build_integer (struct mips_integer_op *codes,
unsigned HOST_WIDE_INT value)
{
if (SMALL_OPERAND (value)
|| SMALL_OPERAND_UNSIGNED (value)
|| LUI_OPERAND (value))
{
codes[0].code = UNKNOWN;
codes[0].value = value;
return 1;
}
else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
{
return mips_build_lower (codes, value);
}
else if ((value & 0xffff) == 0)
{
return mips_build_shift (codes, value);
}
else
{
struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
unsigned int cost, alt_cost;
cost = mips_build_shift (codes, value);
alt_cost = mips_build_lower (alt_codes, value);
if (alt_cost < cost)
{
memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
cost = alt_cost;
}
return cost;
}
}
static void
mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
{
struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
enum machine_mode mode;
unsigned int i, cost;
rtx x;
mode = GET_MODE (dest);
cost = mips_build_integer (codes, value);
x = GEN_INT (codes[0].value);
for (i = 1; i < cost; i++)
{
if (no_new_pseudos)
emit_move_insn (dest, x), x = dest;
else
x = force_reg (mode, x);
x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
}
emit_insn (gen_rtx_SET (VOIDmode, dest, x));
}
static void
mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
{
rtx base;
HOST_WIDE_INT offset;
enum mips_symbol_type symbol_type;
if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
{
mips_move_integer (dest, INTVAL (src));
return;
}
if (!TARGET_MIPS16
&& mips_symbolic_constant_p (src, &symbol_type)
&& mips_split_p[symbol_type])
{
emit_move_insn (dest, mips_split_symbol (dest, src));
return;
}
mips_split_const (src, &base, &offset);
if (!TARGET_MIPS16
&& offset != 0
&& (!no_new_pseudos || SMALL_OPERAND (offset)))
{
base = mips_force_temporary (dest, base);
emit_move_insn (dest, mips_add_offset (0, base, offset));
return;
}
src = force_const_mem (mode, src);
if (!memory_operand (src, VOIDmode))
src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
emit_move_insn (dest, src);
}
bool
mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
{
if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
{
emit_move_insn (dest, force_reg (mode, src));
return true;
}
if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
&& REG_P (src) && MD_REG_P (REGNO (src))
&& REG_P (dest) && GP_REG_P (REGNO (dest)))
{
int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
if (GET_MODE_SIZE (mode) <= 4)
emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
gen_rtx_REG (SImode, REGNO (src)),
gen_rtx_REG (SImode, other_regno)));
else
emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
gen_rtx_REG (DImode, REGNO (src)),
gen_rtx_REG (DImode, other_regno)));
return true;
}
if (CONSTANT_P (src) && !move_operand (src, mode))
{
mips_legitimize_const_move (mode, dest, src);
set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
return true;
}
return false;
}
static int
m16_check_op (rtx op, int low, int high, int mask)
{
return (GET_CODE (op) == CONST_INT
&& INTVAL (op) >= low
&& INTVAL (op) <= high
&& (INTVAL (op) & mask) == 0);
}
int
m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, 0x1, 0x8, 0);
}
int
m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, - 0x8, 0x7, 0);
}
int
m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, - 0x7, 0x8, 0);
}
int
m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, - 0x10, 0xf, 0);
}
int
m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, - 0xf, 0x10, 0);
}
int
m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
}
int
m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
}
int
m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, - 0x80, 0x7f, 0);
}
int
m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, - 0x7f, 0x80, 0);
}
int
m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, 0x0, 0xff, 0);
}
int
m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, - 0xff, 0x0, 0);
}
int
m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, - 0x1, 0xfe, 0);
}
int
m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, 0x0, 0xff << 2, 3);
}
int
m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
}
int
m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
}
int
m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
{
return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
}
static bool
mips_rtx_costs (rtx x, int code, int outer_code, int *total)
{
enum machine_mode mode = GET_MODE (x);
switch (code)
{
case CONST_INT:
if (!TARGET_MIPS16)
{
*total = 0;
return true;
}
if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
|| (outer_code) == LSHIFTRT)
{
if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
*total = 0;
else
*total = COSTS_N_INSNS (1);
return true;
}
if ((outer_code) == XOR
&& INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
{
*total = 0;
return true;
}
if (((outer_code) == LT || (outer_code) == LE
|| (outer_code) == GE || (outer_code) == GT
|| (outer_code) == LTU || (outer_code) == LEU
|| (outer_code) == GEU || (outer_code) == GTU)
&& INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
{
*total = 0;
return true;
}
if (((outer_code) == EQ || (outer_code) == NE)
&& INTVAL (x) == 0)
{
*total = 0;
return true;
}
if (outer_code == SET
&& INTVAL (x) >= 0
&& INTVAL (x) < 256)
{
*total = 0;
return true;
}
case CONST:
case SYMBOL_REF:
case LABEL_REF:
case CONST_DOUBLE:
if (LEGITIMATE_CONSTANT_P (x))
{
*total = COSTS_N_INSNS (1);
return true;
}
else
{
*total = CONSTANT_POOL_COST;
return true;
}
case MEM:
{
int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
if (n > 0)
{
*total = COSTS_N_INSNS (1 + n);
return true;
}
return false;
}
case FFS:
*total = COSTS_N_INSNS (6);
return true;
case NOT:
*total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
return true;
case AND:
case IOR:
case XOR:
if (mode == DImode && !TARGET_64BIT)
{
*total = COSTS_N_INSNS (2);
return true;
}
return false;
case ASHIFT:
case ASHIFTRT:
case LSHIFTRT:
if (mode == DImode && !TARGET_64BIT)
{
*total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
? 4 : 12);
return true;
}
return false;
case ABS:
if (mode == SFmode || mode == DFmode)
*total = COSTS_N_INSNS (1);
else
*total = COSTS_N_INSNS (4);
return true;
case LO_SUM:
*total = COSTS_N_INSNS (1);
return true;
case PLUS:
case MINUS:
if (mode == SFmode || mode == DFmode)
{
if (TUNE_MIPS3000 || TUNE_MIPS3900)
*total = COSTS_N_INSNS (2);
else if (TUNE_MIPS6000)
*total = COSTS_N_INSNS (3);
else if (TUNE_SB1)
*total = COSTS_N_INSNS (4);
else
*total = COSTS_N_INSNS (6);
return true;
}
if (mode == DImode && !TARGET_64BIT)
{
*total = COSTS_N_INSNS (4);
return true;
}
return false;
case NEG:
if (mode == DImode && !TARGET_64BIT)
{
*total = 4;
return true;
}
return false;
case MULT:
if (mode == SFmode)
{
if (TUNE_MIPS3000
|| TUNE_MIPS3900
|| TUNE_MIPS5000
|| TUNE_SB1)
*total = COSTS_N_INSNS (4);
else if (TUNE_MIPS6000
|| TUNE_MIPS5400
|| TUNE_MIPS5500)
*total = COSTS_N_INSNS (5);
else
*total = COSTS_N_INSNS (7);
return true;
}
if (mode == DFmode)
{
if (TUNE_SB1)
*total = COSTS_N_INSNS (4);
else if (TUNE_MIPS3000
|| TUNE_MIPS3900
|| TUNE_MIPS5000)
*total = COSTS_N_INSNS (5);
else if (TUNE_MIPS6000
|| TUNE_MIPS5400
|| TUNE_MIPS5500)
*total = COSTS_N_INSNS (6);
else
*total = COSTS_N_INSNS (8);
return true;
}
if (TUNE_MIPS3000)
*total = COSTS_N_INSNS (12);
else if (TUNE_MIPS3900)
*total = COSTS_N_INSNS (2);
else if (TUNE_MIPS4130)
*total = COSTS_N_INSNS (mode == DImode ? 6 : 4);
else if (TUNE_MIPS5400 || TUNE_SB1)
*total = COSTS_N_INSNS (mode == DImode ? 4 : 3);
else if (TUNE_MIPS5500 || TUNE_MIPS7000)
*total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
else if (TUNE_MIPS9000)
*total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
else if (TUNE_MIPS6000)
*total = COSTS_N_INSNS (17);
else if (TUNE_MIPS5000)
*total = COSTS_N_INSNS (5);
else
*total = COSTS_N_INSNS (10);
return true;
case DIV:
case MOD:
if (mode == SFmode)
{
if (TUNE_MIPS3000
|| TUNE_MIPS3900)
*total = COSTS_N_INSNS (12);
else if (TUNE_MIPS6000)
*total = COSTS_N_INSNS (15);
else if (TUNE_SB1)
*total = COSTS_N_INSNS (24);
else if (TUNE_MIPS5400 || TUNE_MIPS5500)
*total = COSTS_N_INSNS (30);
else
*total = COSTS_N_INSNS (23);
return true;
}
if (mode == DFmode)
{
if (TUNE_MIPS3000
|| TUNE_MIPS3900)
*total = COSTS_N_INSNS (19);
else if (TUNE_MIPS5400 || TUNE_MIPS5500)
*total = COSTS_N_INSNS (59);
else if (TUNE_MIPS6000)
*total = COSTS_N_INSNS (16);
else if (TUNE_SB1)
*total = COSTS_N_INSNS (32);
else
*total = COSTS_N_INSNS (36);
return true;
}
case UDIV:
case UMOD:
if (TUNE_MIPS3000
|| TUNE_MIPS3900)
*total = COSTS_N_INSNS (35);
else if (TUNE_MIPS6000)
*total = COSTS_N_INSNS (38);
else if (TUNE_MIPS5000)
*total = COSTS_N_INSNS (36);
else if (TUNE_SB1)
*total = COSTS_N_INSNS ((mode == SImode) ? 36 : 68);
else if (TUNE_MIPS5400 || TUNE_MIPS5500)
*total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
else
*total = COSTS_N_INSNS (69);
return true;
case SIGN_EXTEND:
if (TARGET_64BIT && mode == DImode
&& GET_MODE (XEXP (x, 0)) == SImode)
*total = COSTS_N_INSNS (1);
else
*total = COSTS_N_INSNS (2);
return true;
case ZERO_EXTEND:
if (TARGET_64BIT && mode == DImode
&& GET_MODE (XEXP (x, 0)) == SImode)
*total = COSTS_N_INSNS (2);
else
*total = COSTS_N_INSNS (1);
return true;
default:
return false;
}
}
static int
mips_address_cost (rtx addr)
{
return mips_address_insns (addr, SImode);
}
rtx
mips_subword (rtx op, int high_p)
{
unsigned int byte;
enum machine_mode mode;
mode = GET_MODE (op);
if (mode == VOIDmode)
mode = DImode;
if (TARGET_BIG_ENDIAN ? !high_p : high_p)
byte = UNITS_PER_WORD;
else
byte = 0;
if (REG_P (op))
{
if (FP_REG_P (REGNO (op)))
return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
if (REGNO (op) == HI_REGNUM)
return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
}
if (MEM_P (op))
return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
return simplify_gen_subreg (word_mode, op, mode, byte);
}
bool
mips_split_64bit_move_p (rtx dest, rtx src)
{
if (TARGET_64BIT)
return false;
if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
return false;
if (mips_isa > 1)
{
if (FP_REG_RTX_P (dest) && MEM_P (src))
return false;
if (FP_REG_RTX_P (src) && MEM_P (dest))
return false;
}
return true;
}
void
mips_split_64bit_move (rtx dest, rtx src)
{
if (FP_REG_RTX_P (dest))
{
emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
copy_rtx (dest)));
}
else if (FP_REG_RTX_P (src))
{
emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
}
else
{
rtx low_dest;
low_dest = mips_subword (dest, 0);
if (REG_P (low_dest)
&& reg_overlap_mentioned_p (low_dest, src))
{
emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
emit_move_insn (low_dest, mips_subword (src, 0));
}
else
{
emit_move_insn (low_dest, mips_subword (src, 0));
emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
}
}
}
const char *
mips_output_move (rtx dest, rtx src)
{
enum rtx_code dest_code, src_code;
bool dbl_p;
dest_code = GET_CODE (dest);
src_code = GET_CODE (src);
dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
if (dbl_p && mips_split_64bit_move_p (dest, src))
return "#";
if ((src_code == REG && GP_REG_P (REGNO (src)))
|| (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
{
if (dest_code == REG)
{
if (GP_REG_P (REGNO (dest)))
return "move\t%0,%z1";
if (MD_REG_P (REGNO (dest)))
return "mt%0\t%z1";
if (FP_REG_P (REGNO (dest)))
return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
if (ALL_COP_REG_P (REGNO (dest)))
{
static char retval[] = "dmtc_\t%z1,%0";
retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
return (dbl_p ? retval : retval + 1);
}
}
if (dest_code == MEM)
return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
}
if (dest_code == REG && GP_REG_P (REGNO (dest)))
{
if (src_code == REG)
{
if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
if (FP_REG_P (REGNO (src)))
return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
if (ALL_COP_REG_P (REGNO (src)))
{
static char retval[] = "dmfc_\t%0,%1";
retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
return (dbl_p ? retval : retval + 1);
}
}
if (src_code == MEM)
return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
if (src_code == CONST_INT)
{
if (!TARGET_MIPS16)
return "li\t%0,%1\t\t\t# %X1";
if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
return "li\t%0,%1";
if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
return "#";
}
if (src_code == HIGH)
return "lui\t%0,%h1";
if (CONST_GP_P (src))
return "move\t%0,%1";
if (symbolic_operand (src, VOIDmode))
return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
}
if (src_code == REG && FP_REG_P (REGNO (src)))
{
if (dest_code == REG && FP_REG_P (REGNO (dest)))
{
if (GET_MODE (dest) == V2SFmode)
return "mov.ps\t%0,%1";
else
return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
}
if (dest_code == MEM)
return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
}
if (dest_code == REG && FP_REG_P (REGNO (dest)))
{
if (src_code == MEM)
return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
}
if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
{
static char retval[] = "l_c_\t%0,%1";
retval[1] = (dbl_p ? 'd' : 'w');
retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
return retval;
}
if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
{
static char retval[] = "s_c_\t%1,%0";
retval[1] = (dbl_p ? 'd' : 'w');
retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
return retval;
}
gcc_unreachable ();
}
void
mips_restore_gp (void)
{
rtx address, slot;
gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
address = mips_add_offset (pic_offset_table_rtx,
frame_pointer_needed
? hard_frame_pointer_rtx
: stack_pointer_rtx,
current_function_outgoing_args_size);
slot = gen_rtx_MEM (Pmode, address);
emit_move_insn (pic_offset_table_rtx, slot);
if (!TARGET_EXPLICIT_RELOCS)
emit_insn (gen_blockage ());
}
static void
mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
{
emit_insn (gen_rtx_SET (VOIDmode, target,
gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
}
static bool
mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
{
switch (code)
{
case GT:
case GTU:
return reg_or_0_operand (cmp1, VOIDmode);
case GE:
case GEU:
return !TARGET_MIPS16 && cmp1 == const1_rtx;
case LT:
case LTU:
return arith_operand (cmp1, VOIDmode);
case LE:
return sle_operand (cmp1, VOIDmode);
case LEU:
return sleu_operand (cmp1, VOIDmode);
default:
gcc_unreachable ();
}
}
static void
mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
rtx target, rtx cmp0, rtx cmp1)
{
if (mips_relational_operand_ok_p (code, cmp1))
mips_emit_binary (code, target, cmp0, cmp1);
else
{
enum rtx_code inv_code = reverse_condition (code);
if (!mips_relational_operand_ok_p (inv_code, cmp1))
{
cmp1 = force_reg (GET_MODE (cmp0), cmp1);
mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
}
else if (invert_ptr == 0)
{
rtx inv_target = gen_reg_rtx (GET_MODE (target));
mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
mips_emit_binary (XOR, target, inv_target, const1_rtx);
}
else
{
*invert_ptr = !*invert_ptr;
mips_emit_binary (inv_code, target, cmp0, cmp1);
}
}
}
static rtx
mips_zero_if_equal (rtx cmp0, rtx cmp1)
{
if (cmp1 == const0_rtx)
return cmp0;
if (uns_arith_operand (cmp1, VOIDmode))
return expand_binop (GET_MODE (cmp0), xor_optab,
cmp0, cmp1, 0, 0, OPTAB_DIRECT);
return expand_binop (GET_MODE (cmp0), sub_optab,
cmp0, cmp1, 0, 0, OPTAB_DIRECT);
}
static void
mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
{
if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
{
*op0 = cmp_operands[0];
*op1 = cmp_operands[1];
}
else if (*code == EQ || *code == NE)
{
if (need_eq_ne_p)
{
*op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
*op1 = const0_rtx;
}
else
{
*op0 = cmp_operands[0];
*op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
}
}
else
{
bool invert = false;
*op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
*op1 = const0_rtx;
mips_emit_int_relational (*code, &invert, *op0,
cmp_operands[0], cmp_operands[1]);
*code = (invert ? EQ : NE);
}
}
else
{
enum rtx_code cmp_code;
switch (*code)
{
case NE:
case UNGE:
case UNGT:
case LTGT:
case ORDERED:
cmp_code = reverse_condition_maybe_unordered (*code);
*code = EQ;
break;
default:
cmp_code = *code;
*code = NE;
break;
}
*op0 = (ISA_HAS_8CC
? gen_reg_rtx (CCmode)
: gen_rtx_REG (CCmode, FPSW_REGNUM));
*op1 = const0_rtx;
mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
}
}
bool
mips_emit_scc (enum rtx_code code, rtx target)
{
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
return false;
target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
if (code == EQ || code == NE)
{
rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
mips_emit_binary (code, target, zie, const0_rtx);
}
else
mips_emit_int_relational (code, 0, target,
cmp_operands[0], cmp_operands[1]);
return true;
}
void
gen_conditional_branch (rtx *operands, enum rtx_code code)
{
rtx op0, op1, target;
mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
target = gen_rtx_IF_THEN_ELSE (VOIDmode,
gen_rtx_fmt_ee (code, GET_MODE (op0),
op0, op1),
gen_rtx_LABEL_REF (VOIDmode, operands[0]),
pc_rtx);
emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, target));
}
void
gen_conditional_move (rtx *operands)
{
enum rtx_code code;
rtx op0, op1;
code = GET_CODE (operands[1]);
mips_emit_compare (&code, &op0, &op1, true);
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
gen_rtx_fmt_ee (code,
GET_MODE (op0),
op0, op1),
operands[2], operands[3])));
}
void
mips_gen_conditional_trap (rtx *operands)
{
rtx op0, op1;
enum rtx_code cmp_code = GET_CODE (operands[0]);
enum machine_mode mode = GET_MODE (cmp_operands[0]);
switch (cmp_code)
{
case GT: cmp_code = LT; break;
case LE: cmp_code = GE; break;
case GTU: cmp_code = LTU; break;
case LEU: cmp_code = GEU; break;
default: break;
}
if (cmp_code == GET_CODE (operands[0]))
{
op0 = cmp_operands[0];
op1 = cmp_operands[1];
}
else
{
op0 = cmp_operands[1];
op1 = cmp_operands[0];
}
op0 = force_reg (mode, op0);
if (!arith_operand (op1, mode))
op1 = force_reg (mode, op1);
emit_insn (gen_rtx_TRAP_IF (VOIDmode,
gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
operands[1]));
}
static void
mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
{
if (TARGET_EXPLICIT_RELOCS
&& !(sibcall_p && TARGET_NEWABI)
&& global_got_operand (addr, VOIDmode))
{
rtx high, lo_sum_symbol;
high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
addr, SYMBOL_GOTOFF_CALL);
lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
if (Pmode == SImode)
emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
else
emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
}
else
emit_move_insn (dest, addr);
}
void
mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
{
rtx orig_addr, pattern, insn;
orig_addr = addr;
if (!call_insn_operand (addr, VOIDmode))
{
addr = gen_reg_rtx (Pmode);
mips_load_call_address (addr, orig_addr, sibcall_p);
}
if (TARGET_MIPS16
&& mips16_hard_float
&& build_mips16_call_stub (result, addr, args_size,
aux == 0 ? 0 : (int) GET_MODE (aux)))
return;
if (result == 0)
pattern = (sibcall_p
? gen_sibcall_internal (addr, args_size)
: gen_call_internal (addr, args_size));
else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
{
rtx reg1, reg2;
reg1 = XEXP (XVECEXP (result, 0, 0), 0);
reg2 = XEXP (XVECEXP (result, 0, 1), 0);
pattern =
(sibcall_p
? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
: gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
}
else
pattern = (sibcall_p
? gen_sibcall_value_internal (result, addr, args_size)
: gen_call_value_internal (result, addr, args_size));
insn = emit_call_insn (pattern);
if (global_got_operand (orig_addr, VOIDmode))
use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
}
static bool
mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
tree exp ATTRIBUTE_UNUSED)
{
return TARGET_SIBCALLS;
}
void
mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
{
rtx fp1, fp2;
if (MEM_P (src))
src = adjust_address (src, SFmode, 0);
else if (REG_P (src) || GET_CODE (src) == SUBREG)
src = gen_rtx_REG (SFmode, true_regnum (src));
fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
emit_move_insn (copy_rtx (fp1), src);
emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
emit_insn (gen_slt_sf (dest, fp2, fp1));
}
void
mips_set_return_address (rtx address, rtx scratch)
{
rtx slot_address;
compute_frame_size (get_frame_size ());
gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
slot_address = mips_add_offset (scratch, stack_pointer_rtx,
cfun->machine->frame.gp_sp_offset);
emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
}
static void
mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
{
HOST_WIDE_INT offset, delta;
unsigned HOST_WIDE_INT bits;
int i;
enum machine_mode mode;
rtx *regs;
if (MEM_ALIGN (src) == BITS_PER_WORD / 2
&& MEM_ALIGN (dest) == BITS_PER_WORD / 2)
bits = BITS_PER_WORD / 2;
else
bits = BITS_PER_WORD;
mode = mode_for_size (bits, MODE_INT, 0);
delta = bits / BITS_PER_UNIT;
regs = alloca (sizeof (rtx) * length / delta);
for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
{
regs[i] = gen_reg_rtx (mode);
if (MEM_ALIGN (src) >= bits)
emit_move_insn (regs[i], adjust_address (src, mode, offset));
else
{
rtx part = adjust_address (src, BLKmode, offset);
if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
gcc_unreachable ();
}
}
for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
if (MEM_ALIGN (dest) >= bits)
emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
else
{
rtx part = adjust_address (dest, BLKmode, offset);
if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
gcc_unreachable ();
}
if (offset < length)
{
src = adjust_address (src, BLKmode, offset);
dest = adjust_address (dest, BLKmode, offset);
move_by_pieces (dest, src, length - offset,
MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
}
}
#define MAX_MOVE_REGS 4
#define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
static void
mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
rtx *loop_reg, rtx *loop_mem)
{
*loop_reg = copy_addr_to_reg (XEXP (mem, 0));
*loop_mem = change_address (mem, BLKmode, *loop_reg);
set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
}
static void
mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
{
rtx label, src_reg, dest_reg, final_src;
HOST_WIDE_INT leftover;
leftover = length % MAX_MOVE_BYTES;
length -= leftover;
mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
0, 0, OPTAB_WIDEN);
label = gen_label_rtx ();
emit_label (label);
mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
if (Pmode == DImode)
emit_insn (gen_cmpdi (src_reg, final_src));
else
emit_insn (gen_cmpsi (src_reg, final_src));
emit_jump_insn (gen_bne (label));
if (leftover)
mips_block_move_straight (dest, src, leftover);
}
bool
mips_expand_block_move (rtx dest, rtx src, rtx length)
{
if (GET_CODE (length) == CONST_INT)
{
if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
{
mips_block_move_straight (dest, src, INTVAL (length));
return true;
}
else if (optimize)
{
mips_block_move_loop (dest, src, INTVAL (length));
return true;
}
}
return false;
}
void
init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
rtx libname ATTRIBUTE_UNUSED)
{
static CUMULATIVE_ARGS zero_cum;
tree param, next_param;
*cum = zero_cum;
cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
param != 0; param = next_param)
{
next_param = TREE_CHAIN (param);
if (next_param == 0 && TREE_VALUE (param) != void_type_node)
cum->gp_reg_found = 1;
}
}
static void
mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
tree type, int named, struct mips_arg_info *info)
{
bool doubleword_aligned_p;
unsigned int num_bytes, num_words, max_regs;
num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
switch (mips_abi)
{
case ABI_EABI:
info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
|| GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
&& GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
break;
case ABI_32:
case ABI_O64:
info->fpr_p = (!cum->gp_reg_found
&& cum->arg_number < 2
&& (type == 0 || SCALAR_FLOAT_TYPE_P (type)
|| VECTOR_FLOAT_TYPE_P (type))
&& (GET_MODE_CLASS (mode) == MODE_FLOAT
|| GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
&& GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
break;
case ABI_N32:
case ABI_64:
info->fpr_p = (named
&& (type == 0 || FLOAT_TYPE_P (type))
&& (GET_MODE_CLASS (mode) == MODE_FLOAT
|| GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
|| GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
&& GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
if (info->fpr_p
&& GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
&& GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
{
if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
info->fpr_p = false;
else
num_words = 2;
}
break;
default:
gcc_unreachable ();
}
doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
? cum->num_fprs
: cum->num_gprs);
if (doubleword_aligned_p)
info->reg_offset += info->reg_offset & 1;
info->stack_offset = cum->stack_words;
if (doubleword_aligned_p)
info->stack_offset += info->stack_offset & 1;
max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
info->reg_words = MIN (num_words, max_regs);
info->stack_words = num_words - info->reg_words;
}
void
function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
tree type, int named)
{
struct mips_arg_info info;
mips_arg_info (cum, mode, type, named, &info);
if (!info.fpr_p)
cum->gp_reg_found = true;
if (cum->arg_number < 2 && info.fpr_p)
cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
if (mips_abi != ABI_EABI || !info.fpr_p)
cum->num_gprs = info.reg_offset + info.reg_words;
else if (info.reg_words > 0)
cum->num_fprs += FP_INC;
if (info.stack_words > 0)
cum->stack_words = info.stack_offset + info.stack_words;
cum->arg_number++;
}
struct rtx_def *
function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
tree type, int named)
{
struct mips_arg_info info;
if (mode == VOIDmode)
{
if (TARGET_MIPS16 && cum->fp_code != 0)
return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
else
return 0;
}
mips_arg_info (cum, mode, type, named, &info);
if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
return 0;
if (type != 0
&& TREE_CODE (type) == RECORD_TYPE
&& TARGET_NEWABI
&& TYPE_SIZE_UNIT (type)
&& host_integerp (TYPE_SIZE_UNIT (type), 1)
&& named)
{
tree field;
for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
if (TREE_CODE (field) == FIELD_DECL
&& TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
&& TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
&& host_integerp (bit_position (field), 0)
&& int_bit_position (field) % BITS_PER_WORD == 0)
break;
if (field != 0)
{
unsigned int i;
HOST_WIDE_INT bitpos;
rtx ret;
ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
bitpos = 0;
field = TYPE_FIELDS (type);
for (i = 0; i < info.reg_words; i++)
{
rtx reg;
for (; field; field = TREE_CHAIN (field))
if (TREE_CODE (field) == FIELD_DECL
&& int_bit_position (field) >= bitpos)
break;
if (field
&& int_bit_position (field) == bitpos
&& TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
&& !TARGET_SOFT_FLOAT
&& TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
else
reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
XVECEXP (ret, 0, i)
= gen_rtx_EXPR_LIST (VOIDmode, reg,
GEN_INT (bitpos / BITS_PER_UNIT));
bitpos += BITS_PER_WORD;
}
return ret;
}
}
if (TARGET_NEWABI
&& info.fpr_p
&& GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
{
rtx real, imag;
enum machine_mode inner;
int reg;
inner = GET_MODE_INNER (mode);
reg = FP_ARG_FIRST + info.reg_offset;
real = gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_REG (inner, reg),
const0_rtx);
imag = gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_REG (inner, reg + info.reg_words / 2),
GEN_INT (GET_MODE_SIZE (inner)));
return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
}
if (!info.fpr_p)
return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
else if (info.reg_offset == 1)
return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
else
return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
}
static int
mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
enum machine_mode mode, tree type, bool named)
{
struct mips_arg_info info;
mips_arg_info (cum, mode, type, named, &info);
return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
}
int
function_arg_boundary (enum machine_mode mode, tree type)
{
unsigned int alignment;
alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
if (alignment < PARM_BOUNDARY)
alignment = PARM_BOUNDARY;
if (alignment > STACK_BOUNDARY)
alignment = STACK_BOUNDARY;
return alignment;
}
bool
mips_pad_arg_upward (enum machine_mode mode, tree type)
{
if (!BYTES_BIG_ENDIAN)
return true;
if (type != 0
? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
: GET_MODE_CLASS (mode) == MODE_INT)
return false;
if (mips_abi == ABI_O64)
if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
return false;
if (mips_abi != ABI_EABI)
return true;
if (mode != BLKmode)
return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
else
return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
}
bool
mips_pad_reg_upward (enum machine_mode mode, tree type)
{
if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
return !BYTES_BIG_ENDIAN;
return mips_pad_arg_upward (mode, type);
}
static void
mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
tree type, int *pretend_size, int no_rtl)
{
CUMULATIVE_ARGS local_cum;
int gp_saved, fp_saved;
local_cum = *cum;
FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
fp_saved = (EABI_FLOAT_VARARGS_P
? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
: 0);
if (!no_rtl)
{
if (gp_saved > 0)
{
rtx ptr, mem;
ptr = virtual_incoming_args_rtx;
switch (mips_abi)
{
case ABI_32:
case ABI_O64:
ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
break;
case ABI_EABI:
ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
break;
}
mem = gen_rtx_MEM (BLKmode, ptr);
set_mem_alias_set (mem, get_varargs_alias_set ());
move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
mem, gp_saved);
}
if (fp_saved > 0)
{
enum machine_mode mode;
int off, i;
off = -gp_saved * UNITS_PER_WORD;
off &= ~(UNITS_PER_FPVALUE - 1);
off -= fp_saved * UNITS_PER_FPREG;
mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
{
rtx ptr, mem;
ptr = plus_constant (virtual_incoming_args_rtx, off);
mem = gen_rtx_MEM (mode, ptr);
set_mem_alias_set (mem, get_varargs_alias_set ());
emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
off += UNITS_PER_HWFPVALUE;
}
}
}
if (TARGET_OLDABI)
{
*pretend_size = 0;
return;
}
*pretend_size = (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
}
static tree
mips_build_builtin_va_list (void)
{
if (EABI_FLOAT_VARARGS_P)
{
tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
tree array, index;
record = (*lang_hooks.types.make_type) (RECORD_TYPE);
f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
ptr_type_node);
f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
ptr_type_node);
f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
ptr_type_node);
f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
unsigned_char_type_node);
f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
unsigned_char_type_node);
index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
array = build_array_type (unsigned_char_type_node,
build_index_type (index));
f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
DECL_FIELD_CONTEXT (f_ovfl) = record;
DECL_FIELD_CONTEXT (f_gtop) = record;
DECL_FIELD_CONTEXT (f_ftop) = record;
DECL_FIELD_CONTEXT (f_goff) = record;
DECL_FIELD_CONTEXT (f_foff) = record;
DECL_FIELD_CONTEXT (f_res) = record;
TYPE_FIELDS (record) = f_ovfl;
TREE_CHAIN (f_ovfl) = f_gtop;
TREE_CHAIN (f_gtop) = f_ftop;
TREE_CHAIN (f_ftop) = f_goff;
TREE_CHAIN (f_goff) = f_foff;
TREE_CHAIN (f_foff) = f_res;
layout_type (record);
return record;
}
else if (TARGET_IRIX && TARGET_IRIX6)
return build_pointer_type (char_type_node);
else
return ptr_type_node;
}
void
mips_va_start (tree valist, rtx nextarg)
{
const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
if (cfun && cfun->emit->regno_pointer_align)
while (((current_function_pretend_args_size * BITS_PER_UNIT)
& (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
if (mips_abi == ABI_EABI)
{
int gpr_save_area_size;
gpr_save_area_size
= (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
if (EABI_FLOAT_VARARGS_P)
{
tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
tree ovfl, gtop, ftop, goff, foff;
tree t;
int fpr_offset;
int fpr_save_area_size;
f_ovfl = TYPE_FIELDS (va_list_type_node);
f_gtop = TREE_CHAIN (f_ovfl);
f_ftop = TREE_CHAIN (f_gtop);
f_goff = TREE_CHAIN (f_ftop);
f_foff = TREE_CHAIN (f_goff);
ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
NULL_TREE);
gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
NULL_TREE);
ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
NULL_TREE);
goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
NULL_TREE);
foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
NULL_TREE);
t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
if (cum->stack_words > 0)
t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
build_int_cst (NULL_TREE,
cum->stack_words * UNITS_PER_WORD));
t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
if (fpr_offset)
t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
build_int_cst (NULL_TREE, -fpr_offset));
t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
build_int_cst (NULL_TREE, gpr_save_area_size));
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
fpr_save_area_size
= (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
build_int_cst (NULL_TREE, fpr_save_area_size));
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}
else
{
nextarg = plus_constant (nextarg, -gpr_save_area_size);
std_expand_builtin_va_start (valist, nextarg);
}
}
else
std_expand_builtin_va_start (valist, nextarg);
}
static tree
mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
{
HOST_WIDE_INT size, rsize;
tree addr;
bool indirect;
indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
if (indirect)
type = build_pointer_type (type);
size = int_size_in_bytes (type);
rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
else
{
tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
tree ovfl, top, off, align;
HOST_WIDE_INT osize;
tree t, u;
f_ovfl = TYPE_FIELDS (va_list_type_node);
f_gtop = TREE_CHAIN (f_ovfl);
f_ftop = TREE_CHAIN (f_gtop);
f_goff = TREE_CHAIN (f_ftop);
f_foff = TREE_CHAIN (f_goff);
ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
NULL_TREE);
if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
&& GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
{
top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
NULL_TREE);
off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
NULL_TREE);
rsize = UNITS_PER_HWFPVALUE;
osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
}
else
{
top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
NULL_TREE);
off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
NULL_TREE);
if (rsize > UNITS_PER_WORD)
{
t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
build_int_cst (NULL_TREE, -rsize));
t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
gimplify_and_add (t, pre_p);
}
osize = rsize;
}
t = lang_hooks.truthvalue_conversion (off);
addr = build (COND_EXPR, ptr_type_node, t, NULL, NULL);
t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
t = build (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
t = fold_convert (sizetype, t);
t = fold_convert (TREE_TYPE (top), t);
t = build (MINUS_EXPR, TREE_TYPE (top), top, t);
if (BYTES_BIG_ENDIAN && rsize > size)
{
u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
rsize - size));
t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
}
COND_EXPR_THEN (addr) = t;
if (osize > UNITS_PER_WORD)
{
u = fold_convert (TREE_TYPE (ovfl),
build_int_cst (NULL_TREE, osize - 1));
t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
u = fold_convert (TREE_TYPE (ovfl),
build_int_cst (NULL_TREE, -osize));
t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
align = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
}
else
align = NULL;
u = fold_convert (TREE_TYPE (ovfl),
build_int_cst (NULL_TREE, osize));
t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
if (BYTES_BIG_ENDIAN && osize > size)
{
u = fold_convert (TREE_TYPE (t),
build_int_cst (NULL_TREE, osize - size));
t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
}
if (align)
t = build (COMPOUND_EXPR, TREE_TYPE (t), align, t);
COND_EXPR_ELSE (addr) = t;
addr = fold_convert (build_pointer_type (type), addr);
addr = build_fold_indirect_ref (addr);
}
if (indirect)
addr = build_fold_indirect_ref (addr);
return addr;
}
static bool
mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
rtx *left, rtx *right)
{
rtx first, last;
if (!MEM_P (*op))
return false;
if (width != 32 && (!TARGET_64BIT || width != 64))
return false;
if (bitpos % BITS_PER_UNIT != 0)
return false;
if (MEM_ALIGN (*op) >= width)
return false;
*op = adjust_address (*op, BLKmode, 0);
set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
first = adjust_address (*op, QImode, 0);
last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
if (TARGET_BIG_ENDIAN)
*left = first, *right = last;
else
*left = last, *right = first;
return true;
}
bool
mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
{
rtx left, right, temp;
if (GET_CODE (dest) == SUBREG
&& GET_MODE (dest) == DImode
&& SUBREG_BYTE (dest) == 0
&& GET_MODE (SUBREG_REG (dest)) == SImode)
dest = SUBREG_REG (dest);
if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
return false;
if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
return false;
temp = gen_reg_rtx (GET_MODE (dest));
if (GET_MODE (dest) == DImode)
{
emit_insn (gen_mov_ldl (temp, src, left));
emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
}
else
{
emit_insn (gen_mov_lwl (temp, src, left));
emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
}
return true;
}
bool
mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
{
rtx left, right;
if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
return false;
src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
if (GET_MODE (src) == DImode)
{
emit_insn (gen_mov_sdl (dest, src, left));
emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
}
else
{
emit_insn (gen_mov_swl (dest, src, left));
emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
}
return true;
}
static void
mips_set_architecture (const struct mips_cpu_info *info)
{
if (info != 0)
{
mips_arch_info = info;
mips_arch = info->cpu;
mips_isa = info->isa;
}
}
static void
mips_set_tune (const struct mips_cpu_info *info)
{
if (info != 0)
{
mips_tune_info = info;
mips_tune = info->cpu;
}
}
void
override_options (void)
{
int i, start, regno;
enum machine_mode mode;
mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
mips_abi = MIPS_ABI_DEFAULT;
if (mips_abi_string != 0)
{
if (strcmp (mips_abi_string, "32") == 0)
mips_abi = ABI_32;
else if (strcmp (mips_abi_string, "o64") == 0)
mips_abi = ABI_O64;
else if (strcmp (mips_abi_string, "n32") == 0)
mips_abi = ABI_N32;
else if (strcmp (mips_abi_string, "64") == 0)
mips_abi = ABI_64;
else if (strcmp (mips_abi_string, "eabi") == 0)
mips_abi = ABI_EABI;
else
fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
}
if (mips_arch_string != 0)
mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
if (mips_isa_string != 0)
{
char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
const struct mips_cpu_info *isa_info;
isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
free (whole_isa_str);
if (mips_arch_info != 0 && mips_isa != isa_info->isa)
error ("-mips%s conflicts with the other architecture options, "
"which specify a MIPS%d processor",
mips_isa_string, mips_isa);
mips_set_architecture (isa_info);
}
if (mips_arch_info == 0)
{
#ifdef MIPS_CPU_STRING_DEFAULT
mips_set_architecture (mips_parse_cpu ("default CPU",
MIPS_CPU_STRING_DEFAULT));
#else
mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
#endif
}
if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
error ("-march=%s is not compatible with the selected ABI",
mips_arch_info->name);
if (mips_tune_string != 0)
mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
if (mips_tune_info == 0)
mips_set_tune (mips_arch_info);
if ((target_flags_explicit & MASK_64BIT) != 0)
{
if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
error ("-mgp64 used with a 32-bit processor");
else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
error ("-mgp32 used with a 64-bit ABI");
else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
error ("-mgp64 used with a 32-bit ABI");
}
else
{
if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
target_flags &= ~MASK_64BIT;
else
target_flags |= MASK_64BIT;
}
if ((target_flags_explicit & MASK_FLOAT64) != 0)
{
if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
else if (!TARGET_64BIT && TARGET_FLOAT64)
error ("unsupported combination: %s", "-mgp32 -mfp64");
else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
error ("unsupported combination: %s", "-mfp64 -msingle-float");
}
else
{
if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
target_flags |= MASK_FLOAT64;
else
target_flags &= ~MASK_FLOAT64;
}
if ((target_flags_explicit & MASK_LONG64) == 0)
{
if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
target_flags |= MASK_LONG64;
else
target_flags &= ~MASK_LONG64;
}
if (TARGET_INT64)
warning ("-mint64 is a deprecated option");
if (mips_fix_vr4130_string && mips_fix_vr4130_string[0] != 0)
error ("unrecognized option %<-mfix-vr4130%s%>", mips_fix_vr4130_string);
if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
&& (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
{
switch ((int) mips_arch)
{
case PROCESSOR_R4100:
case PROCESSOR_R4111:
case PROCESSOR_R4120:
case PROCESSOR_R4130:
target_flags |= MASK_SOFT_FLOAT;
break;
default:
target_flags &= ~MASK_SOFT_FLOAT;
break;
}
}
if (!TARGET_OLDABI)
flag_pcc_struct_return = 0;
if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
{
if (ISA_HAS_BRANCHLIKELY
&& !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
&& !(TUNE_MIPS5500 || TUNE_SB1))
target_flags |= MASK_BRANCHLIKELY;
else
target_flags &= ~MASK_BRANCHLIKELY;
}
if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
if (mips_abi == ABI_EABI && TARGET_ABICALLS)
{
error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
target_flags &= ~MASK_ABICALLS;
}
if (TARGET_ABICALLS)
{
flag_pic = 1;
if (mips_section_threshold > 0)
warning ("-G is incompatible with PIC code which is the default");
}
if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
&& optimize && !flag_pic
&& !ABI_HAS_64BIT_SYMBOLS)
mips_split_addresses = 1;
else
mips_split_addresses = 0;
if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
target_flags |= MASK_VR4130_ALIGN;
if (TARGET_MIPS16)
{
if (TARGET_SOFT_FLOAT)
mips16_hard_float = 0;
else
mips16_hard_float = 1;
target_flags |= MASK_SOFT_FLOAT;
flag_schedule_insns = 0;
flag_reorder_blocks_and_partition = 0;
target_flags &= ~MASK_EXPLICIT_RELOCS;
}
if (TARGET_EXPLICIT_RELOCS)
{
mips_flag_delayed_branch = flag_delayed_branch;
flag_delayed_branch = 0;
}
#ifdef MIPS_TFMODE_FORMAT
REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
#endif
if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE)
&& !TARGET_PAIRED_SINGLE_FLOAT)
error ("-mips3d requires -mpaired-single");
if (TARGET_MIPS3D)
target_flags |= MASK_PAIRED_SINGLE;
if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
error ("-mips3d/-mpaired-single must be used with -mips64");
mips_print_operand_punct['?'] = 1;
mips_print_operand_punct['#'] = 1;
mips_print_operand_punct['/'] = 1;
mips_print_operand_punct['&'] = 1;
mips_print_operand_punct['!'] = 1;
mips_print_operand_punct['*'] = 1;
mips_print_operand_punct['@'] = 1;
mips_print_operand_punct['.'] = 1;
mips_print_operand_punct['('] = 1;
mips_print_operand_punct[')'] = 1;
mips_print_operand_punct['['] = 1;
mips_print_operand_punct[']'] = 1;
mips_print_operand_punct['<'] = 1;
mips_print_operand_punct['>'] = 1;
mips_print_operand_punct['{'] = 1;
mips_print_operand_punct['}'] = 1;
mips_print_operand_punct['^'] = 1;
mips_print_operand_punct['$'] = 1;
mips_print_operand_punct['+'] = 1;
mips_print_operand_punct['~'] = 1;
mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
mips_char_to_class['t'] = T_REG;
mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
mips_char_to_class['h'] = HI_REG;
mips_char_to_class['l'] = LO_REG;
mips_char_to_class['x'] = MD_REGS;
mips_char_to_class['b'] = ALL_REGS;
mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
TARGET_MIPS16 ? M16_NA_REGS :
GR_REGS);
mips_char_to_class['e'] = LEA_REGS;
mips_char_to_class['j'] = PIC_FN_ADDR_REG;
mips_char_to_class['y'] = GR_REGS;
mips_char_to_class['z'] = ST_REGS;
mips_char_to_class['B'] = COP0_REGS;
mips_char_to_class['C'] = COP2_REGS;
mips_char_to_class['D'] = COP3_REGS;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
mips_dbx_regno[i] = -1;
start = GP_DBX_FIRST - GP_REG_FIRST;
for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
mips_dbx_regno[i] = i + start;
start = FP_DBX_FIRST - FP_REG_FIRST;
for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
mips_dbx_regno[i] = i + start;
mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
for (mode = VOIDmode;
mode != MAX_MACHINE_MODE;
mode = (enum machine_mode) ((int)mode + 1))
{
register int size = GET_MODE_SIZE (mode);
register enum mode_class class = GET_MODE_CLASS (mode);
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
{
register int temp;
if (mode == CCV2mode)
temp = (ISA_HAS_8CC
&& ST_REG_P (regno)
&& (regno - ST_REG_FIRST) % 2 == 0);
else if (mode == CCV4mode)
temp = (ISA_HAS_8CC
&& ST_REG_P (regno)
&& (regno - ST_REG_FIRST) % 4 == 0);
else if (mode == CCmode)
{
if (! ISA_HAS_8CC)
temp = (regno == FPSW_REGNUM);
else
temp = (ST_REG_P (regno) || GP_REG_P (regno)
|| FP_REG_P (regno));
}
else if (GP_REG_P (regno))
temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
else if (FP_REG_P (regno))
temp = ((regno % FP_INC) == 0)
&& (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
|| class == MODE_VECTOR_FLOAT)
&& size <= UNITS_PER_FPVALUE)
|| (class == MODE_INT && size <= UNITS_PER_FPREG)
|| (ISA_HAS_8CC && mode == TFmode));
else if (MD_REG_P (regno))
temp = (INTEGRAL_MODE_P (mode)
&& (size <= UNITS_PER_WORD
|| (regno == MD_REG_FIRST
&& size == 2 * UNITS_PER_WORD)));
else if (ALL_COP_REG_P (regno))
temp = (class == MODE_INT && size <= UNITS_PER_WORD);
else
temp = 0;
mips_hard_regno_mode_ok[(int)mode][regno] = temp;
}
}
gpr_mode = TARGET_64BIT ? DImode : SImode;
if (TARGET_64BIT && !TARGET_MIPS16)
{
if (align_loops == 0)
align_loops = 8;
if (align_jumps == 0)
align_jumps = 8;
if (align_functions == 0)
align_functions = 8;
}
init_machine_status = &mips_init_machine_status;
if (ABI_HAS_64BIT_SYMBOLS)
{
if (TARGET_EXPLICIT_RELOCS)
{
mips_split_p[SYMBOL_64_HIGH] = true;
mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
mips_split_p[SYMBOL_64_MID] = true;
mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
mips_split_p[SYMBOL_64_LOW] = true;
mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
mips_split_p[SYMBOL_GENERAL] = true;
mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
}
}
else
{
if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
{
mips_split_p[SYMBOL_GENERAL] = true;
mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
}
}
if (TARGET_MIPS16)
{
mips_split_p[SYMBOL_SMALL_DATA] = true;
mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
}
if (TARGET_EXPLICIT_RELOCS)
{
mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
mips_split_p[SYMBOL_GOT_LOCAL] = true;
if (TARGET_NEWABI)
{
mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
}
else
{
mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
}
if (TARGET_XGOT)
{
mips_split_p[SYMBOL_GOT_GLOBAL] = true;
mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
mips_split_p[SYMBOL_GOTOFF_CALL] = true;
mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
}
else
{
if (TARGET_NEWABI)
mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
else
mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
}
}
if (TARGET_NEWABI)
{
mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
}
if ((target_flags_explicit & MASK_FIX_R4000) == 0
&& mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
target_flags |= MASK_FIX_R4000;
if ((target_flags_explicit & MASK_FIX_R4400) == 0
&& mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
target_flags |= MASK_FIX_R4400;
}
void
mips_conditional_register_usage (void)
{
if (!TARGET_HARD_FLOAT)
{
int regno;
for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
fixed_regs[regno] = call_used_regs[regno] = 1;
for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
fixed_regs[regno] = call_used_regs[regno] = 1;
}
else if (! ISA_HAS_8CC)
{
int regno;
for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
fixed_regs[regno] = call_used_regs[regno] = 1;
}
if (TARGET_MIPS16)
{
fixed_regs[18] = call_used_regs[18] = 1;
fixed_regs[19] = call_used_regs[19] = 1;
fixed_regs[20] = call_used_regs[20] = 1;
fixed_regs[21] = call_used_regs[21] = 1;
fixed_regs[22] = call_used_regs[22] = 1;
fixed_regs[23] = call_used_regs[23] = 1;
fixed_regs[26] = call_used_regs[26] = 1;
fixed_regs[27] = call_used_regs[27] = 1;
fixed_regs[30] = call_used_regs[30] = 1;
}
if (mips_abi == ABI_64)
{
int regno;
for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
call_really_used_regs[regno] = call_used_regs[regno] = 1;
}
if (mips_abi == ABI_N32)
{
int regno;
for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
call_really_used_regs[regno] = call_used_regs[regno] = 1;
}
}
static struct machine_function *
mips_init_machine_status (void)
{
return ((struct machine_function *)
ggc_alloc_cleared (sizeof (struct machine_function)));
}
void
mips_order_regs_for_local_alloc (void)
{
register int i;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
reg_alloc_order[i] = i;
if (TARGET_MIPS16)
{
reg_alloc_order[0] = 24;
reg_alloc_order[24] = 0;
}
}
HOST_WIDE_INT
mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
{
rtx offset2 = const0_rtx;
rtx reg = eliminate_constant_term (addr, &offset2);
if (offset == 0)
offset = INTVAL (offset2);
if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
|| reg == hard_frame_pointer_rtx)
{
HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
? compute_frame_size (get_frame_size ())
: cfun->machine->frame.total_size;
if (frame_pointer_needed && TARGET_MIPS16)
frame_size -= cfun->machine->frame.args_size;
offset = offset - frame_size;
}
#if 0
else if (reg != arg_pointer_rtx)
fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
addr);
#endif
return offset;
}
void
print_operand (FILE *file, rtx op, int letter)
{
register enum rtx_code code;
if (PRINT_OPERAND_PUNCT_VALID_P (letter))
{
switch (letter)
{
case '?':
if (mips_branch_likely)
putc ('l', file);
break;
case '@':
fputs (reg_names [GP_REG_FIRST + 1], file);
break;
case '^':
fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
break;
case '.':
fputs (reg_names [GP_REG_FIRST + 0], file);
break;
case '$':
fputs (reg_names[STACK_POINTER_REGNUM], file);
break;
case '+':
fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
break;
case '&':
if (final_sequence != 0 && set_noreorder++ == 0)
fputs (".set\tnoreorder\n\t", file);
break;
case '*':
if (final_sequence != 0)
{
if (set_noreorder++ == 0)
fputs (".set\tnoreorder\n\t", file);
if (set_nomacro++ == 0)
fputs (".set\tnomacro\n\t", file);
}
break;
case '!':
if (final_sequence != 0 && set_nomacro++ == 0)
fputs ("\n\t.set\tnomacro", file);
break;
case '#':
if (set_noreorder != 0)
fputs ("\n\tnop", file);
break;
case '/':
if (set_noreorder != 0 && final_sequence == 0)
fputs ("\n\tnop\n", file);
break;
case '(':
if (set_noreorder++ == 0)
fputs (".set\tnoreorder\n\t", file);
break;
case ')':
if (set_noreorder == 0)
error ("internal error: %%) found without a %%( in assembler pattern");
else if (--set_noreorder == 0)
fputs ("\n\t.set\treorder", file);
break;
case '[':
if (set_noat++ == 0)
fputs (".set\tnoat\n\t", file);
break;
case ']':
if (set_noat == 0)
error ("internal error: %%] found without a %%[ in assembler pattern");
else if (--set_noat == 0)
fputs ("\n\t.set\tat", file);
break;
case '<':
if (set_nomacro++ == 0)
fputs (".set\tnomacro\n\t", file);
break;
case '>':
if (set_nomacro == 0)
error ("internal error: %%> found without a %%< in assembler pattern");
else if (--set_nomacro == 0)
fputs ("\n\t.set\tmacro", file);
break;
case '{':
if (set_volatile++ == 0)
fputs ("#.set\tvolatile\n\t", file);
break;
case '}':
if (set_volatile == 0)
error ("internal error: %%} found without a %%{ in assembler pattern");
else if (--set_volatile == 0)
fputs ("\n\t#.set\tnovolatile", file);
break;
case '~':
{
if (align_labels_log > 0)
ASM_OUTPUT_ALIGN (file, align_labels_log);
}
break;
default:
error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
break;
}
return;
}
if (! op)
{
error ("PRINT_OPERAND null pointer");
return;
}
code = GET_CODE (op);
if (letter == 'C')
switch (code)
{
case EQ: fputs ("eq", file); break;
case NE: fputs ("ne", file); break;
case GT: fputs ("gt", file); break;
case GE: fputs ("ge", file); break;
case LT: fputs ("lt", file); break;
case LE: fputs ("le", file); break;
case GTU: fputs ("gtu", file); break;
case GEU: fputs ("geu", file); break;
case LTU: fputs ("ltu", file); break;
case LEU: fputs ("leu", file); break;
default:
fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
}
else if (letter == 'N')
switch (code)
{
case EQ: fputs ("ne", file); break;
case NE: fputs ("eq", file); break;
case GT: fputs ("le", file); break;
case GE: fputs ("lt", file); break;
case LT: fputs ("ge", file); break;
case LE: fputs ("gt", file); break;
case GTU: fputs ("leu", file); break;
case GEU: fputs ("ltu", file); break;
case LTU: fputs ("geu", file); break;
case LEU: fputs ("gtu", file); break;
default:
fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
}
else if (letter == 'F')
switch (code)
{
case EQ: fputs ("c1f", file); break;
case NE: fputs ("c1t", file); break;
default:
fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
}
else if (letter == 'W')
switch (code)
{
case EQ: fputs ("c1t", file); break;
case NE: fputs ("c1f", file); break;
default:
fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
}
else if (letter == 'h')
{
if (GET_CODE (op) == HIGH)
op = XEXP (op, 0);
print_operand_reloc (file, op, mips_hi_relocs);
}
else if (letter == 'R')
print_operand_reloc (file, op, mips_lo_relocs);
else if (letter == 'Y')
{
if (GET_CODE (op) == CONST_INT
&& ((unsigned HOST_WIDE_INT) INTVAL (op)
< ARRAY_SIZE (mips_fp_conditions)))
fputs (mips_fp_conditions[INTVAL (op)], file);
else
output_operand_lossage ("invalid %%Y value");
}
else if (letter == 'Z')
{
if (ISA_HAS_8CC)
{
print_operand (file, op, 0);
fputc (',', file);
}
}
else if (code == REG || code == SUBREG)
{
register int regnum;
if (code == REG)
regnum = REGNO (op);
else
regnum = true_regnum (op);
if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
|| (letter == 'L' && WORDS_BIG_ENDIAN)
|| letter == 'D')
regnum++;
fprintf (file, "%s", reg_names[regnum]);
}
else if (code == MEM)
{
if (letter == 'D')
output_address (plus_constant (XEXP (op, 0), 4));
else
output_address (XEXP (op, 0));
}
else if (letter == 'x' && GET_CODE (op) == CONST_INT)
fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
else if (letter == 'X' && GET_CODE(op) == CONST_INT)
fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
else if (letter == 'd' && GET_CODE(op) == CONST_INT)
fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
fputs (reg_names[GP_REG_FIRST], file);
else if (letter == 'd' || letter == 'x' || letter == 'X')
output_operand_lossage ("invalid use of %%d, %%x, or %%X");
else if (letter == 'T' || letter == 't')
{
int truth = (code == NE) == (letter == 'T');
fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
}
else if (CONST_GP_P (op))
fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
else
output_addr_const (file, op);
}
static void
print_operand_reloc (FILE *file, rtx op, const char **relocs)
{
enum mips_symbol_type symbol_type;
const char *p;
rtx base;
HOST_WIDE_INT offset;
if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
mips_split_const (op, &base, &offset);
if (UNSPEC_ADDRESS_P (base))
op = plus_constant (UNSPEC_ADDRESS (base), offset);
fputs (relocs[symbol_type], file);
output_addr_const (file, op);
for (p = relocs[symbol_type]; *p != 0; p++)
if (*p == '(')
fputc (')', file);
}
void
print_operand_address (FILE *file, rtx x)
{
struct mips_address_info addr;
if (mips_classify_address (&addr, x, word_mode, true))
switch (addr.type)
{
case ADDRESS_REG:
print_operand (file, addr.offset, 0);
fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
return;
case ADDRESS_LO_SUM:
print_operand (file, addr.offset, 'R');
fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
return;
case ADDRESS_CONST_INT:
output_addr_const (file, x);
fprintf (file, "(%s)", reg_names[0]);
return;
case ADDRESS_SYMBOLIC:
output_addr_const (file, x);
return;
}
gcc_unreachable ();
}
int
mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
{
register struct extern_list *p;
if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
{
p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
p->next = extern_head;
p->name = name;
p->size = int_size_in_bytes (TREE_TYPE (decl));
extern_head = p;
}
if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
{
p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
p->next = extern_head;
p->name = name;
p->size = -1;
extern_head = p;
}
return 0;
}
#if TARGET_IRIX
static void
irix_output_external_libcall (rtx fun)
{
register struct extern_list *p;
if (mips_abi == ABI_32)
{
p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
p->next = extern_head;
p->name = XSTR (fun, 0);
p->size = -1;
extern_head = p;
}
}
#endif
void
mips_output_filename (FILE *stream, const char *name)
{
if (write_symbols == DWARF2_DEBUG)
return;
else if (mips_output_filename_first_time)
{
mips_output_filename_first_time = 0;
num_source_filenames += 1;
current_function_file = name;
fprintf (stream, "\t.file\t%d ", num_source_filenames);
output_quoted_string (stream, name);
putc ('\n', stream);
}
else if (write_symbols == DBX_DEBUG)
return;
else if (name != current_function_file
&& strcmp (name, current_function_file) != 0)
{
num_source_filenames += 1;
current_function_file = name;
fprintf (stream, "\t.file\t%d ", num_source_filenames);
output_quoted_string (stream, name);
putc ('\n', stream);
}
}
void
mips_output_ascii (FILE *stream, const char *string_param, size_t len,
const char *prefix)
{
size_t i;
int cur_pos = 17;
register const unsigned char *string =
(const unsigned char *)string_param;
fprintf (stream, "%s\"", prefix);
for (i = 0; i < len; i++)
{
register int c = string[i];
if (ISPRINT (c))
{
if (c == '\\' || c == '\"')
{
putc ('\\', stream);
cur_pos++;
}
putc (c, stream);
cur_pos++;
}
else
{
fprintf (stream, "\\%03o", c);
cur_pos += 4;
}
if (cur_pos > 72 && i+1 < len)
{
cur_pos = 17;
fprintf (stream, "\"\n%s\"", prefix);
}
}
fprintf (stream, "\"\n");
}
static void
mips_file_start (void)
{
default_file_start ();
if (!TARGET_IRIX)
{
const char * abi_string = NULL;
switch (mips_abi)
{
case ABI_32: abi_string = "abi32"; break;
case ABI_N32: abi_string = "abiN32"; break;
case ABI_64: abi_string = "abi64"; break;
case ABI_O64: abi_string = "abiO64"; break;
case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
default:
gcc_unreachable ();
}
fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
if (mips_abi == ABI_EABI)
fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
TARGET_LONG64 ? 64 : 32);
fprintf (asm_out_file, "\t.previous\n");
}
if (TARGET_ABICALLS)
fprintf (asm_out_file, "\t.abicalls\n");
if (TARGET_MIPS16)
fprintf (asm_out_file, "\t.set\tmips16\n");
if (flag_verbose_asm)
fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
ASM_COMMENT_START,
mips_section_threshold, mips_arch_info->name, mips_isa);
}
#ifdef BSS_SECTION_ASM_OP
void
mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
unsigned HOST_WIDE_INT size, int align)
{
extern tree last_assemble_variable_decl;
if (mips_in_small_data_p (decl))
named_section (0, ".sbss", 0);
else
bss_section ();
ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
last_assemble_variable_decl = decl;
ASM_DECLARE_OBJECT_NAME (stream, name, decl);
ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
}
#endif
static void
mips_file_end (void)
{
tree name_tree;
struct extern_list *p;
if (extern_head)
{
fputs ("\n", asm_out_file);
for (p = extern_head; p != 0; p = p->next)
{
name_tree = get_identifier (p->name);
if (!TREE_ASM_WRITTEN (name_tree)
&& TREE_SYMBOL_REFERENCED (name_tree))
{
TREE_ASM_WRITTEN (name_tree) = 1;
if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
{
fputs ("\t.globl ", asm_out_file);
assemble_name (asm_out_file, p->name);
fputs (" .text\n", asm_out_file);
}
else
{
fputs ("\t.extern\t", asm_out_file);
assemble_name (asm_out_file, p->name);
fprintf (asm_out_file, ", %d\n", p->size);
}
}
}
}
}
void
mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
unsigned HOST_WIDE_INT size,
unsigned int align)
{
if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
&& TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
&& (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
{
if (TREE_PUBLIC (decl) && DECL_NAME (decl))
targetm.asm_out.globalize_label (stream, name);
readonly_data_section ();
ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
mips_declare_object (stream, name, "",
":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
size);
}
else
mips_declare_common_object (stream, name, "\n\t.comm\t",
size, align, true);
}
void
mips_declare_common_object (FILE *stream, const char *name,
const char *init_string,
unsigned HOST_WIDE_INT size,
unsigned int align, bool takes_alignment_p)
{
if (!takes_alignment_p)
{
size += (align / BITS_PER_UNIT) - 1;
size -= size % (align / BITS_PER_UNIT);
mips_declare_object (stream, name, init_string,
"," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
}
else
mips_declare_object (stream, name, init_string,
"," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
size, align / BITS_PER_UNIT);
}
void
mips_declare_object (FILE *stream, const char *name, const char *init_string,
const char *final_string, ...)
{
va_list ap;
fputs (init_string, stream);
assemble_name (stream, name);
va_start (ap, final_string);
vfprintf (stream, final_string, ap);
va_end (ap);
if (!TARGET_EXPLICIT_RELOCS)
{
tree name_tree = get_identifier (name);
TREE_ASM_WRITTEN (name_tree) = 1;
}
}
#ifdef ASM_OUTPUT_SIZE_DIRECTIVE
extern int size_directive_output;
void
mips_declare_object_name (FILE *stream, const char *name,
tree decl ATTRIBUTE_UNUSED)
{
#ifdef ASM_OUTPUT_TYPE_DIRECTIVE
ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
#endif
size_directive_output = 0;
if (!flag_inhibit_size_directive && DECL_SIZE (decl))
{
HOST_WIDE_INT size;
size_directive_output = 1;
size = int_size_in_bytes (TREE_TYPE (decl));
ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
}
mips_declare_object (stream, name, "", ":\n", 0);
}
void
mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
{
const char *name;
name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
if (!flag_inhibit_size_directive
&& DECL_SIZE (decl) != 0
&& !at_end && top_level
&& DECL_INITIAL (decl) == error_mark_node
&& !size_directive_output)
{
HOST_WIDE_INT size;
size_directive_output = 1;
size = int_size_in_bytes (TREE_TYPE (decl));
ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
}
}
#endif
static bool
mips_rewrite_small_data_p (rtx x)
{
enum mips_symbol_type symbol_type;
return (TARGET_EXPLICIT_RELOCS
&& mips_symbolic_constant_p (x, &symbol_type)
&& symbol_type == SYMBOL_SMALL_DATA);
}
static int
mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
{
if (GET_CODE (*loc) == LO_SUM)
return -1;
return mips_rewrite_small_data_p (*loc);
}
bool
mips_small_data_pattern_p (rtx op)
{
return for_each_rtx (&op, mips_small_data_pattern_1, 0);
}
static int
mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
{
if (mips_rewrite_small_data_p (*loc))
*loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
if (GET_CODE (*loc) == LO_SUM)
return -1;
return 0;
}
rtx
mips_rewrite_small_data (rtx op)
{
op = copy_insn (op);
for_each_rtx (&op, mips_rewrite_small_data_1, 0);
return op;
}
static bool
mips_function_has_gp_insn (void)
{
if (!cfun->machine->has_gp_insn_p)
{
rtx insn;
push_topmost_sequence ();
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
if (INSN_P (insn)
&& GET_CODE (PATTERN (insn)) != USE
&& GET_CODE (PATTERN (insn)) != CLOBBER
&& (get_attr_got (insn) != GOT_UNSET
|| small_data_pattern (PATTERN (insn), VOIDmode)))
break;
pop_topmost_sequence ();
cfun->machine->has_gp_insn_p = (insn != 0);
}
return cfun->machine->has_gp_insn_p;
}
static unsigned int
mips_global_pointer (void)
{
unsigned int regno;
if (!TARGET_ABICALLS)
return GLOBAL_POINTER_REGNUM;
if (!TARGET_EXPLICIT_RELOCS)
return GLOBAL_POINTER_REGNUM;
if (current_function_profile)
return GLOBAL_POINTER_REGNUM;
if (current_function_has_nonlocal_goto)
return GLOBAL_POINTER_REGNUM;
if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
&& !current_function_uses_const_pool
&& !mips_function_has_gp_insn ())
return 0;
if (TARGET_NEWABI && current_function_is_leaf)
for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
if (!regs_ever_live[regno]
&& call_used_regs[regno]
&& !fixed_regs[regno]
&& regno != PIC_FUNCTION_ADDR_REGNUM)
return regno;
return GLOBAL_POINTER_REGNUM;
}
static bool
mips_save_reg_p (unsigned int regno)
{
if (regno == GLOBAL_POINTER_REGNUM)
return (TARGET_ABICALLS && TARGET_NEWABI
&& cfun->machine->global_pointer == regno);
if (regs_ever_live[regno] && !call_used_regs[regno])
return true;
if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
return true;
if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
return true;
if (TARGET_MIPS16)
{
tree return_type;
return_type = DECL_RESULT (current_function_decl);
if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
return true;
if (regno == GP_REG_FIRST + 31
&& mips16_hard_float
&& !aggregate_value_p (return_type, current_function_decl)
&& GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
&& GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
return true;
}
return false;
}
HOST_WIDE_INT
compute_frame_size (HOST_WIDE_INT size)
{
unsigned int regno;
HOST_WIDE_INT total_size;
HOST_WIDE_INT var_size;
HOST_WIDE_INT args_size;
HOST_WIDE_INT cprestore_size;
HOST_WIDE_INT gp_reg_rounded;
HOST_WIDE_INT gp_reg_size;
HOST_WIDE_INT fp_reg_size;
unsigned int mask;
unsigned int fmask;
cfun->machine->global_pointer = mips_global_pointer ();
gp_reg_size = 0;
fp_reg_size = 0;
mask = 0;
fmask = 0;
var_size = MIPS_STACK_ALIGN (size);
args_size = current_function_outgoing_args_size;
cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
if (var_size == 0 && current_function_is_leaf)
cprestore_size = args_size = 0;
if (args_size == 0 && current_function_calls_alloca)
args_size = 4 * UNITS_PER_WORD;
total_size = var_size + args_size + cprestore_size;
for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
if (mips_save_reg_p (regno))
{
gp_reg_size += GET_MODE_SIZE (gpr_mode);
mask |= 1 << (regno - GP_REG_FIRST);
}
if (current_function_calls_eh_return)
{
unsigned int i;
for (i = 0; ; ++i)
{
regno = EH_RETURN_DATA_REGNO (i);
if (regno == INVALID_REGNUM)
break;
gp_reg_size += GET_MODE_SIZE (gpr_mode);
mask |= 1 << (regno - GP_REG_FIRST);
}
}
for (regno = (FP_REG_LAST - FP_INC + 1);
regno >= FP_REG_FIRST;
regno -= FP_INC)
{
if (mips_save_reg_p (regno))
{
fp_reg_size += FP_INC * UNITS_PER_FPREG;
fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
}
}
gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
if (!TARGET_OLDABI)
total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
cfun->machine->frame.total_size = total_size;
cfun->machine->frame.var_size = var_size;
cfun->machine->frame.args_size = args_size;
cfun->machine->frame.cprestore_size = cprestore_size;
cfun->machine->frame.gp_reg_size = gp_reg_size;
cfun->machine->frame.fp_reg_size = fp_reg_size;
cfun->machine->frame.mask = mask;
cfun->machine->frame.fmask = fmask;
cfun->machine->frame.initialized = reload_completed;
cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
if (mask)
{
HOST_WIDE_INT offset;
offset = (args_size + cprestore_size + var_size
+ gp_reg_size - GET_MODE_SIZE (gpr_mode));
cfun->machine->frame.gp_sp_offset = offset;
cfun->machine->frame.gp_save_offset = offset - total_size;
}
else
{
cfun->machine->frame.gp_sp_offset = 0;
cfun->machine->frame.gp_save_offset = 0;
}
if (fmask)
{
HOST_WIDE_INT offset;
offset = (args_size + cprestore_size + var_size
+ gp_reg_rounded + fp_reg_size
- FP_INC * UNITS_PER_FPREG);
cfun->machine->frame.fp_sp_offset = offset;
cfun->machine->frame.fp_save_offset = offset - total_size;
}
else
{
cfun->machine->frame.fp_sp_offset = 0;
cfun->machine->frame.fp_save_offset = 0;
}
return total_size;
}
HOST_WIDE_INT
mips_initial_elimination_offset (int from, int to)
{
HOST_WIDE_INT offset;
compute_frame_size (get_frame_size ());
switch (from)
{
case FRAME_POINTER_REGNUM:
offset = 0;
break;
case ARG_POINTER_REGNUM:
offset = cfun->machine->frame.total_size;
if (TARGET_NEWABI)
offset -= current_function_pretend_args_size;
break;
default:
gcc_unreachable ();
}
if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
offset -= cfun->machine->frame.args_size;
return offset;
}
rtx
mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
{
if (count != 0)
return const0_rtx;
return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
}
static void
mips_save_restore_reg (enum machine_mode mode, int regno,
HOST_WIDE_INT offset, mips_save_restore_fn fn)
{
rtx mem;
mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
fn (gen_rtx_REG (mode, regno), mem);
}
static void
mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
{
#define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
enum machine_mode fpr_mode;
HOST_WIDE_INT offset;
int regno;
offset = cfun->machine->frame.gp_sp_offset - sp_offset;
for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
{
mips_save_restore_reg (gpr_mode, regno, offset, fn);
offset -= GET_MODE_SIZE (gpr_mode);
}
offset = cfun->machine->frame.fp_sp_offset - sp_offset;
fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
for (regno = (FP_REG_LAST - FP_INC + 1);
regno >= FP_REG_FIRST;
regno -= FP_INC)
if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
{
mips_save_restore_reg (fpr_mode, regno, offset, fn);
offset -= GET_MODE_SIZE (fpr_mode);
}
#undef BITSET_P
}
static void
mips_output_cplocal (void)
{
if (!TARGET_EXPLICIT_RELOCS
&& cfun->machine->global_pointer > 0
&& cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
output_asm_insn (".cplocal %+", 0);
}
static void
mips_emit_loadgp (void)
{
if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
{
rtx addr, offset, incoming_address;
addr = XEXP (DECL_RTL (current_function_decl), 0);
offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
emit_insn (gen_loadgp (offset, incoming_address));
if (!TARGET_EXPLICIT_RELOCS)
emit_insn (gen_loadgp_blockage ());
}
}
static void
mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
{
const char *fnname;
HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
#ifdef SDB_DEBUGGING_INFO
if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
#endif
if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
&& current_function_args_info.fp_code != 0)
build_mips16_function_stub (file);
if (!FUNCTION_NAME_ALREADY_DECLARED)
{
fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
if (!flag_inhibit_size_directive)
{
fputs ("\t.ent\t", file);
assemble_name (file, fnname);
fputs ("\n", file);
}
assemble_name (file, fnname);
fputs (":\n", file);
}
if (TARGET_IRIX && mips_abi == ABI_32)
TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
if (!flag_inhibit_size_directive)
{
fprintf (file,
"\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
"# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
", args= " HOST_WIDE_INT_PRINT_DEC
", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
(reg_names[(frame_pointer_needed)
? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
((frame_pointer_needed && TARGET_MIPS16)
? tsize - cfun->machine->frame.args_size
: tsize),
reg_names[GP_REG_FIRST + 31],
cfun->machine->frame.var_size,
cfun->machine->frame.num_gp,
cfun->machine->frame.num_fp,
cfun->machine->frame.args_size,
cfun->machine->frame.cprestore_size);
fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
cfun->machine->frame.mask,
cfun->machine->frame.gp_save_offset);
fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
cfun->machine->frame.fmask,
cfun->machine->frame.fp_save_offset);
}
if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
{
if (!cfun->machine->all_noreorder_p)
output_asm_insn ("%(.cpload\t%^%)", 0);
else
output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
}
else if (cfun->machine->all_noreorder_p)
output_asm_insn ("%(%<", 0);
mips_output_cplocal ();
}
static void
mips_set_frame_expr (rtx frame_pattern)
{
rtx insn;
insn = get_last_insn ();
RTX_FRAME_RELATED_P (insn) = 1;
REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
frame_pattern,
REG_NOTES (insn));
}
static rtx
mips_frame_set (rtx mem, rtx reg)
{
rtx set;
if (REGNO (reg) == GP_REG_FIRST + 31
&& DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
set = gen_rtx_SET (VOIDmode, mem, reg);
RTX_FRAME_RELATED_P (set) = 1;
return set;
}
static void
mips_save_reg (rtx reg, rtx mem)
{
if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
{
rtx x1, x2;
if (mips_split_64bit_move_p (mem, reg))
mips_split_64bit_move (mem, reg);
else
emit_move_insn (mem, reg);
x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
}
else
{
if (TARGET_MIPS16
&& REGNO (reg) != GP_REG_FIRST + 31
&& !M16_REG_P (REGNO (reg)))
{
emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
}
else
emit_move_insn (mem, reg);
mips_set_frame_expr (mips_frame_set (mem, reg));
}
}
void
mips_expand_prologue (void)
{
HOST_WIDE_INT size;
if (cfun->machine->global_pointer > 0)
REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
size = compute_frame_size (get_frame_size ());
if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
{
HOST_WIDE_INT step1;
step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
stack_pointer_rtx,
GEN_INT (-step1)))) = 1;
size -= step1;
mips_for_each_saved_reg (size, mips_save_reg);
}
if (size > 0)
{
if (SMALL_OPERAND (-size))
RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
stack_pointer_rtx,
GEN_INT (-size)))) = 1;
else
{
emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
if (TARGET_MIPS16)
{
gcc_assert (frame_pointer_needed);
emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
hard_frame_pointer_rtx,
MIPS_PROLOGUE_TEMP (Pmode)));
emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
}
else
emit_insn (gen_sub3_insn (stack_pointer_rtx,
stack_pointer_rtx,
MIPS_PROLOGUE_TEMP (Pmode)));
mips_set_frame_expr
(gen_rtx_SET (VOIDmode, stack_pointer_rtx,
plus_constant (stack_pointer_rtx, -size)));
}
}
if (frame_pointer_needed)
{
if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
{
rtx offset = GEN_INT (cfun->machine->frame.args_size);
RTX_FRAME_RELATED_P
(emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
stack_pointer_rtx,
offset))) = 1;
}
else
RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
stack_pointer_rtx)) = 1;
}
if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
mips_emit_loadgp ();
if (current_function_profile)
emit_insn (gen_blockage ());
}
#define RA_MASK BITMASK_HIGH
static void
mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
HOST_WIDE_INT size ATTRIBUTE_UNUSED)
{
REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
mips_output_cplocal ();
if (cfun->machine->all_noreorder_p)
{
output_asm_insn (".set\tmacro", 0);
output_asm_insn (".set\treorder", 0);
set_noreorder = set_nomacro = 0;
}
if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
{
const char *fnname;
fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
fputs ("\t.end\t", file);
assemble_name (file, fnname);
fputs ("\n", file);
}
}
static void
mips_restore_reg (rtx reg, rtx mem)
{
if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
reg = gen_rtx_REG (GET_MODE (reg), 7);
if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
{
emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
}
else
emit_move_insn (reg, mem);
}
void
mips_expand_epilogue (int sibcall_p)
{
HOST_WIDE_INT step1, step2;
rtx base, target;
if (!sibcall_p && mips_can_use_return_insn ())
{
emit_jump_insn (gen_return ());
return;
}
step1 = cfun->machine->frame.total_size;
step2 = 0;
if (!frame_pointer_needed)
base = stack_pointer_rtx;
else
{
base = hard_frame_pointer_rtx;
if (TARGET_MIPS16)
step1 -= cfun->machine->frame.args_size;
}
if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
{
step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
step1 -= step2;
}
target = base;
if (step1 > 0)
{
rtx adjust;
adjust = GEN_INT (step1);
if (!SMALL_OPERAND (step1))
{
emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
adjust = MIPS_EPILOGUE_TEMP (Pmode);
}
if (!TARGET_MIPS16)
target = stack_pointer_rtx;
emit_insn (gen_add3_insn (target, base, adjust));
}
if (target != stack_pointer_rtx)
emit_move_insn (stack_pointer_rtx, target);
if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
emit_insn (gen_blockage ());
mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
mips_restore_reg);
if (step2 > 0)
emit_insn (gen_add3_insn (stack_pointer_rtx,
stack_pointer_rtx,
GEN_INT (step2)));
if (current_function_calls_eh_return)
{
if (TARGET_MIPS16)
{
emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
MIPS_EPILOGUE_TEMP (Pmode),
EH_RETURN_STACKADJ_RTX));
emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
}
else
emit_insn (gen_add3_insn (stack_pointer_rtx,
stack_pointer_rtx,
EH_RETURN_STACKADJ_RTX));
}
if (!sibcall_p)
{
if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
GP_REG_FIRST + 7)));
else
emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
GP_REG_FIRST + 31)));
}
}
int
mips_can_use_return_insn (void)
{
tree return_type;
if (! reload_completed)
return 0;
if (regs_ever_live[31] || current_function_profile)
return 0;
return_type = DECL_RESULT (current_function_decl);
if (TARGET_MIPS16
&& mips16_hard_float
&& ! aggregate_value_p (return_type, current_function_decl)
&& GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
&& GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
return 0;
if (cfun->machine->frame.initialized)
return cfun->machine->frame.total_size == 0;
return compute_frame_size (get_frame_size ()) == 0;
}
static void
mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
tree function)
{
rtx this, temp1, temp2, insn, fnaddr;
no_new_pseudos = 1;
reload_completed = 1;
reset_block_changes ();
if (TARGET_ABICALLS)
cfun->machine->global_pointer
= REGNO (pic_offset_table_rtx)
= TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
mips_emit_loadgp ();
temp1 = gen_rtx_REG (Pmode, 2);
temp2 = gen_rtx_REG (Pmode, 3);
if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
else
this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
if (delta != 0)
{
rtx offset = GEN_INT (delta);
if (!SMALL_OPERAND (delta))
{
emit_move_insn (temp1, offset);
offset = temp1;
}
emit_insn (gen_add3_insn (this, this, offset));
}
if (vcall_offset != 0)
{
rtx addr;
emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
addr = mips_add_offset (temp2, temp1, vcall_offset);
emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
emit_insn (gen_add3_insn (this, this, temp1));
}
fnaddr = XEXP (DECL_RTL (function), 0);
if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
{
if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
mips_load_call_address (temp1, fnaddr, true);
if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
emit_jump_insn (gen_indirect_jump (temp1));
}
else
{
insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
SIBLING_CALL_P (insn) = 1;
}
insn = get_insns ();
insn_locators_initialize ();
split_all_insns_noflow ();
if (TARGET_MIPS16)
mips16_lay_out_constants ();
shorten_branches (insn);
final_start_function (insn, file, 1);
final (insn, file, 1, 0);
final_end_function ();
reload_completed = 0;
no_new_pseudos = 0;
}
static int
symbolic_expression_p (rtx x)
{
if (GET_CODE (x) == SYMBOL_REF)
return 1;
if (GET_CODE (x) == CONST)
return symbolic_expression_p (XEXP (x, 0));
if (UNARY_P (x))
return symbolic_expression_p (XEXP (x, 0));
if (ARITHMETIC_P (x))
return (symbolic_expression_p (XEXP (x, 0))
|| symbolic_expression_p (XEXP (x, 1)));
return 0;
}
static void
mips_select_rtx_section (enum machine_mode mode, rtx x,
unsigned HOST_WIDE_INT align)
{
if (TARGET_MIPS16)
{
function_section (current_function_decl);
}
else if (TARGET_EMBEDDED_DATA)
{
mergeable_constant_section (mode, align, 0);
}
else
{
if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
&& mips_section_threshold > 0)
named_section (0, ".sdata", 0);
else if (flag_pic && symbolic_expression_p (x))
named_section (0, ".data.rel.ro", 3);
else
mergeable_constant_section (mode, align, 0);
}
}
static void
mips_function_rodata_section (tree decl)
{
if (!TARGET_ABICALLS || TARGET_GPWORD)
default_function_rodata_section (decl);
else if (decl && DECL_SECTION_NAME (decl))
{
const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
{
char *rname = ASTRDUP (name);
rname[14] = 'd';
named_section_real (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
}
else if (flag_function_sections && flag_data_sections
&& strncmp (name, ".text.", 6) == 0)
{
char *rname = ASTRDUP (name);
memcpy (rname + 1, "data", 4);
named_section_flags (rname, SECTION_WRITE);
}
else
data_section ();
}
else
data_section ();
}
static bool
mips_in_small_data_p (tree decl)
{
HOST_WIDE_INT size;
if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
return false;
if (TARGET_ABICALLS)
return false;
if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
{
const char *name;
name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
return false;
if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
return true;
}
else if (TARGET_EMBEDDED_DATA)
{
if (TREE_CODE (decl) != VAR_DECL)
return false;
if (TREE_READONLY (decl)
&& !TREE_SIDE_EFFECTS (decl)
&& (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
return false;
}
size = int_size_in_bytes (TREE_TYPE (decl));
return (size > 0 && size <= mips_section_threshold);
}
static int
mips_fpr_return_fields (tree valtype, tree *fields)
{
tree field;
int i;
if (!TARGET_NEWABI)
return 0;
if (TREE_CODE (valtype) != RECORD_TYPE)
return 0;
i = 0;
for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
{
if (TREE_CODE (field) != FIELD_DECL)
continue;
if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
return 0;
if (i == 2)
return 0;
fields[i++] = field;
}
return i;
}
static bool
mips_return_in_msb (tree valtype)
{
tree fields[2];
return (TARGET_NEWABI
&& TARGET_BIG_ENDIAN
&& AGGREGATE_TYPE_P (valtype)
&& mips_fpr_return_fields (valtype, fields) == 0);
}
static rtx
mips_return_fpr_pair (enum machine_mode mode,
enum machine_mode mode1, HOST_WIDE_INT offset1,
enum machine_mode mode2, HOST_WIDE_INT offset2)
{
int inc;
inc = (TARGET_NEWABI ? 2 : FP_INC);
return gen_rtx_PARALLEL
(mode,
gen_rtvec (2,
gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_REG (mode1, FP_RETURN),
GEN_INT (offset1)),
gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_REG (mode2, FP_RETURN + inc),
GEN_INT (offset2))));
}
rtx
mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
enum machine_mode mode)
{
if (valtype)
{
tree fields[2];
int unsignedp;
mode = TYPE_MODE (valtype);
unsignedp = TYPE_UNSIGNED (valtype);
mode = promote_mode (valtype, mode, &unsignedp, 1);
switch (mips_fpr_return_fields (valtype, fields))
{
case 1:
return gen_rtx_REG (mode, FP_RETURN);
case 2:
return mips_return_fpr_pair (mode,
TYPE_MODE (TREE_TYPE (fields[0])),
int_byte_position (fields[0]),
TYPE_MODE (TREE_TYPE (fields[1])),
int_byte_position (fields[1]));
}
if (mips_return_in_msb (valtype))
{
HOST_WIDE_INT size = int_size_in_bytes (valtype);
if (size % UNITS_PER_WORD != 0)
{
size += UNITS_PER_WORD - size % UNITS_PER_WORD;
mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
}
}
if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
return gen_rtx_REG (mode, GP_RETURN);
}
if ((GET_MODE_CLASS (mode) == MODE_FLOAT
|| GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
&& GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
return gen_rtx_REG (mode, FP_RETURN);
if (mode == TFmode)
return mips_return_fpr_pair (mode,
DImode, 0,
DImode, GET_MODE_SIZE (mode) / 2);
if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
&& GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
return mips_return_fpr_pair (mode,
GET_MODE_INNER (mode), 0,
GET_MODE_INNER (mode),
GET_MODE_SIZE (mode) / 2);
return gen_rtx_REG (mode, GP_RETURN);
}
static bool
mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
enum machine_mode mode, tree type,
bool named ATTRIBUTE_UNUSED)
{
if (mips_abi == ABI_EABI)
{
int size;
if (type == NULL_TREE || mode == DImode || mode == DFmode)
return 0;
size = int_size_in_bytes (type);
return size == -1 || size > UNITS_PER_WORD;
}
else
{
return targetm.calls.must_pass_in_stack (mode, type);
}
}
static bool
mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
enum machine_mode mode ATTRIBUTE_UNUSED,
tree type ATTRIBUTE_UNUSED, bool named)
{
return mips_abi == ABI_EABI && named;
}
bool
mips_cannot_change_mode_class (enum machine_mode from,
enum machine_mode to, enum reg_class class)
{
if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
&& MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
{
if (TARGET_BIG_ENDIAN)
{
if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
return true;
}
else
{
if (reg_classes_intersect_p (HI_REG, class))
return true;
}
}
if (TARGET_FLOAT64
&& from == SImode
&& GET_MODE_SIZE (to) >= UNITS_PER_WORD
&& reg_classes_intersect_p (FP_REGS, class))
return true;
return false;
}
bool
mips_dangerous_for_la25_p (rtx x)
{
HOST_WIDE_INT offset;
if (TARGET_EXPLICIT_RELOCS)
return false;
mips_split_const (x, &x, &offset);
return global_got_operand (x, VOIDmode);
}
enum reg_class
mips_preferred_reload_class (rtx x, enum reg_class class)
{
if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
return LEA_REGS;
if (TARGET_HARD_FLOAT
&& FLOAT_MODE_P (GET_MODE (x))
&& reg_class_subset_p (FP_REGS, class))
return FP_REGS;
if (reg_class_subset_p (GR_REGS, class))
class = GR_REGS;
if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
class = M16_REGS;
return class;
}
enum reg_class
mips_secondary_reload_class (enum reg_class class,
enum machine_mode mode, rtx x, int in_p)
{
enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
int regno = -1;
int gp_reg_p;
if (REG_P (x)|| GET_CODE (x) == SUBREG)
regno = true_regnum (x);
gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
if (mips_dangerous_for_la25_p (x))
{
gr_regs = LEA_REGS;
if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
return gr_regs;
}
if (class == HI_REG || class == LO_REG || class == MD_REGS)
{
if (TARGET_MIPS16 && in_p)
{
return M16_REGS;
}
return gp_reg_p ? NO_REGS : gr_regs;
}
if (MD_REG_P (regno))
{
if (TARGET_MIPS16 && ! in_p)
{
return M16_REGS;
}
return class == gr_regs ? NO_REGS : gr_regs;
}
if (class == ST_REGS)
{
if (in_p)
return FP_REGS;
return gp_reg_p ? NO_REGS : gr_regs;
}
if (ST_REG_P (regno))
{
if (! in_p)
return FP_REGS;
return class == gr_regs ? NO_REGS : gr_regs;
}
if (class == FP_REGS)
{
if (MEM_P (x))
{
return NO_REGS;
}
else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
{
return NO_REGS;
}
else if (gp_reg_p || x == CONST0_RTX (mode))
{
return NO_REGS;
}
else if (FP_REG_P (regno))
{
return NO_REGS;
}
else
{
return gr_regs;
}
}
if (TARGET_MIPS16)
{
if (class != M16_REGS && class != M16_NA_REGS)
{
if (gp_reg_p)
return NO_REGS;
return M16_REGS;
}
if (! gp_reg_p)
{
if (class == M16_REGS || class == M16_NA_REGS)
return NO_REGS;
return M16_REGS;
}
}
return NO_REGS;
}
int
mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
enum machine_mode mode)
{
if (class == ST_REGS)
return (GET_MODE_SIZE (mode) + 3) / 4;
else
return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
}
static bool
mips_valid_pointer_mode (enum machine_mode mode)
{
return (mode == SImode || (TARGET_64BIT && mode == DImode));
}
static bool
mips_scalar_mode_supported_p (enum machine_mode mode)
{
switch (mode)
{
case QImode:
case HImode:
case SImode:
case DImode:
return true;
case TImode:
return TARGET_64BIT;
case SFmode:
case DFmode:
return true;
case TFmode:
return TARGET_NEWABI;
default:
return false;
}
}
static bool
mips_vector_mode_supported_p (enum machine_mode mode)
{
if (mode == V2SFmode && TARGET_PAIRED_SINGLE_FLOAT)
return true;
else
return false;
}
static rtx
mips16_gp_pseudo_reg (void)
{
if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
{
rtx unspec;
rtx insn, scan;
cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
start_sequence ();
unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
gen_rtx_CONST (Pmode, unspec));
insn = get_insns ();
end_sequence ();
push_topmost_sequence ();
for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
if (NOTE_P (scan)
&& NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
break;
if (scan == NULL_RTX)
scan = get_insns ();
insn = emit_insn_after (insn, scan);
pop_topmost_sequence ();
}
return cfun->machine->mips16_gp_pseudo_rtx;
}
static void
mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
{
const char *s;
int gparg, fparg;
unsigned int f;
gcc_assert (TARGET_OLDABI);
if (from_fp_p)
s = "mfc1";
else
s = "mtc1";
gparg = GP_ARG_FIRST;
fparg = FP_ARG_FIRST;
for (f = (unsigned int) fp_code; f != 0; f >>= 2)
{
if ((f & 3) == 1)
{
if ((fparg & 1) != 0)
++fparg;
fprintf (file, "\t%s\t%s,%s\n", s,
reg_names[gparg], reg_names[fparg]);
}
else if ((f & 3) == 2)
{
if (TARGET_64BIT)
fprintf (file, "\td%s\t%s,%s\n", s,
reg_names[gparg], reg_names[fparg]);
else
{
if ((fparg & 1) != 0)
++fparg;
if (TARGET_BIG_ENDIAN)
fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
reg_names[gparg], reg_names[fparg + 1], s,
reg_names[gparg + 1], reg_names[fparg]);
else
fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
reg_names[gparg], reg_names[fparg], s,
reg_names[gparg + 1], reg_names[fparg + 1]);
++gparg;
++fparg;
}
}
else
gcc_unreachable ();
++gparg;
++fparg;
}
}
static void
build_mips16_function_stub (FILE *file)
{
const char *fnname;
char *secname, *stubname;
tree stubid, stubdecl;
int need_comma;
unsigned int f;
fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
secname = (char *) alloca (strlen (fnname) + 20);
sprintf (secname, ".mips16.fn.%s", fnname);
stubname = (char *) alloca (strlen (fnname) + 20);
sprintf (stubname, "__fn_stub_%s", fnname);
stubid = get_identifier (stubname);
stubdecl = build_decl (FUNCTION_DECL, stubid,
build_function_type (void_type_node, NULL_TREE));
DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
fprintf (file, "\t# Stub function for %s (", current_function_name ());
need_comma = 0;
for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
{
fprintf (file, "%s%s",
need_comma ? ", " : "",
(f & 3) == 1 ? "float" : "double");
need_comma = 1;
}
fprintf (file, ")\n");
fprintf (file, "\t.set\tnomips16\n");
function_section (stubdecl);
ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
if (!FUNCTION_NAME_ALREADY_DECLARED)
{
fputs ("\t.ent\t", file);
assemble_name (file, stubname);
fputs ("\n", file);
}
assemble_name (file, stubname);
fputs (":\n", file);
fprintf (file, "\t.set\tnoreorder\n");
mips16_fp_args (file, current_function_args_info.fp_code, 1);
fprintf (asm_out_file, "\t.set\tnoat\n");
fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
assemble_name (file, fnname);
fprintf (file, "\n");
fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
fprintf (asm_out_file, "\t.set\tat\n");
fprintf (file, "\tnop\n");
fprintf (file, "\t.set\treorder\n");
if (!FUNCTION_NAME_ALREADY_DECLARED)
{
fputs ("\t.end\t", file);
assemble_name (file, stubname);
fputs ("\n", file);
}
fprintf (file, "\t.set\tmips16\n");
function_section (current_function_decl);
}
struct mips16_stub
{
struct mips16_stub *next;
char *name;
int fpret;
};
static struct mips16_stub *mips16_stubs;
int
build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
{
int fpret;
const char *fnname;
char *secname, *stubname;
struct mips16_stub *l;
tree stubid, stubdecl;
int need_comma;
unsigned int f;
if (! TARGET_MIPS16 || ! mips16_hard_float)
return 0;
fpret = (retval != 0
&& GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
&& GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
if (fp_code == 0 && ! fpret)
return 0;
if (GET_CODE (fn) == SYMBOL_REF
&& strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
return 0;
gcc_assert (TARGET_OLDABI);
if (fpret)
gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
if (GET_CODE (fn) != SYMBOL_REF)
{
char buf[30];
tree id;
rtx stub_fn, insn;
sprintf (buf, "__mips16_call_stub_%s%d",
(fpret
? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
: ""),
fp_code);
id = get_identifier (buf);
stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
if (retval == NULL_RTX)
insn = gen_call_internal (stub_fn, arg_size);
else
insn = gen_call_value_internal (retval, stub_fn, arg_size);
insn = emit_call_insn (insn);
CALL_INSN_FUNCTION_USAGE (insn) =
gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
CALL_INSN_FUNCTION_USAGE (insn));
if (fpret)
CALL_INSN_FUNCTION_USAGE (insn) =
gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_USE (VOIDmode,
gen_rtx_REG (word_mode, 18)),
CALL_INSN_FUNCTION_USAGE (insn));
return 1;
}
fnname = XSTR (fn, 0);
for (l = mips16_stubs; l != NULL; l = l->next)
if (strcmp (l->name, fnname) == 0)
break;
if (l == NULL)
{
secname = (char *) alloca (strlen (fnname) + 40);
sprintf (secname, ".mips16.call.%s%s",
fpret ? "fp." : "",
fnname);
stubname = (char *) alloca (strlen (fnname) + 20);
sprintf (stubname, "__call_stub_%s%s",
fpret ? "fp_" : "",
fnname);
stubid = get_identifier (stubname);
stubdecl = build_decl (FUNCTION_DECL, stubid,
build_function_type (void_type_node, NULL_TREE));
DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
fprintf (asm_out_file, "\t# Stub function to call %s%s (",
(fpret
? (GET_MODE (retval) == SFmode ? "float " : "double ")
: ""),
fnname);
need_comma = 0;
for (f = (unsigned int) fp_code; f != 0; f >>= 2)
{
fprintf (asm_out_file, "%s%s",
need_comma ? ", " : "",
(f & 3) == 1 ? "float" : "double");
need_comma = 1;
}
fprintf (asm_out_file, ")\n");
fprintf (asm_out_file, "\t.set\tnomips16\n");
assemble_start_function (stubdecl, stubname);
if (!FUNCTION_NAME_ALREADY_DECLARED)
{
fputs ("\t.ent\t", asm_out_file);
assemble_name (asm_out_file, stubname);
fputs ("\n", asm_out_file);
assemble_name (asm_out_file, stubname);
fputs (":\n", asm_out_file);
}
fprintf (asm_out_file, "\t.set\tnoreorder\n");
mips16_fp_args (asm_out_file, fp_code, 0);
if (! fpret)
{
fprintf (asm_out_file, "\t.set\tnoat\n");
fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
fnname);
fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
fprintf (asm_out_file, "\t.set\tat\n");
fprintf (asm_out_file, "\tnop\n");
}
else
{
fprintf (asm_out_file, "\tmove\t%s,%s\n",
reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
fprintf (asm_out_file, "\tjal\t%s\n", fnname);
fprintf (asm_out_file, "\tnop\n");
if (GET_MODE (retval) == SFmode)
fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
else
{
if (TARGET_BIG_ENDIAN)
{
fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
reg_names[GP_REG_FIRST + 2],
reg_names[FP_REG_FIRST + 1]);
fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
reg_names[GP_REG_FIRST + 3],
reg_names[FP_REG_FIRST + 0]);
}
else
{
fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
reg_names[GP_REG_FIRST + 2],
reg_names[FP_REG_FIRST + 0]);
fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
reg_names[GP_REG_FIRST + 3],
reg_names[FP_REG_FIRST + 1]);
}
}
fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
fprintf (asm_out_file, "\tnop\n");
}
fprintf (asm_out_file, "\t.set\treorder\n");
#ifdef ASM_DECLARE_FUNCTION_SIZE
ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
#endif
if (!FUNCTION_NAME_ALREADY_DECLARED)
{
fputs ("\t.end\t", asm_out_file);
assemble_name (asm_out_file, stubname);
fputs ("\n", asm_out_file);
}
fprintf (asm_out_file, "\t.set\tmips16\n");
l = (struct mips16_stub *) xmalloc (sizeof *l);
l->name = xstrdup (fnname);
l->fpret = fpret;
l->next = mips16_stubs;
mips16_stubs = l;
}
if (fpret && ! l->fpret)
error ("cannot handle inconsistent calls to %qs", fnname);
if (l->fpret)
{
rtx insn;
if (retval == NULL_RTX)
insn = gen_call_internal (fn, arg_size);
else
insn = gen_call_value_internal (retval, fn, arg_size);
insn = emit_call_insn (insn);
CALL_INSN_FUNCTION_USAGE (insn) =
gen_rtx_EXPR_LIST (VOIDmode,
gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
CALL_INSN_FUNCTION_USAGE (insn));
return 1;
}
return 0;
}
struct mips16_constant {
struct mips16_constant *next;
rtx value;
rtx label;
enum machine_mode mode;
};
struct mips16_constant_pool {
struct mips16_constant *first;
int highest_address;
int insn_address;
};
static rtx
add_constant (struct mips16_constant_pool *pool,
rtx value, enum machine_mode mode)
{
struct mips16_constant **p, *c;
bool first_of_size_p;
first_of_size_p = true;
for (p = &pool->first; *p != 0; p = &(*p)->next)
{
if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
return (*p)->label;
if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
break;
if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
first_of_size_p = false;
}
if (pool->first == 0)
pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
pool->highest_address -= GET_MODE_SIZE (mode);
if (first_of_size_p)
pool->highest_address -= GET_MODE_SIZE (mode) - 1;
c = (struct mips16_constant *) xmalloc (sizeof *c);
c->value = value;
c->mode = mode;
c->label = gen_label_rtx ();
c->next = *p;
*p = c;
return c->label;
}
static rtx
dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
{
switch (GET_MODE_CLASS (mode))
{
case MODE_INT:
{
rtx size = GEN_INT (GET_MODE_SIZE (mode));
return emit_insn_after (gen_consttable_int (value, size), insn);
}
case MODE_FLOAT:
return emit_insn_after (gen_consttable_float (value), insn);
case MODE_VECTOR_FLOAT:
case MODE_VECTOR_INT:
{
int i;
for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
insn = dump_constants_1 (GET_MODE_INNER (mode),
CONST_VECTOR_ELT (value, i), insn);
return insn;
}
default:
gcc_unreachable ();
}
}
static void
dump_constants (struct mips16_constant *constants, rtx insn)
{
struct mips16_constant *c, *next;
int align;
align = 0;
for (c = constants; c != NULL; c = next)
{
if (align < GET_MODE_SIZE (c->mode))
{
int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
}
align = GET_MODE_SIZE (c->mode);
insn = emit_label_after (c->label, insn);
insn = dump_constants_1 (c->mode, c->value, insn);
next = c->next;
free (c);
}
emit_barrier_after (insn);
}
static int
mips16_insn_length (rtx insn)
{
if (JUMP_P (insn))
{
rtx body = PATTERN (insn);
if (GET_CODE (body) == ADDR_VEC)
return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
if (GET_CODE (body) == ADDR_DIFF_VEC)
return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
}
return get_attr_length (insn);
}
static int
mips16_rewrite_pool_refs (rtx *x, void *data)
{
struct mips16_constant_pool *pool = data;
if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
*x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
get_pool_constant (*x),
get_pool_mode (*x)));
return 0;
}
static void
mips16_lay_out_constants (void)
{
struct mips16_constant_pool pool;
rtx insn, barrier;
barrier = 0;
memset (&pool, 0, sizeof (pool));
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{
if (INSN_P (insn))
for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
pool.insn_address += mips16_insn_length (insn);
if (pool.first != NULL)
{
if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
{
rtx label, jump;
label = gen_label_rtx ();
jump = emit_jump_insn_before (gen_jump (label), insn);
JUMP_LABEL (jump) = label;
LABEL_NUSES (label) = 1;
barrier = emit_barrier_after (jump);
emit_label_after (label, barrier);
pool.insn_address += 4;
}
if (pool.insn_address > pool.highest_address)
{
dump_constants (pool.first, barrier);
pool.first = NULL;
barrier = 0;
}
else if (BARRIER_P (insn))
barrier = insn;
}
}
dump_constants (pool.first, get_last_insn ());
}
static rtx mips_sim_insn;
struct mips_sim {
unsigned int issue_rate;
unsigned int time;
unsigned int insns_left;
struct {
rtx insn;
unsigned int time;
} last_set[FIRST_PSEUDO_REGISTER];
state_t dfa_state;
};
static void
mips_sim_reset (struct mips_sim *state)
{
state->time = 0;
state->insns_left = state->issue_rate;
memset (&state->last_set, 0, sizeof (state->last_set));
state_reset (state->dfa_state);
}
static void
mips_sim_init (struct mips_sim *state, state_t dfa_state)
{
state->issue_rate = mips_issue_rate ();
state->dfa_state = dfa_state;
mips_sim_reset (state);
}
static void
mips_sim_next_cycle (struct mips_sim *state)
{
state->time++;
state->insns_left = state->issue_rate;
state_transition (state->dfa_state, 0);
}
static void
mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
{
unsigned int i;
for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
if (state->last_set[REGNO (reg) + i].insn != 0)
{
unsigned int t;
t = state->last_set[REGNO (reg) + i].time;
t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
while (state->time < t)
mips_sim_next_cycle (state);
}
}
static int
mips_sim_wait_regs_2 (rtx *x, void *data)
{
if (REG_P (*x))
mips_sim_wait_reg (data, mips_sim_insn, *x);
return 0;
}
static void
mips_sim_wait_regs_1 (rtx *x, void *data)
{
for_each_rtx (x, mips_sim_wait_regs_2, data);
}
static void
mips_sim_wait_regs (struct mips_sim *state, rtx insn)
{
mips_sim_insn = insn;
note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
}
static void
mips_sim_wait_units (struct mips_sim *state, rtx insn)
{
state_t tmp_state;
tmp_state = alloca (state_size ());
while (state->insns_left == 0
|| (memcpy (tmp_state, state->dfa_state, state_size ()),
state_transition (tmp_state, insn) >= 0))
mips_sim_next_cycle (state);
}
static void
mips_sim_wait_insn (struct mips_sim *state, rtx insn)
{
mips_sim_wait_regs (state, insn);
mips_sim_wait_units (state, insn);
}
static void
mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
{
struct mips_sim *state;
unsigned int i;
state = data;
if (REG_P (x))
for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
{
state->last_set[REGNO (x) + i].insn = mips_sim_insn;
state->last_set[REGNO (x) + i].time = state->time;
}
}
static void
mips_sim_issue_insn (struct mips_sim *state, rtx insn)
{
state_transition (state->dfa_state, insn);
state->insns_left--;
mips_sim_insn = insn;
note_stores (PATTERN (insn), mips_sim_record_set, state);
}
static void
mips_sim_issue_nop (struct mips_sim *state)
{
if (state->insns_left == 0)
mips_sim_next_cycle (state);
state->insns_left--;
}
static void
mips_sim_finish_insn (struct mips_sim *state, rtx insn)
{
if (JUMP_P (insn))
mips_sim_issue_nop (state);
switch (GET_CODE (SEQ_BEGIN (insn)))
{
case CODE_LABEL:
case CALL_INSN:
mips_sim_reset (state);
break;
case JUMP_INSN:
if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
mips_sim_reset (state);
break;
default:
break;
}
}
static void
vr4130_avoid_branch_rt_conflict (rtx insn)
{
rtx first, second;
first = SEQ_BEGIN (insn);
second = SEQ_END (insn);
if (JUMP_P (first)
&& NONJUMP_INSN_P (second)
&& GET_CODE (PATTERN (first)) == SET
&& GET_CODE (SET_DEST (PATTERN (first))) == PC
&& GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
{
rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
&& REG_P (XEXP (cond, 0))
&& REG_P (XEXP (cond, 1))
&& reg_referenced_p (XEXP (cond, 1), PATTERN (second))
&& !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
{
rtx tmp = XEXP (cond, 0);
XEXP (cond, 0) = XEXP (cond, 1);
XEXP (cond, 1) = tmp;
}
}
}
static void
vr4130_align_insns (void)
{
struct mips_sim state;
rtx insn, subinsn, last, last2, next;
bool aligned_p;
dfa_start ();
last = 0;
last2 = 0;
aligned_p = true;
mips_sim_init (&state, alloca (state_size ()));
for (insn = get_insns (); insn != 0; insn = next)
{
unsigned int length;
next = NEXT_INSN (insn);
vr4130_avoid_branch_rt_conflict (insn);
if (USEFUL_INSN_P (insn))
FOR_EACH_SUBINSN (subinsn, insn)
{
mips_sim_wait_insn (&state, subinsn);
if (state.insns_left != state.issue_rate
&& !CALL_P (subinsn))
{
if (subinsn == SEQ_BEGIN (insn) && aligned_p)
{
emit_insn_after (gen_nop (), last2);
aligned_p = false;
}
else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
{
emit_insn_after (gen_nop (), last);
aligned_p = true;
}
}
mips_sim_issue_insn (&state, subinsn);
}
mips_sim_finish_insn (&state, insn);
length = get_attr_length (insn);
if (length > 0)
{
if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
&& (recog_memoized (insn) < 0 || length >= 8))
{
next = emit_insn_after (gen_align (GEN_INT (3)), insn);
next = NEXT_INSN (next);
mips_sim_next_cycle (&state);
aligned_p = true;
}
else if (length & 4)
aligned_p = !aligned_p;
last2 = last;
last = insn;
}
if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
aligned_p = true;
}
dfa_finish ();
}
static void
mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
rtx *delayed_reg, rtx lo_reg)
{
rtx pattern, set;
int nops, ninsns;
if (!INSN_P (insn))
return;
pattern = PATTERN (insn);
if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
cfun->machine->all_noreorder_p = false;
ninsns = get_attr_length (insn) / 4;
if (ninsns == 0)
return;
if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
nops = 2 - *hilo_delay;
else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
nops = 1;
else
nops = 0;
*hilo_delay += nops;
while (nops-- > 0)
emit_insn_after (gen_hazard_nop (), after);
*hilo_delay += ninsns;
*delayed_reg = 0;
if (INSN_CODE (insn) >= 0)
switch (get_attr_hazard (insn))
{
case HAZARD_NONE:
break;
case HAZARD_HILO:
*hilo_delay = 0;
break;
case HAZARD_DELAY:
set = single_set (insn);
gcc_assert (set != 0);
*delayed_reg = SET_DEST (set);
break;
}
}
static void
mips_avoid_hazards (void)
{
rtx insn, last_insn, lo_reg, delayed_reg;
int hilo_delay, i;
split_all_insns_noflow ();
cfun->machine->ignore_hazard_length_p = true;
shorten_branches (get_insns ());
cfun->machine->all_noreorder_p = true;
if (current_function_profile)
cfun->machine->all_noreorder_p = false;
if (TARGET_FIX_VR4120)
cfun->machine->all_noreorder_p = false;
if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
cfun->machine->all_noreorder_p = false;
last_insn = 0;
hilo_delay = 2;
delayed_reg = 0;
lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
if (INSN_P (insn))
{
if (GET_CODE (PATTERN (insn)) == SEQUENCE)
for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
&hilo_delay, &delayed_reg, lo_reg);
else
mips_avoid_hazard (last_insn, insn, &hilo_delay,
&delayed_reg, lo_reg);
last_insn = insn;
}
}
static void
mips_reorg (void)
{
if (TARGET_MIPS16)
mips16_lay_out_constants ();
else if (TARGET_EXPLICIT_RELOCS)
{
if (mips_flag_delayed_branch)
dbr_schedule (get_insns (), dump_file);
mips_avoid_hazards ();
if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
vr4130_align_insns ();
}
}
#include "config/gofast.h"
static void
mips_init_libfuncs (void)
{
if (TARGET_FIX_VR4120)
{
set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
}
if (TARGET_MIPS16 && mips16_hard_float)
{
set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
if (TARGET_DOUBLE_FLOAT)
{
set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
}
}
else
gofast_maybe_init_libfuncs ();
}
int
mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
enum reg_class to, enum reg_class from)
{
if (from == M16_REGS && GR_REG_CLASS_P (to))
return 2;
else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
return 2;
else if (GR_REG_CLASS_P (from))
{
if (to == M16_REGS)
return 2;
else if (to == M16_NA_REGS)
return 2;
else if (GR_REG_CLASS_P (to))
{
if (TARGET_MIPS16)
return 4;
else
return 2;
}
else if (to == FP_REGS)
return 4;
else if (to == HI_REG || to == LO_REG || to == MD_REGS)
{
if (TARGET_MIPS16)
return 12;
else
return 6;
}
else if (COP_REG_CLASS_P (to))
{
return 5;
}
}
else if (from == FP_REGS)
{
if (GR_REG_CLASS_P (to))
return 4;
else if (to == FP_REGS)
return 2;
else if (to == ST_REGS)
return 8;
}
else if (from == HI_REG || from == LO_REG || from == MD_REGS)
{
if (GR_REG_CLASS_P (to))
{
if (TARGET_MIPS16)
return 12;
else
return 6;
}
}
else if (from == ST_REGS && GR_REG_CLASS_P (to))
return 4;
else if (COP_REG_CLASS_P (from))
{
return 5;
}
return 12;
}
int
mips_adjust_insn_length (rtx insn, int length)
{
if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
length += 4;
if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
switch (get_attr_hazard (insn))
{
case HAZARD_NONE:
break;
case HAZARD_DELAY:
length += 4;
break;
case HAZARD_HILO:
length += 8;
break;
}
if (TARGET_MIPS16)
length /= 2;
return length;
}
const char *
mips_output_load_label (void)
{
if (TARGET_EXPLICIT_RELOCS)
switch (mips_abi)
{
case ABI_N32:
return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
case ABI_64:
return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
default:
if (ISA_HAS_LOAD_DELAY)
return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
}
else
{
if (Pmode == DImode)
return "%[dla\t%@,%0";
else
return "%[la\t%@,%0";
}
}
const char *
mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
int float_p, int inverted_p, int length)
{
static char buffer[200];
enum rtx_code code = GET_CODE (operands[0]);
int need_z_p;
const char *op1 = "%z2";
const char *op2 = (two_operands_p ? ",%z3" : ",%.");
const char *const comp = (float_p ? "%F0" : "%C0");
const char *const inverted_comp = (float_p ? "%W0" : "%N0");
mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
if (!two_operands_p)
{
switch (code)
{
case GTU:
code = NE;
break;
case LEU:
code = EQ;
break;
case GEU:
code = EQ;
op1 = "%.";
break;
case LTU:
code = NE;
op1 = "%.";
break;
default:
break;
}
}
need_z_p = (!float_p && code != EQ && code != NE);
if (need_z_p)
op2 = "";
buffer[0] = '\0';
switch (length)
{
case 4:
case 8:
if (float_p)
sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
inverted_p ? inverted_comp : comp);
else
sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
inverted_p ? inverted_comp : comp,
need_z_p ? "z" : "",
op1,
op2);
return buffer;
case 12:
case 16:
case 24:
case 28:
{
rtx orig_target;
rtx target = gen_label_rtx ();
orig_target = operands[1];
operands[1] = target;
if (float_p)
sprintf (buffer, "%%*b%s\t%%Z2%%1",
inverted_p ? comp : inverted_comp);
else
sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
inverted_p ? comp : inverted_comp,
need_z_p ? "z" : "",
op1,
op2);
output_asm_insn (buffer, operands);
if (length != 16 && length != 28 && ! mips_branch_likely)
{
rtx insn = final_sequence;
final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
optimize, 0, 1, NULL);
INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
}
else
output_asm_insn ("%#", 0);
if (length <= 16)
output_asm_insn ("j\t%0", &orig_target);
else
{
output_asm_insn (mips_output_load_label (), &orig_target);
output_asm_insn ("jr\t%@%]", 0);
}
if (length != 16 && length != 28 && mips_branch_likely)
{
rtx insn = final_sequence;
final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
optimize, 0, 1, NULL);
INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
}
else
output_asm_insn ("%#", 0);
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (target));
return "";
}
default:
gcc_unreachable ();
}
return 0;
}
const char *
mips_output_division (const char *division, rtx *operands)
{
const char *s;
s = division;
if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
{
output_asm_insn (s, operands);
s = "nop";
}
if (TARGET_CHECK_ZERO_DIV)
{
if (TARGET_MIPS16)
{
output_asm_insn (s, operands);
s = "bnez\t%2,1f\n\tbreak\t7\n1:";
}
else if (GENERATE_DIVIDE_TRAPS)
{
output_asm_insn (s, operands);
s = "teq\t%2,%.,7";
}
else
{
output_asm_insn ("%(bne\t%2,%.,1f", operands);
output_asm_insn (s, operands);
s = "break\t7%)\n1:";
}
}
return s;
}
static bool
mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
{
while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
given++, canonical++;
return ((*given == 0 && *canonical == 0)
|| (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
}
static bool
mips_matching_cpu_name_p (const char *canonical, const char *given)
{
if (mips_strict_matching_cpu_name_p (canonical, given))
return true;
if (TOLOWER (*given) == 'r')
given++;
if (!ISDIGIT (*given))
return false;
if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
canonical += 2;
else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
canonical += 2;
else if (TOLOWER (canonical[0]) == 'r')
canonical += 1;
return mips_strict_matching_cpu_name_p (canonical, given);
}
static const struct mips_cpu_info *
mips_parse_cpu (const char *option, const char *cpu_string)
{
const struct mips_cpu_info *p;
const char *s;
for (s = cpu_string; *s != 0; s++)
if (ISUPPER (*s))
{
warning ("the cpu name must be lower case");
break;
}
if (strcasecmp (cpu_string, "from-abi") == 0)
return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
: ABI_NEEDS_64BIT_REGS ? 3
: (TARGET_64BIT ? 3 : 1));
if (strcasecmp (cpu_string, "default") == 0)
return 0;
for (p = mips_cpu_info_table; p->name != 0; p++)
if (mips_matching_cpu_name_p (p->name, cpu_string))
return p;
error ("bad value (%s) for %s", cpu_string, option);
return 0;
}
static const struct mips_cpu_info *
mips_cpu_info_from_isa (int isa)
{
const struct mips_cpu_info *p;
for (p = mips_cpu_info_table; p->name != 0; p++)
if (p->isa == isa)
return p;
return 0;
}
unsigned int
mips_hard_regno_nregs (int regno, enum machine_mode mode)
{
if (ST_REG_P (regno))
return ((GET_MODE_SIZE (mode) + 3) / 4);
else if (! FP_REG_P (regno))
return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
else
return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
}
static bool
mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
{
if (TARGET_OLDABI)
return (TYPE_MODE (type) == BLKmode);
else
return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
|| (int_size_in_bytes (type) == -1));
}
static bool
mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
{
return !TARGET_OLDABI;
}
bool
mips_linked_madd_p (rtx prev, rtx insn)
{
rtx x;
x = single_set (insn);
if (x == 0)
return false;
x = SET_SRC (x);
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 0)) == MULT
&& reg_set_p (XEXP (x, 1), prev))
return true;
if (GET_CODE (x) == MINUS
&& GET_CODE (XEXP (x, 1)) == MULT
&& reg_set_p (XEXP (x, 0), prev))
return true;
return false;
}
static rtx mips_macc_chains_last_hilo;
static void
mips_macc_chains_record (rtx insn)
{
if (get_attr_may_clobber_hilo (insn))
mips_macc_chains_last_hilo = insn;
}
static void
mips_macc_chains_reorder (rtx *ready, int nready)
{
int i, j;
if (mips_macc_chains_last_hilo != 0)
for (i = nready - 1; i >= 0; i--)
if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
{
for (j = nready - 1; j > i; j--)
if (recog_memoized (ready[j]) >= 0
&& get_attr_may_clobber_hilo (ready[j]))
{
mips_promote_ready (ready, i, j);
break;
}
break;
}
}
static rtx vr4130_last_insn;
static void
vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
{
rtx *insn_ptr = data;
if (REG_P (x)
&& *insn_ptr != 0
&& reg_referenced_p (x, PATTERN (*insn_ptr)))
*insn_ptr = 0;
}
static bool
vr4130_true_reg_dependence_p (rtx insn)
{
note_stores (PATTERN (vr4130_last_insn),
vr4130_true_reg_dependence_p_1, &insn);
return insn == 0;
}
static bool
vr4130_swap_insns_p (rtx insn1, rtx insn2)
{
rtx dep;
for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
&& INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
&& recog_memoized (XEXP (dep, 0)) >= 0
&& get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
return false;
if (vr4130_last_insn != 0
&& recog_memoized (insn1) >= 0
&& recog_memoized (insn2) >= 0)
{
enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
if (class1 != class2 || class1 == VR4130_CLASS_ALU)
{
bool dep1 = vr4130_true_reg_dependence_p (insn1);
bool dep2 = vr4130_true_reg_dependence_p (insn2);
if (dep1 != dep2)
return dep1;
if (class1 != VR4130_CLASS_ALU
&& recog_memoized (vr4130_last_insn) >= 0
&& class1 == get_attr_vr4130_class (vr4130_last_insn))
return true;
}
}
return false;
}
static void
vr4130_reorder (rtx *ready, int nready)
{
if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
mips_promote_ready (ready, nready - 2, nready - 1);
}
static void
mips_promote_ready (rtx *ready, int lower, int higher)
{
rtx new_head;
int i;
new_head = ready[lower];
for (i = lower; i < higher; i++)
ready[i] = ready[i + 1];
ready[i] = new_head;
}
static int
mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
rtx *ready, int *nreadyp, int cycle)
{
if (!reload_completed && TUNE_MACC_CHAINS)
{
if (cycle == 0)
mips_macc_chains_last_hilo = 0;
if (*nreadyp > 0)
mips_macc_chains_reorder (ready, *nreadyp);
}
if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
{
if (cycle == 0)
vr4130_last_insn = 0;
if (*nreadyp > 1)
vr4130_reorder (ready, *nreadyp);
}
return mips_issue_rate ();
}
static int
mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
rtx insn, int more)
{
switch (GET_CODE (PATTERN (insn)))
{
case USE:
case CLOBBER:
break;
default:
more--;
if (!reload_completed && TUNE_MACC_CHAINS)
mips_macc_chains_record (insn);
vr4130_last_insn = insn;
break;
}
return more;
}
static int
mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
rtx dep ATTRIBUTE_UNUSED, int cost)
{
if (REG_NOTE_KIND (link) != 0)
return 0;
return cost;
}
static int
mips_issue_rate (void)
{
switch (mips_tune)
{
case PROCESSOR_R4130:
case PROCESSOR_R5400:
case PROCESSOR_R5500:
case PROCESSOR_R7000:
case PROCESSOR_R9000:
return 2;
case PROCESSOR_SB1:
return 3;
default:
return 1;
}
}
static int
mips_multipass_dfa_lookahead (void)
{
if (mips_tune == PROCESSOR_SB1)
return 4;
return 0;
}
rtx
mips_prefetch_cookie (rtx write, rtx locality)
{
if (INTVAL (locality) <= 0)
return GEN_INT (INTVAL (write) + 4);
if (INTVAL (locality) <= 2)
return write;
return GEN_INT (INTVAL (write) + 6);
}
struct builtin_description
{
enum insn_code icode;
enum mips_fp_condition cond;
const char *name;
enum mips_builtin_type builtin_type;
enum mips_function_type function_type;
int target_flags;
};
#define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
{ CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
#define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
{ CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
"__builtin_mips_" #INSN "_" #COND "_s", \
MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
{ CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
"__builtin_mips_" #INSN "_" #COND "_d", \
MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
#define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
"__builtin_mips_any_" #INSN "_" #COND "_ps", \
MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
"__builtin_mips_all_" #INSN "_" #COND "_ps", \
MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
"__builtin_mips_lower_" #INSN "_" #COND "_ps", \
MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
"__builtin_mips_upper_" #INSN "_" #COND "_ps", \
MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
#define CMP_4S_BUILTINS(INSN, COND) \
{ CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
"__builtin_mips_any_" #INSN "_" #COND "_4s", \
MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
MASK_MIPS3D }, \
{ CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
"__builtin_mips_all_" #INSN "_" #COND "_4s", \
MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
MASK_MIPS3D }
#define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
"__builtin_mips_movt_" #INSN "_" #COND "_ps", \
MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
TARGET_FLAGS }, \
{ CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
"__builtin_mips_movf_" #INSN "_" #COND "_ps", \
MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
TARGET_FLAGS }
#define CMP_BUILTINS(COND) \
MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE), \
MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE), \
CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
CMP_4S_BUILTINS (c, COND), \
CMP_4S_BUILTINS (cabs, COND)
#define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
static const struct builtin_description mips_bdesc[] =
{
DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE),
DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE),
DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE),
DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE),
DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, MASK_PAIRED_SINGLE),
DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
MIPS_FP_CONDITIONS (CMP_BUILTINS)
};
#define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
static const struct builtin_description sb1_bdesc[] =
{
DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE)
};
struct bdesc_map
{
const struct builtin_description *bdesc;
unsigned int size;
enum processor_type proc;
};
static const struct bdesc_map bdesc_arrays[] =
{
{ mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_DEFAULT },
{ sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 }
};
static rtx
mips_prepare_builtin_arg (enum insn_code icode,
unsigned int op, tree *arglist)
{
rtx value;
enum machine_mode mode;
value = expand_expr (TREE_VALUE (*arglist), NULL_RTX, VOIDmode, 0);
mode = insn_data[icode].operand[op].mode;
if (!insn_data[icode].operand[op].predicate (value, mode))
value = copy_to_mode_reg (mode, value);
*arglist = TREE_CHAIN (*arglist);
return value;
}
static rtx
mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
{
enum machine_mode mode;
mode = insn_data[icode].operand[op].mode;
if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
target = gen_reg_rtx (mode);
return target;
}
rtx
mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
enum machine_mode mode ATTRIBUTE_UNUSED,
int ignore ATTRIBUTE_UNUSED)
{
enum insn_code icode;
enum mips_builtin_type type;
tree fndecl, arglist;
unsigned int fcode;
const struct builtin_description *bdesc;
const struct bdesc_map *m;
fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
arglist = TREE_OPERAND (exp, 1);
fcode = DECL_FUNCTION_CODE (fndecl);
bdesc = NULL;
for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
{
if (fcode < m->size)
{
bdesc = m->bdesc;
icode = bdesc[fcode].icode;
type = bdesc[fcode].builtin_type;
break;
}
fcode -= m->size;
}
if (bdesc == NULL)
return 0;
switch (type)
{
case MIPS_BUILTIN_DIRECT:
return mips_expand_builtin_direct (icode, target, arglist);
case MIPS_BUILTIN_MOVT:
case MIPS_BUILTIN_MOVF:
return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
target, arglist);
case MIPS_BUILTIN_CMP_ANY:
case MIPS_BUILTIN_CMP_ALL:
case MIPS_BUILTIN_CMP_UPPER:
case MIPS_BUILTIN_CMP_LOWER:
case MIPS_BUILTIN_CMP_SINGLE:
return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
target, arglist);
default:
return 0;
}
}
void
mips_init_builtins (void)
{
const struct builtin_description *d;
const struct bdesc_map *m;
tree types[(int) MIPS_MAX_FTYPE_MAX];
tree V2SF_type_node;
unsigned int offset;
if (!TARGET_PAIRED_SINGLE_FLOAT)
return;
V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
types[MIPS_V2SF_FTYPE_V2SF]
= build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
types[MIPS_V2SF_FTYPE_V2SF_V2SF]
= build_function_type_list (V2SF_type_node,
V2SF_type_node, V2SF_type_node, NULL_TREE);
types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
= build_function_type_list (V2SF_type_node,
V2SF_type_node, V2SF_type_node,
integer_type_node, NULL_TREE);
types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
= build_function_type_list (V2SF_type_node,
V2SF_type_node, V2SF_type_node,
V2SF_type_node, V2SF_type_node, NULL_TREE);
types[MIPS_V2SF_FTYPE_SF_SF]
= build_function_type_list (V2SF_type_node,
float_type_node, float_type_node, NULL_TREE);
types[MIPS_INT_FTYPE_V2SF_V2SF]
= build_function_type_list (integer_type_node,
V2SF_type_node, V2SF_type_node, NULL_TREE);
types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
= build_function_type_list (integer_type_node,
V2SF_type_node, V2SF_type_node,
V2SF_type_node, V2SF_type_node, NULL_TREE);
types[MIPS_INT_FTYPE_SF_SF]
= build_function_type_list (integer_type_node,
float_type_node, float_type_node, NULL_TREE);
types[MIPS_INT_FTYPE_DF_DF]
= build_function_type_list (integer_type_node,
double_type_node, double_type_node, NULL_TREE);
types[MIPS_SF_FTYPE_V2SF]
= build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
types[MIPS_SF_FTYPE_SF]
= build_function_type_list (float_type_node,
float_type_node, NULL_TREE);
types[MIPS_SF_FTYPE_SF_SF]
= build_function_type_list (float_type_node,
float_type_node, float_type_node, NULL_TREE);
types[MIPS_DF_FTYPE_DF]
= build_function_type_list (double_type_node,
double_type_node, NULL_TREE);
types[MIPS_DF_FTYPE_DF_DF]
= build_function_type_list (double_type_node,
double_type_node, double_type_node, NULL_TREE);
offset = 0;
for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
{
if (m->proc == PROCESSOR_DEFAULT || (m->proc == mips_arch))
for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
if ((d->target_flags & target_flags) == d->target_flags)
lang_hooks.builtin_function (d->name, types[d->function_type],
d - m->bdesc + offset,
BUILT_IN_MD, NULL, NULL);
offset += m->size;
}
}
static rtx
mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist)
{
rtx ops[MAX_RECOG_OPERANDS];
int i;
target = mips_prepare_builtin_target (icode, 0, target);
for (i = 1; i < insn_data[icode].n_operands; i++)
ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
switch (insn_data[icode].n_operands)
{
case 2:
emit_insn (GEN_FCN (icode) (target, ops[1]));
break;
case 3:
emit_insn (GEN_FCN (icode) (target, ops[1], ops[2]));
break;
case 4:
emit_insn (GEN_FCN (icode) (target, ops[1], ops[2], ops[3]));
break;
default:
gcc_unreachable ();
}
return target;
}
static rtx
mips_expand_builtin_movtf (enum mips_builtin_type type,
enum insn_code icode, enum mips_fp_condition cond,
rtx target, tree arglist)
{
rtx cmp_result, op0, op1;
cmp_result = mips_prepare_builtin_target (icode, 0, 0);
op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
icode = CODE_FOR_mips_cond_move_tf_ps;
target = mips_prepare_builtin_target (icode, 0, target);
if (type == MIPS_BUILTIN_MOVT)
{
op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
}
else
{
op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
}
emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
return target;
}
static rtx
mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
enum insn_code icode, enum mips_fp_condition cond,
rtx target, tree arglist)
{
rtx label1, label2, if_then_else;
rtx pat, cmp_result, ops[MAX_RECOG_OPERANDS];
rtx target_if_equal, target_if_unequal;
int cmp_value, i;
if (target == 0 || GET_MODE (target) != SImode)
target = gen_reg_rtx (SImode);
cmp_result = mips_prepare_builtin_target (icode, 0, 0);
for (i = 1; i < insn_data[icode].n_operands - 1; i++)
ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
switch (insn_data[icode].n_operands)
{
case 4:
pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond));
break;
case 6:
pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2],
ops[3], ops[4], GEN_INT (cond));
break;
default:
gcc_unreachable ();
}
if (builtin_type == MIPS_BUILTIN_CMP_ALL)
{
cmp_value = -1;
target_if_equal = const1_rtx;
target_if_unequal = const0_rtx;
}
else
{
cmp_value = 0;
target_if_equal = const0_rtx;
target_if_unequal = const1_rtx;
if (builtin_type == MIPS_BUILTIN_CMP_UPPER)
cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 4);
else if (builtin_type == MIPS_BUILTIN_CMP_LOWER)
cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 0);
}
emit_move_insn (target, target_if_equal);
emit_insn (pat);
label1 = gen_label_rtx ();
label2 = gen_label_rtx ();
if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode,
gen_rtx_fmt_ee (NE, GET_MODE (cmp_result),
cmp_result, GEN_INT (cmp_value)),
gen_rtx_LABEL_REF (VOIDmode, label1), pc_rtx);
emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_then_else));
emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
gen_rtx_LABEL_REF (VOIDmode, label2)));
emit_barrier ();
emit_label (label1);
emit_move_insn (target, target_if_unequal);
emit_label (label2);
return target;
}
#include "gt-mips.h"