#define OBJECT_XCOFF 1
#define OBJECT_ELF 2
#define OBJECT_PEF 3
#define OBJECT_MACHO 4
#define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
#define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
#define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
#define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
#ifndef TARGET_AIX
#define TARGET_AIX 0
#endif
#define DOT_SYMBOLS 1
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT ((char *)0)
#endif
#define ASM_CPU_SPEC \
"%{!mcpu*: \
%{mpower: %{!mpower2: -mpwr}} \
%{mpower2: -mpwrx} \
%{mpowerpc64*: -mppc64} \
%{!mpowerpc64*: %{mpowerpc*: -mppc}} \
%{mno-power: %{!mpowerpc*: -mcom}} \
%{!mno-power: %{!mpower*: %(asm_default)}}} \
%{mcpu=common: -mcom} \
%{mcpu=power: -mpwr} \
%{mcpu=power2: -mpwrx} \
%{mcpu=power3: -mppc64} \
%{mcpu=power4: -mpower4} \
%{mcpu=power5: -mpower4} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rios: -mpwr} \
%{mcpu=rios1: -mpwr} \
%{mcpu=rios2: -mpwrx} \
%{mcpu=rsc: -mpwr} \
%{mcpu=rsc1: -mpwr} \
%{mcpu=rs64a: -mppc64} \
%{mcpu=401: -mppc} \
%{mcpu=403: -m403} \
%{mcpu=405: -m405} \
%{mcpu=405fp: -m405} \
%{mcpu=440: -m440} \
%{mcpu=440fp: -m440} \
%{mcpu=505: -mppc} \
%{mcpu=601: -m601} \
%{mcpu=602: -mppc} \
%{mcpu=603: -mppc} \
%{mcpu=603e: -mppc} \
%{mcpu=ec603e: -mppc} \
%{mcpu=604: -mppc} \
%{mcpu=604e: -mppc} \
%{mcpu=620: -mppc64} \
%{mcpu=630: -mppc64} \
%{mcpu=740: -mppc} \
%{mcpu=750: -mppc} \
%{mcpu=G3: -mppc} \
%{mcpu=7400: -mppc -maltivec} \
%{mcpu=7450: -mppc -maltivec} \
%{mcpu=G4: -mppc -maltivec} \
%{mcpu=801: -mppc} \
%{mcpu=821: -mppc} \
%{mcpu=823: -mppc} \
%{mcpu=860: -mppc} \
%{mcpu=970: -mpower4 -maltivec} \
%{mcpu=G5: -mpower4 -maltivec} \
%{mcpu=8540: -me500} \
%{maltivec: -maltivec} \
-many"
#define CPP_DEFAULT_SPEC ""
#define ASM_DEFAULT_SPEC ""
#define SUBTARGET_EXTRA_SPECS
#define EXTRA_SPECS \
{ "cpp_default", CPP_DEFAULT_SPEC }, \
{ "asm_cpu", ASM_CPU_SPEC }, \
{ "asm_default", ASM_DEFAULT_SPEC }, \
SUBTARGET_EXTRA_SPECS
extern int target_flags;
#define MASK_POWER 0x00000001
#define MASK_POWER2 0x00000002
#define MASK_POWERPC 0x00000004
#define MASK_PPC_GPOPT 0x00000008
#define MASK_PPC_GFXOPT 0x00000010
#define MASK_POWERPC64 0x00000020
#define MASK_NEW_MNEMONICS 0x00000040
#define MASK_NO_FP_IN_TOC 0x00000080
#define MASK_NO_SUM_IN_TOC 0x00000100
#define MASK_MINIMAL_TOC 0x00000200
#define MASK_64BIT 0x00000400
#define MASK_SOFT_FLOAT 0x00000800
#define MASK_MULTIPLE 0x00001000
#define MASK_STRING 0x00002000
#define MASK_NO_UPDATE 0x00004000
#define MASK_NO_FUSED_MADD 0x00008000
#define MASK_SCHED_PROLOG 0x00010000
#define MASK_ALTIVEC 0x00020000
#define MASK_AIX_STRUCT_RET 0x00040000
#define MASK_MFCRF 0x00080000
#define TARGET_POWER (target_flags & MASK_POWER)
#define TARGET_POWER2 (target_flags & MASK_POWER2)
#define TARGET_POWERPC (target_flags & MASK_POWERPC)
#define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
#define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
#define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
#define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
#define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
#define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
#define TARGET_64BIT (target_flags & MASK_64BIT)
#define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
#define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
#define TARGET_STRING (target_flags & MASK_STRING)
#define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
#define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
#define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
#define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
#define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
#ifdef HAVE_AS_MFCRF
#define TARGET_MFCRF (target_flags & MASK_MFCRF)
#else
#define TARGET_MFCRF 0
#endif
#define TARGET_32BIT (! TARGET_64BIT)
#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
#define TARGET_UPDATE (! TARGET_NO_UPDATE)
#define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
#ifdef HAVE_AS_TLS
#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
rs6000_output_dwarf_dtprel (FILE, SIZE, X)
#endif
#ifndef HAVE_AS_TLS
#define HAVE_AS_TLS 0
#endif
#ifdef IN_LIBGCC2
#if defined (__64BIT__) || defined (__powerpc64__)
#define TARGET_POWERPC64 1
#else
#define TARGET_POWERPC64 0
#endif
#else
#define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
#endif
#define TARGET_XL_COMPAT 0
#define TARGET_SWITCHES \
{{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
N_("Use POWER instruction set")}, \
{"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
| MASK_POWER2), \
N_("Use POWER2 instruction set")}, \
{"no-power2", - MASK_POWER2, \
N_("Do not use POWER2 instruction set")}, \
{"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
| MASK_STRING), \
N_("Do not use POWER instruction set")}, \
{"powerpc", MASK_POWERPC, \
N_("Use PowerPC instruction set")}, \
{"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
| MASK_PPC_GFXOPT | MASK_POWERPC64), \
N_("Do not use PowerPC instruction set")}, \
{"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
N_("Use PowerPC General Purpose group optional instructions")},\
{"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
N_("Do not use PowerPC General Purpose group optional instructions")},\
{"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
N_("Use PowerPC Graphics group optional instructions")},\
{"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
N_("Do not use PowerPC Graphics group optional instructions")},\
{"powerpc64", MASK_POWERPC64, \
N_("Use PowerPC-64 instruction set")}, \
{"no-powerpc64", - MASK_POWERPC64, \
N_("Do not use PowerPC-64 instruction set")}, \
{"altivec", MASK_ALTIVEC , \
N_("Use AltiVec instructions")}, \
{"no-altivec", - MASK_ALTIVEC , \
N_("Do not use AltiVec instructions")}, \
{"new-mnemonics", MASK_NEW_MNEMONICS, \
N_("Use new mnemonics for PowerPC architecture")},\
{"old-mnemonics", -MASK_NEW_MNEMONICS, \
N_("Use old mnemonics for PowerPC architecture")},\
{"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
| MASK_MINIMAL_TOC), \
N_("Put everything in the regular TOC")}, \
{"fp-in-toc", - MASK_NO_FP_IN_TOC, \
N_("Place floating point constants in TOC")}, \
{"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
N_("Do not place floating point constants in TOC")},\
{"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
N_("Place symbol+offset constants in TOC")}, \
{"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
N_("Do not place symbol+offset constants in TOC")},\
{"minimal-toc", MASK_MINIMAL_TOC, \
"Use only one TOC entry per procedure"}, \
{"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
""}, \
{"no-minimal-toc", - MASK_MINIMAL_TOC, \
N_("Place variable addresses in the regular TOC")},\
{"hard-float", - MASK_SOFT_FLOAT, \
N_("Use hardware floating point")}, \
{"soft-float", MASK_SOFT_FLOAT, \
N_("Do not use hardware floating point")}, \
{"multiple", MASK_MULTIPLE, \
N_("Generate load/store multiple instructions")}, \
{"no-multiple", - MASK_MULTIPLE, \
N_("Do not generate load/store multiple instructions")},\
{"string", MASK_STRING, \
N_("Generate string instructions for block moves")},\
{"no-string", - MASK_STRING, \
N_("Do not generate string instructions for block moves")},\
{"update", - MASK_NO_UPDATE, \
N_("Generate load/store with update instructions")},\
{"no-update", MASK_NO_UPDATE, \
N_("Do not generate load/store with update instructions")},\
{"fused-madd", - MASK_NO_FUSED_MADD, \
N_("Generate fused multiply/add instructions")},\
{"no-fused-madd", MASK_NO_FUSED_MADD, \
N_("Do not generate fused multiply/add instructions")},\
{"sched-prolog", MASK_SCHED_PROLOG, \
""}, \
{"no-sched-prolog", -MASK_SCHED_PROLOG, \
N_("Do not schedule the start and end of the procedure")},\
{"sched-epilog", MASK_SCHED_PROLOG, \
""}, \
{"no-sched-epilog", -MASK_SCHED_PROLOG, \
""}, \
{"aix-struct-return", MASK_AIX_STRUCT_RET, \
N_("Return all structures in memory (AIX default)")},\
{"svr4-struct-return", - MASK_AIX_STRUCT_RET, \
N_("Return small structures in registers (SVR4 default)")},\
{"no-aix-struct-return", - MASK_AIX_STRUCT_RET, \
""}, \
{"no-svr4-struct-return", MASK_AIX_STRUCT_RET, \
""}, \
{"mfcrf", MASK_MFCRF, \
N_("Generate single field mfcr instruction")}, \
{"no-mfcrf", - MASK_MFCRF, \
N_("Do not generate single field mfcr instruction")},\
SUBTARGET_SWITCHES \
{"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
""}}
#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
#define SUBTARGET_SWITCHES
enum processor_type
{
PROCESSOR_RIOS1,
PROCESSOR_RIOS2,
PROCESSOR_RS64A,
PROCESSOR_MPCCORE,
PROCESSOR_PPC403,
PROCESSOR_PPC405,
PROCESSOR_PPC440,
PROCESSOR_PPC601,
PROCESSOR_PPC603,
PROCESSOR_PPC604,
PROCESSOR_PPC604e,
PROCESSOR_PPC620,
PROCESSOR_PPC630,
PROCESSOR_PPC750,
PROCESSOR_PPC7400,
PROCESSOR_PPC7450,
PROCESSOR_PPC8540,
PROCESSOR_POWER4,
PROCESSOR_POWER5
};
extern enum processor_type rs6000_cpu;
#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
#define PROCESSOR_COMMON PROCESSOR_PPC601
#define PROCESSOR_POWER PROCESSOR_RIOS1
#define PROCESSOR_POWERPC PROCESSOR_PPC604
#define PROCESSOR_POWERPC64 PROCESSOR_RS64A
#define PROCESSOR_DEFAULT PROCESSOR_RIOS1
#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
enum rs6000_dependence_cost
{
max_dep_latency = 1000,
no_dep_costly,
all_deps_costly,
true_store_to_load_dep_costly,
store_to_load_dep_costly
};
enum rs6000_nop_insertion
{
sched_finish_regroup_exact = 1000,
sched_finish_pad_groups,
sched_finish_none
};
enum group_termination
{
current_group,
previous_group
};
#define SUBTARGET_OPTIONS
#define TARGET_OPTIONS \
{ \
{"cpu=", &rs6000_select[1].string, \
N_("Use features of and schedule code for given CPU"), 0}, \
{"tune=", &rs6000_select[2].string, \
N_("Schedule code for given CPU"), 0}, \
{"debug=", &rs6000_debug_name, N_("Enable debug output"), 0}, \
{"traceback=", &rs6000_traceback_name, \
N_("Select full, part, or no traceback table"), 0}, \
{"abi=", &rs6000_abi_string, N_("Specify ABI to use"), 0}, \
{"long-double-", &rs6000_long_double_size_string, \
N_("Specify size of long double (64 or 128 bits)"), 0}, \
{"isel=", &rs6000_isel_string, \
N_("Specify yes/no if isel instructions should be generated"), 0}, \
{"spe=", &rs6000_spe_string, \
N_("Specify yes/no if SPE SIMD instructions should be generated"), 0},\
{"float-gprs=", &rs6000_float_gprs_string, \
N_("Specify yes/no if using floating point in the GPRs"), 0}, \
{"vrsave=", &rs6000_altivec_vrsave_string, \
N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec"), 0}, \
{"longcall", &rs6000_longcall_switch, \
N_("Avoid all range limits on call instructions"), 0}, \
{"no-longcall", &rs6000_longcall_switch, "", 0}, \
{"warn-altivec-long", &rs6000_warn_altivec_long_switch, \
N_("Warn about deprecated 'vector long ...' AltiVec type usage"), 0}, \
{"no-warn-altivec-long", &rs6000_warn_altivec_long_switch, "", 0}, \
{"sched-costly-dep=", &rs6000_sched_costly_dep_str, \
N_("Determine which dependences between insns are considered costly"), 0}, \
{"insert-sched-nops=", &rs6000_sched_insert_nops_str, \
N_("Specify which post scheduling nop insertion scheme to apply"), 0}, \
{"align-", &rs6000_alignment_string, \
N_("Specify alignment of structure fields default/natural"), 0}, \
{"prioritize-restricted-insns=", &rs6000_sched_restricted_insns_priority_str, \
N_("Specify scheduling priority for dispatch slot restricted insns"), 0}, \
SUBTARGET_OPTIONS \
}
#define OPTION_DEFAULT_SPECS \
{"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
{"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
{"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
struct rs6000_cpu_select
{
const char *string;
const char *name;
int set_tune_p;
int set_arch_p;
};
extern struct rs6000_cpu_select rs6000_select[];
extern const char *rs6000_debug_name;
extern const char *rs6000_abi_string;
extern int rs6000_debug_stack;
extern int rs6000_debug_arg;
#define TARGET_DEBUG_STACK rs6000_debug_stack
#define TARGET_DEBUG_ARG rs6000_debug_arg
extern const char *rs6000_traceback_name;
extern const char *rs6000_long_double_size_string;
extern int rs6000_long_double_type_size;
extern int rs6000_altivec_abi;
extern int rs6000_spe_abi;
extern int rs6000_isel;
extern int rs6000_spe;
extern int rs6000_float_gprs;
extern const char *rs6000_float_gprs_string;
extern const char *rs6000_isel_string;
extern const char *rs6000_spe_string;
extern const char *rs6000_altivec_vrsave_string;
extern int rs6000_altivec_vrsave;
extern const char *rs6000_longcall_switch;
extern int rs6000_default_long_calls;
extern const char* rs6000_alignment_string;
extern int rs6000_alignment_flags;
extern const char *rs6000_sched_restricted_insns_priority_str;
extern int rs6000_sched_restricted_insns_priority;
extern const char *rs6000_sched_costly_dep_str;
extern enum rs6000_dependence_cost rs6000_sched_costly_dep;
extern const char *rs6000_sched_insert_nops_str;
extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
extern int rs6000_warn_altivec_long;
extern const char *rs6000_warn_altivec_long_switch;
#ifndef IN_TARGET_LIBS
#define MASK_ALIGN_POWER 0x00000000
#define MASK_ALIGN_NATURAL 0x00000001
#define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
#else
#define TARGET_ALIGN_NATURAL 0
#endif
#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
#define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
#define TARGET_SPE_ABI 0
#define TARGET_SPE 0
#define TARGET_E500 0
#define TARGET_ISEL 0
#define TARGET_FPRS 1
#define TARGET_E500_SINGLE 0
#define TARGET_E500_DOUBLE 0
#define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
#define CAN_DEBUG_WITHOUT_FP
#define REGISTER_TARGET_PRAGMAS() do { \
c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
} while (0)
#define TARGET_CPU_CPP_BUILTINS() \
rs6000_cpu_cpp_builtins (pfile)
#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
do \
{ \
if (BYTES_BIG_ENDIAN) \
{ \
builtin_define ("__BIG_ENDIAN__"); \
builtin_define ("_BIG_ENDIAN"); \
builtin_assert ("machine=bigendian"); \
} \
else \
{ \
builtin_define ("__LITTLE_ENDIAN__"); \
builtin_define ("_LITTLE_ENDIAN"); \
builtin_assert ("machine=littleendian"); \
} \
} \
while (0)
#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
(MODE) = TARGET_32BIT ? SImode : DImode;
#define BITS_BIG_ENDIAN 1
#define BYTES_BIG_ENDIAN 1
#define WORDS_BIG_ENDIAN 1
#define MAX_BITS_PER_WORD 64
#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
#ifdef IN_LIBGCC2
#define MIN_UNITS_PER_WORD UNITS_PER_WORD
#else
#define MIN_UNITS_PER_WORD 4
#endif
#define UNITS_PER_FP_WORD 8
#define UNITS_PER_ALTIVEC_WORD 16
#define UNITS_PER_SPE_WORD 8
#define PTRDIFF_TYPE "int"
#define SIZE_TYPE "long unsigned int"
#define WCHAR_TYPE "short unsigned int"
#define WCHAR_TYPE_SIZE 16
#define SHORT_TYPE_SIZE 16
#define INT_TYPE_SIZE 32
#define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
#ifdef __LONG_DOUBLE_128__
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
#else
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
#endif
#define WIDEST_HARDWARE_FP_SIZE 64
#define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
#define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
#define STACK_BOUNDARY \
((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
#define FUNCTION_BOUNDARY 32
#define BIGGEST_ALIGNMENT 128
#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
(TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \
(TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
#define EMPTY_FIELD_BOUNDARY 32
#define STRUCTURE_SIZE_BOUNDARY 8
#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
|| (TARGET_E500_DOUBLE && (MODE) == DFmode))
#define PCC_BITFIELD_TYPE_MATTERS 1
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
(TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < BITS_PER_WORD \
? BITS_PER_WORD \
: (ALIGN))
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
: (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \
: TREE_CODE (TYPE) == ARRAY_TYPE \
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
#define STRICT_ALIGNMENT 0
#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
(STRICT_ALIGNMENT \
|| (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
|| (MODE) == DImode) \
&& (ALIGN) < 32))
#define FIRST_PSEUDO_REGISTER 113
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER + 32)
#define DWARF_REG_TO_UNWIND_COLUMN(r) \
((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER) : (r))
#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
#define FIXED_REGISTERS \
{0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
, 1, 1 \
}
#define CALL_USED_REGISTERS \
{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
, 1, 1 \
}
#define CALL_REALLY_USED_REGISTERS \
{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0 \
, 0, 0 \
}
#define MQ_REGNO 64
#define CR0_REGNO 68
#define CR1_REGNO 69
#define CR2_REGNO 70
#define CR3_REGNO 71
#define CR4_REGNO 72
#define MAX_CR_REGNO 75
#define XER_REGNO 76
#define FIRST_ALTIVEC_REGNO 77
#define LAST_ALTIVEC_REGNO 108
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
#define VRSAVE_REGNO 109
#define VSCR_REGNO 110
#define SPE_ACC_REGNO 111
#define SPEFSCR_REGNO 112
#define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
#define FIRST_SAVED_FP_REGNO (14+32)
#define FIRST_SAVED_GP_REGNO 13
#if FIXED_R2 == 1
#define MAYBE_R2_AVAILABLE
#define MAYBE_R2_FIXED 2,
#else
#define MAYBE_R2_AVAILABLE 2,
#define MAYBE_R2_FIXED
#endif
#define REG_ALLOC_ORDER \
{32, \
45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
33, \
63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
50, 49, 48, 47, 46, \
75, 74, 69, 68, 72, 71, 70, \
0, MAYBE_R2_AVAILABLE \
9, 11, 10, 8, 7, 6, 5, 4, \
3, \
31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
18, 17, 16, 15, 14, 13, 12, \
64, 66, 65, \
73, 1, MAYBE_R2_FIXED 67, 76, \
\
77, 78, \
90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
79, \
96, 95, 94, 93, 92, 91, \
108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
97, 109, 110 \
, 111, 112 \
}
#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
#define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
#define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
#define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
#define SPE_SIMD_REGNO_P(N) ((N) <= 31)
#define XER_REGNO_P(N) ((N) == XER_REGNO)
#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
#define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
((TARGET_32BIT && TARGET_POWERPC64 \
&& (GET_MODE_SIZE (MODE) > 4) \
&& INT_REGNO_P (REGNO)) ? 1 : 0)
#define ALTIVEC_VECTOR_MODE(MODE) \
((MODE) == V16QImode \
|| (MODE) == V8HImode \
|| (MODE) == V4SFmode \
|| (MODE) == V4SImode)
#define SPE_VECTOR_MODE(MODE) \
((MODE) == V4HImode \
|| (MODE) == V2SFmode \
|| (MODE) == V1DImode \
|| (MODE) == V2SImode)
#define UNITS_PER_SIMD_WORD \
(TARGET_ALTIVEC ? 16 : (TARGET_SPE ? 8 : 0) )
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
#define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_CLASS (MODE1) == MODE_FLOAT \
? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
: GET_MODE_CLASS (MODE2) == MODE_FLOAT \
? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
: GET_MODE_CLASS (MODE1) == MODE_CC \
? GET_MODE_CLASS (MODE2) == MODE_CC \
: GET_MODE_CLASS (MODE2) == MODE_CC \
? GET_MODE_CLASS (MODE1) == MODE_CC \
: SPE_VECTOR_MODE (MODE1) \
? SPE_VECTOR_MODE (MODE2) \
: SPE_VECTOR_MODE (MODE2) \
? SPE_VECTOR_MODE (MODE1) \
: ALTIVEC_VECTOR_MODE (MODE1) \
? ALTIVEC_VECTOR_MODE (MODE2) \
: ALTIVEC_VECTOR_MODE (MODE2) \
? ALTIVEC_VECTOR_MODE (MODE1) \
: 1)
#define HARD_REGNO_RENAME_OK(SRC, DST) \
(! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
#define REGISTER_MOVE_COST rs6000_register_move_cost
#define MEMORY_MOVE_COST rs6000_memory_move_cost
#define BRANCH_COST 3
#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
#define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
#define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
#define STACK_POINTER_REGNUM 1
#define FRAME_POINTER_REGNUM 31
#define FRAME_POINTER_REQUIRED 0
#define ARG_POINTER_REGNUM 67
#define STATIC_CHAIN_REGNUM 11
#define LINK_REGISTER_REGNUM 65
#define COUNT_REGISTER_REGNUM 66
enum reg_class
{
NO_REGS,
BASE_REGS,
GENERAL_REGS,
FLOAT_REGS,
ALTIVEC_REGS,
VRSAVE_REGS,
VSCR_REGS,
SPE_ACC_REGS,
SPEFSCR_REGS,
NON_SPECIAL_REGS,
MQ_REGS,
LINK_REGS,
CTR_REGS,
LINK_OR_CTR_REGS,
SPECIAL_REGS,
SPEC_OR_GEN_REGS,
CR0_REGS,
CR_REGS,
NON_FLOAT_REGS,
XER_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"BASE_REGS", \
"GENERAL_REGS", \
"FLOAT_REGS", \
"ALTIVEC_REGS", \
"VRSAVE_REGS", \
"VSCR_REGS", \
"SPE_ACC_REGS", \
"SPEFSCR_REGS", \
"NON_SPECIAL_REGS", \
"MQ_REGS", \
"LINK_REGS", \
"CTR_REGS", \
"LINK_OR_CTR_REGS", \
"SPECIAL_REGS", \
"SPEC_OR_GEN_REGS", \
"CR0_REGS", \
"CR_REGS", \
"NON_FLOAT_REGS", \
"XER_REGS", \
"ALL_REGS" \
}
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, \
{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \
{ 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
{ 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \
{ 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, \
{ 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
{ 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, \
{ 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \
{ 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } \
}
#define REGNO_REG_CLASS(REGNO) \
((REGNO) == 0 ? GENERAL_REGS \
: (REGNO) < 32 ? BASE_REGS \
: FP_REGNO_P (REGNO) ? FLOAT_REGS \
: ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
: (REGNO) == CR0_REGNO ? CR0_REGS \
: CR_REGNO_P (REGNO) ? CR_REGS \
: (REGNO) == MQ_REGNO ? MQ_REGS \
: (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
: (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
: (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
: (REGNO) == XER_REGNO ? XER_REGS \
: (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
: (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
: (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
: (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
: NO_REGS)
#define INDEX_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS BASE_REGS
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'f' ? ((TARGET_HARD_FLOAT && TARGET_FPRS) ? FLOAT_REGS : NO_REGS) \
: (C) == 'b' ? BASE_REGS \
: (C) == 'h' ? SPECIAL_REGS \
: (C) == 'q' ? MQ_REGS \
: (C) == 'c' ? CTR_REGS \
: (C) == 'l' ? LINK_REGS \
: (C) == 'v' ? ALTIVEC_REGS \
: (C) == 'x' ? CR0_REGS \
: (C) == 'y' ? CR_REGS \
: (C) == 'z' ? XER_REGS \
: NO_REGS)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
: (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
: (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
: (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
&& ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
: (C) == 'M' ? (VALUE) > 31 \
: (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
: (C) == 'O' ? (VALUE) == 0 \
: (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
: 0)
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
== ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
: (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
: 0)
#define EXTRA_CONSTRAINT(OP, C) \
((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
: (C) == 'R' ? legitimate_constant_pool_address_p (OP) \
: (C) == 'S' ? mask64_operand (OP, DImode) \
: (C) == 'T' ? mask_operand (OP, SImode) \
: (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
&& small_data_operand (OP, GET_MODE (OP))) \
: (C) == 't' ? (mask64_2_operand (OP, DImode) \
&& (fixed_regs[CR0_REGNO] \
|| !logical_operand (OP, DImode)) \
&& !mask64_operand (OP, DImode)) \
: (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
: (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \
: 0)
#define EXTRA_MEMORY_CONSTRAINT(C, STR) \
((C) == 'Q' || (C) == 'Y')
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
((CONSTANT_P (X) \
&& reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
? NO_REGS \
: (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
&& (CLASS) == NON_SPECIAL_REGS) \
? GENERAL_REGS \
: (CLASS))
#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
secondary_reload_class (CLASS, MODE, IN)
#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
|| (CLASS2) == FLOAT_REGS \
|| (CLASS1) == ALTIVEC_REGS \
|| (CLASS2) == ALTIVEC_REGS))
#define CLASS_MAX_NREGS(CLASS, MODE) \
(((CLASS) == FLOAT_REGS) \
? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
: (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \
? 1 \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
(((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) \
&& GET_MODE_SIZE (FROM) >= 8 && GET_MODE_SIZE (TO) >= 8) \
? 0 \
: GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
: (TARGET_E500_DOUBLE && (((TO) == DFmode) + ((FROM) == DFmode)) == 1) \
? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
: (TARGET_E500_DOUBLE && (((TO) == DImode) + ((FROM) == DImode)) == 1) \
? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
: (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \
? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
: 0)
enum rs6000_abi {
ABI_NONE,
ABI_AIX,
ABI_V4,
ABI_DARWIN
};
extern enum rs6000_abi rs6000_current_abi;
#define STACK_GROWS_DOWNWARD
#define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
|| DEFAULT_ABI == ABI_DARWIN) \
? (TARGET_64BIT ? 64 : 32) \
: 0)
#define RS6000_SAVE_AREA \
(((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
<< (TARGET_64BIT ? 1 : 0))
#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
plus_constant (stack_pointer_rtx, \
(TARGET_32BIT ? 20 : 40)))
#define RS6000_VARARGS_AREA 0
#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
#define RS6000_VARARGS_SIZE \
((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
#define STARTING_FRAME_OFFSET \
(RS6000_ALIGN (current_function_outgoing_args_size, \
TARGET_ALTIVEC ? 16 : 8) \
+ RS6000_VARARGS_AREA \
+ RS6000_SAVE_AREA)
#define STACK_DYNAMIC_OFFSET(FUNDECL) \
(RS6000_ALIGN (current_function_outgoing_args_size, \
TARGET_ALTIVEC ? 16 : 8) \
+ (STACK_POINTER_OFFSET))
#define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
#define OUTGOING_REG_PARM_STACK_SPACE
#define STACK_POINTER_OFFSET RS6000_SAVE_AREA
#define ACCUMULATE_OUTGOING_ARGS 1
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
#define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
#define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
#define DRAFT_V4_STRUCT_RET 0
#define DEFAULT_PCC_STRUCT_RETURN 0
#define STACK_SAVEAREA_MODE(LEVEL) \
(LEVEL == SAVE_FUNCTION ? VOIDmode \
: LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
#define GP_ARG_MIN_REG 3
#define GP_ARG_MAX_REG 10
#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
#define FP_ARG_MIN_REG 33
#define FP_ARG_AIX_MAX_REG 45
#define FP_ARG_V4_MAX_REG 40
#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
|| DEFAULT_ABI == ABI_DARWIN) \
? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
#define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
#define GP_ARG_RETURN GP_ARG_MIN_REG
#define FP_ARG_RETURN FP_ARG_MIN_REG
#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
#define CALL_NORMAL 0x00000000
#define CALL_V4_CLEAR_FP_ARGS 0x00000002
#define CALL_V4_SET_FP_ARGS 0x00000004
#define CALL_LONG 0x00000008
#define CALL_LIBCALL 0x00000010
#define WORLD_SAVE_P(INFO) 0
#define FUNCTION_VALUE_REGNO_P(N) \
((N) == GP_ARG_RETURN \
|| ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
|| ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
#define FUNCTION_ARG_REGNO_P(N) \
((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
|| ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
&& TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
|| ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
&& TARGET_HARD_FLOAT && TARGET_FPRS))
typedef struct machine_function GTY(())
{
int ra_needs_full_frame;
const char *some_ld_name;
int insn_chain_scanned_p;
int ra_need_lr;
} machine_function;
typedef struct rs6000_args
{
int words;
int fregno;
int vregno;
int nargs_prototype;
int prototype;
int stdarg;
int call_cookie;
int sysv_gregno;
int intoffset;
int use_stack;
int named;
} CUMULATIVE_ARGS;
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
function_arg (&CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
function_arg_boundary (MODE, TYPE)
#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
rs6000_va_start (valist, nextarg)
#define PAD_VARARGS_DOWN \
(FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
#define FUNCTION_PROFILER(FILE, LABELNO) \
output_function_profiler ((FILE), (LABELNO));
#define EXIT_IGNORE_STACK 1
#define EPILOGUE_USES(REGNO) \
((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
|| (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
|| (current_function_calls_eh_return \
&& TARGET_AIX \
&& (REGNO) == 2))
#define TRAMPOLINE_SIZE rs6000_trampoline_size ()
#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
#define RETURN_ADDRESS_OFFSET \
((DEFAULT_ABI == ABI_AIX \
|| DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
(DEFAULT_ABI == ABI_V4) ? 4 : \
(internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
#define RETURN_ADDR_RTX(COUNT, FRAME) \
(rs6000_return_addr (COUNT, FRAME))
#define ELIMINABLE_REGS \
{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
{ RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
#define CAN_ELIMINATE(FROM, TO) \
((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
? ! frame_pointer_needed \
: (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
: 1)
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
#define HAVE_PRE_DECREMENT 1
#define HAVE_PRE_INCREMENT 1
#define REGNO_OK_FOR_INDEX_P(REGNO) \
((REGNO) < FIRST_PSEUDO_REGISTER \
? (REGNO) <= 31 || (REGNO) == 67 \
: (reg_renumber[REGNO] >= 0 \
&& (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
#define REGNO_OK_FOR_BASE_P(REGNO) \
((REGNO) < FIRST_PSEUDO_REGISTER \
? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
: (reg_renumber[REGNO] > 0 \
&& (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
#define MAX_REGS_PER_ADDRESS 2
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
|| GET_CODE (X) == HIGH)
#define LEGITIMATE_CONSTANT_P(X) \
(((GET_CODE (X) != CONST_DOUBLE \
&& GET_CODE (X) != CONST_VECTOR) \
|| GET_MODE (X) == VOIDmode \
|| (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
|| easy_fp_constant (X, GET_MODE (X)) \
|| easy_vector_constant (X, GET_MODE (X))) \
&& !rs6000_tls_referenced_p (X))
#ifdef REG_OK_STRICT
# define REG_OK_STRICT_FLAG 1
#else
# define REG_OK_STRICT_FLAG 0
#endif
#define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
((! (STRICT) \
&& (REGNO (X) <= 31 \
|| REGNO (X) == ARG_POINTER_REGNUM \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
|| ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
#define INT_REG_OK_FOR_BASE_P(X, STRICT) \
(REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
#define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
#define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
goto ADDR; \
}
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
{ rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
if (result != NULL_RTX) \
{ \
(X) = result; \
goto WIN; \
} \
}
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
do { \
int win; \
(X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
(int)(TYPE), (IND_LEVELS), &win); \
if ( win ) \
goto WIN; \
} while (0)
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
do { \
if (rs6000_mode_dependent_address (ADDR)) \
goto LABEL; \
} while (0)
#define RS6000_PIC_OFFSET_TABLE_REGNUM 30
#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
#define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
#define CASE_VECTOR_MODE SImode
#define CASE_VECTOR_PC_RELATIVE 1
#define DEFAULT_SIGNED_CHAR 0
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
#define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
#define MAX_MOVE_MAX 8
#define SLOW_BYTE_ACCESS 1
#define WORD_REGISTER_OPERATIONS
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
#define SHORT_IMMEDIATES_SIGN_EXTEND
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
((VALUE) = ((MODE) == SImode ? 32 : 64))
#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
#define Pmode (TARGET_32BIT ? SImode : DImode)
#define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
#define FUNCTION_MODE SImode
#define NO_FUNCTION_CSE
#define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
#define SELECT_CC_MODE(OP,X,Y) \
(GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
: (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
: (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
? CCEQmode : CCmode))
#define REVERSIBLE_CC_MODE(MODE) 1
#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
extern GTY(()) rtx rs6000_compare_op0;
extern GTY(()) rtx rs6000_compare_op1;
extern int rs6000_compare_fp_p;
#define ASM_COMMENT_START " #"
extern int toc_initialized;
#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
{ \
output_toc (FILE, X, LABELNO, MODE); \
goto WIN; \
} \
}
#ifdef HAVE_GAS_WEAK
#define RS6000_WEAK 1
#else
#define RS6000_WEAK 0
#endif
#if RS6000_WEAK
#define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
do \
{ \
fputs ("\t.weak\t", (FILE)); \
RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
&& DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
{ \
if (TARGET_XCOFF) \
fputs ("[DS]", (FILE)); \
fputs ("\n\t.weak\t.", (FILE)); \
RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
} \
fputc ('\n', (FILE)); \
if (VAL) \
{ \
ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
&& DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
{ \
fputs ("\t.set\t.", (FILE)); \
RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
fputs (",.", (FILE)); \
RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
fputc ('\n', (FILE)); \
} \
} \
} \
while (0)
#endif
#undef ASM_OUTPUT_DEF_FROM_DECLS
#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
do \
{ \
const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
const char *name = IDENTIFIER_POINTER (TARGET); \
if (TREE_CODE (DECL) == FUNCTION_DECL \
&& DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
{ \
if (TREE_PUBLIC (DECL)) \
{ \
if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
{ \
fputs ("\t.globl\t.", FILE); \
RS6000_OUTPUT_BASENAME (FILE, alias); \
putc ('\n', FILE); \
} \
} \
else if (TARGET_XCOFF) \
{ \
fputs ("\t.lglobl\t.", FILE); \
RS6000_OUTPUT_BASENAME (FILE, alias); \
putc ('\n', FILE); \
} \
fputs ("\t.set\t.", FILE); \
RS6000_OUTPUT_BASENAME (FILE, alias); \
fputs (",.", FILE); \
RS6000_OUTPUT_BASENAME (FILE, name); \
fputc ('\n', FILE); \
} \
ASM_OUTPUT_DEF (FILE, alias, name); \
} \
while (0)
#define TARGET_ASM_FILE_START rs6000_file_start
#define ASM_APP_ON ""
#define ASM_APP_OFF ""
extern char rs6000_reg_names[][8];
#define REGISTER_NAMES \
{ \
&rs6000_reg_names[ 0][0], \
&rs6000_reg_names[ 1][0], \
&rs6000_reg_names[ 2][0], \
&rs6000_reg_names[ 3][0], \
&rs6000_reg_names[ 4][0], \
&rs6000_reg_names[ 5][0], \
&rs6000_reg_names[ 6][0], \
&rs6000_reg_names[ 7][0], \
&rs6000_reg_names[ 8][0], \
&rs6000_reg_names[ 9][0], \
&rs6000_reg_names[10][0], \
&rs6000_reg_names[11][0], \
&rs6000_reg_names[12][0], \
&rs6000_reg_names[13][0], \
&rs6000_reg_names[14][0], \
&rs6000_reg_names[15][0], \
&rs6000_reg_names[16][0], \
&rs6000_reg_names[17][0], \
&rs6000_reg_names[18][0], \
&rs6000_reg_names[19][0], \
&rs6000_reg_names[20][0], \
&rs6000_reg_names[21][0], \
&rs6000_reg_names[22][0], \
&rs6000_reg_names[23][0], \
&rs6000_reg_names[24][0], \
&rs6000_reg_names[25][0], \
&rs6000_reg_names[26][0], \
&rs6000_reg_names[27][0], \
&rs6000_reg_names[28][0], \
&rs6000_reg_names[29][0], \
&rs6000_reg_names[30][0], \
&rs6000_reg_names[31][0], \
\
&rs6000_reg_names[32][0], \
&rs6000_reg_names[33][0], \
&rs6000_reg_names[34][0], \
&rs6000_reg_names[35][0], \
&rs6000_reg_names[36][0], \
&rs6000_reg_names[37][0], \
&rs6000_reg_names[38][0], \
&rs6000_reg_names[39][0], \
&rs6000_reg_names[40][0], \
&rs6000_reg_names[41][0], \
&rs6000_reg_names[42][0], \
&rs6000_reg_names[43][0], \
&rs6000_reg_names[44][0], \
&rs6000_reg_names[45][0], \
&rs6000_reg_names[46][0], \
&rs6000_reg_names[47][0], \
&rs6000_reg_names[48][0], \
&rs6000_reg_names[49][0], \
&rs6000_reg_names[50][0], \
&rs6000_reg_names[51][0], \
&rs6000_reg_names[52][0], \
&rs6000_reg_names[53][0], \
&rs6000_reg_names[54][0], \
&rs6000_reg_names[55][0], \
&rs6000_reg_names[56][0], \
&rs6000_reg_names[57][0], \
&rs6000_reg_names[58][0], \
&rs6000_reg_names[59][0], \
&rs6000_reg_names[60][0], \
&rs6000_reg_names[61][0], \
&rs6000_reg_names[62][0], \
&rs6000_reg_names[63][0], \
\
&rs6000_reg_names[64][0], \
&rs6000_reg_names[65][0], \
&rs6000_reg_names[66][0], \
&rs6000_reg_names[67][0], \
\
&rs6000_reg_names[68][0], \
&rs6000_reg_names[69][0], \
&rs6000_reg_names[70][0], \
&rs6000_reg_names[71][0], \
&rs6000_reg_names[72][0], \
&rs6000_reg_names[73][0], \
&rs6000_reg_names[74][0], \
&rs6000_reg_names[75][0], \
\
&rs6000_reg_names[76][0], \
\
&rs6000_reg_names[77][0], \
&rs6000_reg_names[78][0], \
&rs6000_reg_names[79][0], \
&rs6000_reg_names[80][0], \
&rs6000_reg_names[81][0], \
&rs6000_reg_names[82][0], \
&rs6000_reg_names[83][0], \
&rs6000_reg_names[84][0], \
&rs6000_reg_names[85][0], \
&rs6000_reg_names[86][0], \
&rs6000_reg_names[87][0], \
&rs6000_reg_names[88][0], \
&rs6000_reg_names[89][0], \
&rs6000_reg_names[90][0], \
&rs6000_reg_names[91][0], \
&rs6000_reg_names[92][0], \
&rs6000_reg_names[93][0], \
&rs6000_reg_names[94][0], \
&rs6000_reg_names[95][0], \
&rs6000_reg_names[96][0], \
&rs6000_reg_names[97][0], \
&rs6000_reg_names[98][0], \
&rs6000_reg_names[99][0], \
&rs6000_reg_names[100][0], \
&rs6000_reg_names[101][0], \
&rs6000_reg_names[102][0], \
&rs6000_reg_names[103][0], \
&rs6000_reg_names[104][0], \
&rs6000_reg_names[105][0], \
&rs6000_reg_names[106][0], \
&rs6000_reg_names[107][0], \
&rs6000_reg_names[108][0], \
&rs6000_reg_names[109][0], \
&rs6000_reg_names[110][0], \
&rs6000_reg_names[111][0], \
&rs6000_reg_names[112][0], \
}
#define ADDITIONAL_REGISTER_NAMES \
{{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
{"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
{"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
{"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
{"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
{"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
{"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
{"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
{"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
{"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
{"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
{"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
{"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
{"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
{"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
{"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
{"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
{"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
{"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
{"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
{"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
{"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
{"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
{"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
{"vrsave", 109}, {"vscr", 110}, \
{"spe_acc", 111}, {"spefscr", 112}, \
\
{"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
{"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
{"cc", 68}, {"sp", 1}, {"toc", 2} }
#define RS6000_CALL_GLUE "cror 31,31,31"
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
do { char buf[100]; \
fputs ("\t.long ", FILE); \
ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
assemble_name (FILE, buf); \
putc ('-', FILE); \
ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
assemble_name (FILE, buf); \
putc ('\n', FILE); \
} while (0)
#define ASM_OUTPUT_ALIGN(FILE,LOG) \
if ((LOG) != 0) \
fprintf (FILE, "\t.align %d\n", (LOG))
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
((CODE) == '.' || (CODE) == '&')
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
#define PREDICATE_CODES \
{"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
LABEL_REF, SUBREG, REG, MEM}}, \
{"any_parallel_operand", {PARALLEL}}, \
{"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
LABEL_REF, SUBREG, REG, MEM}}, \
{"short_cint_operand", {CONST_INT}}, \
{"u_short_cint_operand", {CONST_INT}}, \
{"non_short_cint_operand", {CONST_INT}}, \
{"exact_log2_cint_operand", {CONST_INT}}, \
{"gpc_reg_operand", {SUBREG, REG}}, \
{"cc_reg_operand", {SUBREG, REG}}, \
{"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
{"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
{"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
{"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
{"easy_fp_constant", {CONST_DOUBLE}}, \
{"easy_vector_constant", {CONST_VECTOR}}, \
{"easy_vector_constant_add_self", {CONST_VECTOR}}, \
{"zero_fp_constant", {CONST_DOUBLE}}, \
{"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
{"lwa_operand", {SUBREG, MEM, REG}}, \
{"volatile_mem_operand", {MEM}}, \
{"offsettable_mem_operand", {MEM}}, \
{"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
{"add_operand", {SUBREG, REG, CONST_INT}}, \
{"non_add_cint_operand", {CONST_INT}}, \
{"and_operand", {SUBREG, REG, CONST_INT}}, \
{"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
{"and64_2_operand", {SUBREG, REG, CONST_INT}}, \
{"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
{"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
{"mask_operand", {CONST_INT}}, \
{"mask_operand_wrap", {CONST_INT}}, \
{"mask64_operand", {CONST_INT}}, \
{"mask64_2_operand", {CONST_INT}}, \
{"count_register_operand", {REG}}, \
{"xer_operand", {REG}}, \
{"symbol_ref_operand", {SYMBOL_REF}}, \
{"rs6000_tls_symbol_ref", {SYMBOL_REF}}, \
{"call_operand", {SYMBOL_REF, REG}}, \
{"current_file_function_operand", {SYMBOL_REF}}, \
{"input_operand", {SUBREG, MEM, REG, CONST_INT, \
CONST_DOUBLE, SYMBOL_REF}}, \
{"rs6000_nonimmediate_operand", {SUBREG, MEM, REG}}, \
{"load_multiple_operation", {PARALLEL}}, \
{"store_multiple_operation", {PARALLEL}}, \
{"lmw_operation", {PARALLEL}}, \
{"stmw_operation", {PARALLEL}}, \
{"vrsave_operation", {PARALLEL}}, \
{"save_world_operation", {PARALLEL}}, \
{"restore_world_operation", {PARALLEL}}, \
{"mfcr_operation", {PARALLEL}}, \
{"mtcrf_operation", {PARALLEL}}, \
{"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
GT, LEU, LTU, GEU, GTU, \
UNORDERED, ORDERED, \
UNGE, UNLE }}, \
{"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
UNORDERED }}, \
{"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
GT, LEU, LTU, GEU, GTU, \
UNORDERED, ORDERED, \
UNGE, UNLE }}, \
{"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
GT, LEU, LTU, GEU, GTU}}, \
{"boolean_operator", {AND, IOR, XOR}}, \
{"boolean_or_operator", {IOR, XOR}}, \
{"altivec_register_operand", {REG}}, \
{"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
extern int flag_pic;
extern int optimize;
extern int flag_expensive_optimizations;
extern int frame_pointer_needed;
enum rs6000_builtins
{
ALTIVEC_BUILTIN_ST_INTERNAL_4si,
ALTIVEC_BUILTIN_LD_INTERNAL_4si,
ALTIVEC_BUILTIN_ST_INTERNAL_8hi,
ALTIVEC_BUILTIN_LD_INTERNAL_8hi,
ALTIVEC_BUILTIN_ST_INTERNAL_16qi,
ALTIVEC_BUILTIN_LD_INTERNAL_16qi,
ALTIVEC_BUILTIN_ST_INTERNAL_4sf,
ALTIVEC_BUILTIN_LD_INTERNAL_4sf,
ALTIVEC_BUILTIN_VADDUBM,
ALTIVEC_BUILTIN_VADDUHM,
ALTIVEC_BUILTIN_VADDUWM,
ALTIVEC_BUILTIN_VADDFP,
ALTIVEC_BUILTIN_VADDCUW,
ALTIVEC_BUILTIN_VADDUBS,
ALTIVEC_BUILTIN_VADDSBS,
ALTIVEC_BUILTIN_VADDUHS,
ALTIVEC_BUILTIN_VADDSHS,
ALTIVEC_BUILTIN_VADDUWS,
ALTIVEC_BUILTIN_VADDSWS,
ALTIVEC_BUILTIN_VAND,
ALTIVEC_BUILTIN_VANDC,
ALTIVEC_BUILTIN_VAVGUB,
ALTIVEC_BUILTIN_VAVGSB,
ALTIVEC_BUILTIN_VAVGUH,
ALTIVEC_BUILTIN_VAVGSH,
ALTIVEC_BUILTIN_VAVGUW,
ALTIVEC_BUILTIN_VAVGSW,
ALTIVEC_BUILTIN_VCFUX,
ALTIVEC_BUILTIN_VCFSX,
ALTIVEC_BUILTIN_VCTSXS,
ALTIVEC_BUILTIN_VCTUXS,
ALTIVEC_BUILTIN_VCMPBFP,
ALTIVEC_BUILTIN_VCMPEQUB,
ALTIVEC_BUILTIN_VCMPEQUH,
ALTIVEC_BUILTIN_VCMPEQUW,
ALTIVEC_BUILTIN_VCMPEQFP,
ALTIVEC_BUILTIN_VCMPGEFP,
ALTIVEC_BUILTIN_VCMPGTUB,
ALTIVEC_BUILTIN_VCMPGTSB,
ALTIVEC_BUILTIN_VCMPGTUH,
ALTIVEC_BUILTIN_VCMPGTSH,
ALTIVEC_BUILTIN_VCMPGTUW,
ALTIVEC_BUILTIN_VCMPGTSW,
ALTIVEC_BUILTIN_VCMPGTFP,
ALTIVEC_BUILTIN_VEXPTEFP,
ALTIVEC_BUILTIN_VLOGEFP,
ALTIVEC_BUILTIN_VMADDFP,
ALTIVEC_BUILTIN_VMAXUB,
ALTIVEC_BUILTIN_VMAXSB,
ALTIVEC_BUILTIN_VMAXUH,
ALTIVEC_BUILTIN_VMAXSH,
ALTIVEC_BUILTIN_VMAXUW,
ALTIVEC_BUILTIN_VMAXSW,
ALTIVEC_BUILTIN_VMAXFP,
ALTIVEC_BUILTIN_VMHADDSHS,
ALTIVEC_BUILTIN_VMHRADDSHS,
ALTIVEC_BUILTIN_VMLADDUHM,
ALTIVEC_BUILTIN_VMRGHB,
ALTIVEC_BUILTIN_VMRGHH,
ALTIVEC_BUILTIN_VMRGHW,
ALTIVEC_BUILTIN_VMRGLB,
ALTIVEC_BUILTIN_VMRGLH,
ALTIVEC_BUILTIN_VMRGLW,
ALTIVEC_BUILTIN_VMSUMUBM,
ALTIVEC_BUILTIN_VMSUMMBM,
ALTIVEC_BUILTIN_VMSUMUHM,
ALTIVEC_BUILTIN_VMSUMSHM,
ALTIVEC_BUILTIN_VMSUMUHS,
ALTIVEC_BUILTIN_VMSUMSHS,
ALTIVEC_BUILTIN_VMINUB,
ALTIVEC_BUILTIN_VMINSB,
ALTIVEC_BUILTIN_VMINUH,
ALTIVEC_BUILTIN_VMINSH,
ALTIVEC_BUILTIN_VMINUW,
ALTIVEC_BUILTIN_VMINSW,
ALTIVEC_BUILTIN_VMINFP,
ALTIVEC_BUILTIN_VMULEUB,
ALTIVEC_BUILTIN_VMULESB,
ALTIVEC_BUILTIN_VMULEUH,
ALTIVEC_BUILTIN_VMULESH,
ALTIVEC_BUILTIN_VMULOUB,
ALTIVEC_BUILTIN_VMULOSB,
ALTIVEC_BUILTIN_VMULOUH,
ALTIVEC_BUILTIN_VMULOSH,
ALTIVEC_BUILTIN_VNMSUBFP,
ALTIVEC_BUILTIN_VNOR,
ALTIVEC_BUILTIN_VOR,
ALTIVEC_BUILTIN_VSEL_4SI,
ALTIVEC_BUILTIN_VSEL_4SF,
ALTIVEC_BUILTIN_VSEL_8HI,
ALTIVEC_BUILTIN_VSEL_16QI,
ALTIVEC_BUILTIN_VPERM_4SI,
ALTIVEC_BUILTIN_VPERM_4SF,
ALTIVEC_BUILTIN_VPERM_8HI,
ALTIVEC_BUILTIN_VPERM_16QI,
ALTIVEC_BUILTIN_VPKUHUM,
ALTIVEC_BUILTIN_VPKUWUM,
ALTIVEC_BUILTIN_VPKPX,
ALTIVEC_BUILTIN_VPKUHSS,
ALTIVEC_BUILTIN_VPKSHSS,
ALTIVEC_BUILTIN_VPKUWSS,
ALTIVEC_BUILTIN_VPKSWSS,
ALTIVEC_BUILTIN_VPKUHUS,
ALTIVEC_BUILTIN_VPKSHUS,
ALTIVEC_BUILTIN_VPKUWUS,
ALTIVEC_BUILTIN_VPKSWUS,
ALTIVEC_BUILTIN_VREFP,
ALTIVEC_BUILTIN_VRFIM,
ALTIVEC_BUILTIN_VRFIN,
ALTIVEC_BUILTIN_VRFIP,
ALTIVEC_BUILTIN_VRFIZ,
ALTIVEC_BUILTIN_VRLB,
ALTIVEC_BUILTIN_VRLH,
ALTIVEC_BUILTIN_VRLW,
ALTIVEC_BUILTIN_VRSQRTEFP,
ALTIVEC_BUILTIN_VSLB,
ALTIVEC_BUILTIN_VSLH,
ALTIVEC_BUILTIN_VSLW,
ALTIVEC_BUILTIN_VSL,
ALTIVEC_BUILTIN_VSLO,
ALTIVEC_BUILTIN_VSPLTB,
ALTIVEC_BUILTIN_VSPLTH,
ALTIVEC_BUILTIN_VSPLTW,
ALTIVEC_BUILTIN_VSPLTISB,
ALTIVEC_BUILTIN_VSPLTISH,
ALTIVEC_BUILTIN_VSPLTISW,
ALTIVEC_BUILTIN_VSRB,
ALTIVEC_BUILTIN_VSRH,
ALTIVEC_BUILTIN_VSRW,
ALTIVEC_BUILTIN_VSRAB,
ALTIVEC_BUILTIN_VSRAH,
ALTIVEC_BUILTIN_VSRAW,
ALTIVEC_BUILTIN_VSR,
ALTIVEC_BUILTIN_VSRO,
ALTIVEC_BUILTIN_VSUBUBM,
ALTIVEC_BUILTIN_VSUBUHM,
ALTIVEC_BUILTIN_VSUBUWM,
ALTIVEC_BUILTIN_VSUBFP,
ALTIVEC_BUILTIN_VSUBCUW,
ALTIVEC_BUILTIN_VSUBUBS,
ALTIVEC_BUILTIN_VSUBSBS,
ALTIVEC_BUILTIN_VSUBUHS,
ALTIVEC_BUILTIN_VSUBSHS,
ALTIVEC_BUILTIN_VSUBUWS,
ALTIVEC_BUILTIN_VSUBSWS,
ALTIVEC_BUILTIN_VSUM4UBS,
ALTIVEC_BUILTIN_VSUM4SBS,
ALTIVEC_BUILTIN_VSUM4SHS,
ALTIVEC_BUILTIN_VSUM2SWS,
ALTIVEC_BUILTIN_VSUMSWS,
ALTIVEC_BUILTIN_VXOR,
ALTIVEC_BUILTIN_VSLDOI_16QI,
ALTIVEC_BUILTIN_VSLDOI_8HI,
ALTIVEC_BUILTIN_VSLDOI_4SI,
ALTIVEC_BUILTIN_VSLDOI_4SF,
ALTIVEC_BUILTIN_VUPKHSB,
ALTIVEC_BUILTIN_VUPKHPX,
ALTIVEC_BUILTIN_VUPKHSH,
ALTIVEC_BUILTIN_VUPKLSB,
ALTIVEC_BUILTIN_VUPKLPX,
ALTIVEC_BUILTIN_VUPKLSH,
ALTIVEC_BUILTIN_MTVSCR,
ALTIVEC_BUILTIN_MFVSCR,
ALTIVEC_BUILTIN_DSSALL,
ALTIVEC_BUILTIN_DSS,
ALTIVEC_BUILTIN_LVSL,
ALTIVEC_BUILTIN_LVSR,
ALTIVEC_BUILTIN_DSTT,
ALTIVEC_BUILTIN_DSTST,
ALTIVEC_BUILTIN_DSTSTT,
ALTIVEC_BUILTIN_DST,
ALTIVEC_BUILTIN_LVEBX,
ALTIVEC_BUILTIN_LVEHX,
ALTIVEC_BUILTIN_LVEWX,
ALTIVEC_BUILTIN_LVXL,
ALTIVEC_BUILTIN_LVX,
ALTIVEC_BUILTIN_STVX,
ALTIVEC_BUILTIN_STVEBX,
ALTIVEC_BUILTIN_STVEHX,
ALTIVEC_BUILTIN_STVEWX,
ALTIVEC_BUILTIN_STVXL,
ALTIVEC_BUILTIN_VCMPBFP_P,
ALTIVEC_BUILTIN_VCMPEQFP_P,
ALTIVEC_BUILTIN_VCMPEQUB_P,
ALTIVEC_BUILTIN_VCMPEQUH_P,
ALTIVEC_BUILTIN_VCMPEQUW_P,
ALTIVEC_BUILTIN_VCMPGEFP_P,
ALTIVEC_BUILTIN_VCMPGTFP_P,
ALTIVEC_BUILTIN_VCMPGTSB_P,
ALTIVEC_BUILTIN_VCMPGTSH_P,
ALTIVEC_BUILTIN_VCMPGTSW_P,
ALTIVEC_BUILTIN_VCMPGTUB_P,
ALTIVEC_BUILTIN_VCMPGTUH_P,
ALTIVEC_BUILTIN_VCMPGTUW_P,
ALTIVEC_BUILTIN_ABSS_V4SI,
ALTIVEC_BUILTIN_ABSS_V8HI,
ALTIVEC_BUILTIN_ABSS_V16QI,
ALTIVEC_BUILTIN_ABS_V4SI,
ALTIVEC_BUILTIN_ABS_V4SF,
ALTIVEC_BUILTIN_ABS_V8HI,
ALTIVEC_BUILTIN_ABS_V16QI,
ALTIVEC_BUILTIN_COMPILETIME_ERROR,
ALTIVEC_BUILTIN_MASK_FOR_LOAD,
ALTIVEC_BUILTIN_MASK_FOR_STORE,
SPE_BUILTIN_EVADDW,
SPE_BUILTIN_EVAND,
SPE_BUILTIN_EVANDC,
SPE_BUILTIN_EVDIVWS,
SPE_BUILTIN_EVDIVWU,
SPE_BUILTIN_EVEQV,
SPE_BUILTIN_EVFSADD,
SPE_BUILTIN_EVFSDIV,
SPE_BUILTIN_EVFSMUL,
SPE_BUILTIN_EVFSSUB,
SPE_BUILTIN_EVLDDX,
SPE_BUILTIN_EVLDHX,
SPE_BUILTIN_EVLDWX,
SPE_BUILTIN_EVLHHESPLATX,
SPE_BUILTIN_EVLHHOSSPLATX,
SPE_BUILTIN_EVLHHOUSPLATX,
SPE_BUILTIN_EVLWHEX,
SPE_BUILTIN_EVLWHOSX,
SPE_BUILTIN_EVLWHOUX,
SPE_BUILTIN_EVLWHSPLATX,
SPE_BUILTIN_EVLWWSPLATX,
SPE_BUILTIN_EVMERGEHI,
SPE_BUILTIN_EVMERGEHILO,
SPE_BUILTIN_EVMERGELO,
SPE_BUILTIN_EVMERGELOHI,
SPE_BUILTIN_EVMHEGSMFAA,
SPE_BUILTIN_EVMHEGSMFAN,
SPE_BUILTIN_EVMHEGSMIAA,
SPE_BUILTIN_EVMHEGSMIAN,
SPE_BUILTIN_EVMHEGUMIAA,
SPE_BUILTIN_EVMHEGUMIAN,
SPE_BUILTIN_EVMHESMF,
SPE_BUILTIN_EVMHESMFA,
SPE_BUILTIN_EVMHESMFAAW,
SPE_BUILTIN_EVMHESMFANW,
SPE_BUILTIN_EVMHESMI,
SPE_BUILTIN_EVMHESMIA,
SPE_BUILTIN_EVMHESMIAAW,
SPE_BUILTIN_EVMHESMIANW,
SPE_BUILTIN_EVMHESSF,
SPE_BUILTIN_EVMHESSFA,
SPE_BUILTIN_EVMHESSFAAW,
SPE_BUILTIN_EVMHESSFANW,
SPE_BUILTIN_EVMHESSIAAW,
SPE_BUILTIN_EVMHESSIANW,
SPE_BUILTIN_EVMHEUMI,
SPE_BUILTIN_EVMHEUMIA,
SPE_BUILTIN_EVMHEUMIAAW,
SPE_BUILTIN_EVMHEUMIANW,
SPE_BUILTIN_EVMHEUSIAAW,
SPE_BUILTIN_EVMHEUSIANW,
SPE_BUILTIN_EVMHOGSMFAA,
SPE_BUILTIN_EVMHOGSMFAN,
SPE_BUILTIN_EVMHOGSMIAA,
SPE_BUILTIN_EVMHOGSMIAN,
SPE_BUILTIN_EVMHOGUMIAA,
SPE_BUILTIN_EVMHOGUMIAN,
SPE_BUILTIN_EVMHOSMF,
SPE_BUILTIN_EVMHOSMFA,
SPE_BUILTIN_EVMHOSMFAAW,
SPE_BUILTIN_EVMHOSMFANW,
SPE_BUILTIN_EVMHOSMI,
SPE_BUILTIN_EVMHOSMIA,
SPE_BUILTIN_EVMHOSMIAAW,
SPE_BUILTIN_EVMHOSMIANW,
SPE_BUILTIN_EVMHOSSF,
SPE_BUILTIN_EVMHOSSFA,
SPE_BUILTIN_EVMHOSSFAAW,
SPE_BUILTIN_EVMHOSSFANW,
SPE_BUILTIN_EVMHOSSIAAW,
SPE_BUILTIN_EVMHOSSIANW,
SPE_BUILTIN_EVMHOUMI,
SPE_BUILTIN_EVMHOUMIA,
SPE_BUILTIN_EVMHOUMIAAW,
SPE_BUILTIN_EVMHOUMIANW,
SPE_BUILTIN_EVMHOUSIAAW,
SPE_BUILTIN_EVMHOUSIANW,
SPE_BUILTIN_EVMWHSMF,
SPE_BUILTIN_EVMWHSMFA,
SPE_BUILTIN_EVMWHSMI,
SPE_BUILTIN_EVMWHSMIA,
SPE_BUILTIN_EVMWHSSF,
SPE_BUILTIN_EVMWHSSFA,
SPE_BUILTIN_EVMWHUMI,
SPE_BUILTIN_EVMWHUMIA,
SPE_BUILTIN_EVMWLSMIAAW,
SPE_BUILTIN_EVMWLSMIANW,
SPE_BUILTIN_EVMWLSSIAAW,
SPE_BUILTIN_EVMWLSSIANW,
SPE_BUILTIN_EVMWLUMI,
SPE_BUILTIN_EVMWLUMIA,
SPE_BUILTIN_EVMWLUMIAAW,
SPE_BUILTIN_EVMWLUMIANW,
SPE_BUILTIN_EVMWLUSIAAW,
SPE_BUILTIN_EVMWLUSIANW,
SPE_BUILTIN_EVMWSMF,
SPE_BUILTIN_EVMWSMFA,
SPE_BUILTIN_EVMWSMFAA,
SPE_BUILTIN_EVMWSMFAN,
SPE_BUILTIN_EVMWSMI,
SPE_BUILTIN_EVMWSMIA,
SPE_BUILTIN_EVMWSMIAA,
SPE_BUILTIN_EVMWSMIAN,
SPE_BUILTIN_EVMWHSSFAA,
SPE_BUILTIN_EVMWSSF,
SPE_BUILTIN_EVMWSSFA,
SPE_BUILTIN_EVMWSSFAA,
SPE_BUILTIN_EVMWSSFAN,
SPE_BUILTIN_EVMWUMI,
SPE_BUILTIN_EVMWUMIA,
SPE_BUILTIN_EVMWUMIAA,
SPE_BUILTIN_EVMWUMIAN,
SPE_BUILTIN_EVNAND,
SPE_BUILTIN_EVNOR,
SPE_BUILTIN_EVOR,
SPE_BUILTIN_EVORC,
SPE_BUILTIN_EVRLW,
SPE_BUILTIN_EVSLW,
SPE_BUILTIN_EVSRWS,
SPE_BUILTIN_EVSRWU,
SPE_BUILTIN_EVSTDDX,
SPE_BUILTIN_EVSTDHX,
SPE_BUILTIN_EVSTDWX,
SPE_BUILTIN_EVSTWHEX,
SPE_BUILTIN_EVSTWHOX,
SPE_BUILTIN_EVSTWWEX,
SPE_BUILTIN_EVSTWWOX,
SPE_BUILTIN_EVSUBFW,
SPE_BUILTIN_EVXOR,
SPE_BUILTIN_EVABS,
SPE_BUILTIN_EVADDSMIAAW,
SPE_BUILTIN_EVADDSSIAAW,
SPE_BUILTIN_EVADDUMIAAW,
SPE_BUILTIN_EVADDUSIAAW,
SPE_BUILTIN_EVCNTLSW,
SPE_BUILTIN_EVCNTLZW,
SPE_BUILTIN_EVEXTSB,
SPE_BUILTIN_EVEXTSH,
SPE_BUILTIN_EVFSABS,
SPE_BUILTIN_EVFSCFSF,
SPE_BUILTIN_EVFSCFSI,
SPE_BUILTIN_EVFSCFUF,
SPE_BUILTIN_EVFSCFUI,
SPE_BUILTIN_EVFSCTSF,
SPE_BUILTIN_EVFSCTSI,
SPE_BUILTIN_EVFSCTSIZ,
SPE_BUILTIN_EVFSCTUF,
SPE_BUILTIN_EVFSCTUI,
SPE_BUILTIN_EVFSCTUIZ,
SPE_BUILTIN_EVFSNABS,
SPE_BUILTIN_EVFSNEG,
SPE_BUILTIN_EVMRA,
SPE_BUILTIN_EVNEG,
SPE_BUILTIN_EVRNDW,
SPE_BUILTIN_EVSUBFSMIAAW,
SPE_BUILTIN_EVSUBFSSIAAW,
SPE_BUILTIN_EVSUBFUMIAAW,
SPE_BUILTIN_EVSUBFUSIAAW,
SPE_BUILTIN_EVADDIW,
SPE_BUILTIN_EVLDD,
SPE_BUILTIN_EVLDH,
SPE_BUILTIN_EVLDW,
SPE_BUILTIN_EVLHHESPLAT,
SPE_BUILTIN_EVLHHOSSPLAT,
SPE_BUILTIN_EVLHHOUSPLAT,
SPE_BUILTIN_EVLWHE,
SPE_BUILTIN_EVLWHOS,
SPE_BUILTIN_EVLWHOU,
SPE_BUILTIN_EVLWHSPLAT,
SPE_BUILTIN_EVLWWSPLAT,
SPE_BUILTIN_EVRLWI,
SPE_BUILTIN_EVSLWI,
SPE_BUILTIN_EVSRWIS,
SPE_BUILTIN_EVSRWIU,
SPE_BUILTIN_EVSTDD,
SPE_BUILTIN_EVSTDH,
SPE_BUILTIN_EVSTDW,
SPE_BUILTIN_EVSTWHE,
SPE_BUILTIN_EVSTWHO,
SPE_BUILTIN_EVSTWWE,
SPE_BUILTIN_EVSTWWO,
SPE_BUILTIN_EVSUBIFW,
SPE_BUILTIN_EVCMPEQ,
SPE_BUILTIN_EVCMPGTS,
SPE_BUILTIN_EVCMPGTU,
SPE_BUILTIN_EVCMPLTS,
SPE_BUILTIN_EVCMPLTU,
SPE_BUILTIN_EVFSCMPEQ,
SPE_BUILTIN_EVFSCMPGT,
SPE_BUILTIN_EVFSCMPLT,
SPE_BUILTIN_EVFSTSTEQ,
SPE_BUILTIN_EVFSTSTGT,
SPE_BUILTIN_EVFSTSTLT,
SPE_BUILTIN_EVSEL_CMPEQ,
SPE_BUILTIN_EVSEL_CMPGTS,
SPE_BUILTIN_EVSEL_CMPGTU,
SPE_BUILTIN_EVSEL_CMPLTS,
SPE_BUILTIN_EVSEL_CMPLTU,
SPE_BUILTIN_EVSEL_FSCMPEQ,
SPE_BUILTIN_EVSEL_FSCMPGT,
SPE_BUILTIN_EVSEL_FSCMPLT,
SPE_BUILTIN_EVSEL_FSTSTEQ,
SPE_BUILTIN_EVSEL_FSTSTGT,
SPE_BUILTIN_EVSEL_FSTSTLT,
SPE_BUILTIN_EVSPLATFI,
SPE_BUILTIN_EVSPLATI,
SPE_BUILTIN_EVMWHSSMAA,
SPE_BUILTIN_EVMWHSMFAA,
SPE_BUILTIN_EVMWHSMIAA,
SPE_BUILTIN_EVMWHUSIAA,
SPE_BUILTIN_EVMWHUMIAA,
SPE_BUILTIN_EVMWHSSFAN,
SPE_BUILTIN_EVMWHSSIAN,
SPE_BUILTIN_EVMWHSMFAN,
SPE_BUILTIN_EVMWHSMIAN,
SPE_BUILTIN_EVMWHUSIAN,
SPE_BUILTIN_EVMWHUMIAN,
SPE_BUILTIN_EVMWHGSSFAA,
SPE_BUILTIN_EVMWHGSMFAA,
SPE_BUILTIN_EVMWHGSMIAA,
SPE_BUILTIN_EVMWHGUMIAA,
SPE_BUILTIN_EVMWHGSSFAN,
SPE_BUILTIN_EVMWHGSMFAN,
SPE_BUILTIN_EVMWHGSMIAN,
SPE_BUILTIN_EVMWHGUMIAN,
SPE_BUILTIN_MTSPEFSCR,
SPE_BUILTIN_MFSPEFSCR,
SPE_BUILTIN_BRINC
};