#include "sysdep.h"
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
#include "xstormy16-desc.h"
#include "xstormy16-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"
static const CGEN_ATTR_ENTRY bool_attr[] =
{
{ "#f", 0 },
{ "#t", 1 },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
{
{ "base", MACH_BASE },
{ "xstormy16", MACH_XSTORMY16 },
{ "max", MACH_MAX },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
{
{ "xstormy16", ISA_XSTORMY16 },
{ "max", ISA_MAX },
{ 0, 0 }
};
const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
{ "RESERVED", &bool_attr[0], &bool_attr[0] },
{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
{ "SIGNED", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
{ "PC", &bool_attr[0], &bool_attr[0] },
{ "PROFILE", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
{ "SIGNED", &bool_attr[0], &bool_attr[0] },
{ "NEGATIVE", &bool_attr[0], &bool_attr[0] },
{ "RELAX", &bool_attr[0], &bool_attr[0] },
{ "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "ALIAS", &bool_attr[0], &bool_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
{ "COND-CTI", &bool_attr[0], &bool_attr[0] },
{ "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
{ "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
{ "RELAXABLE", &bool_attr[0], &bool_attr[0] },
{ "RELAXED", &bool_attr[0], &bool_attr[0] },
{ "NO-DIS", &bool_attr[0], &bool_attr[0] },
{ "PBB", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
static const CGEN_ISA xstormy16_cgen_isa_table[] = {
{ "xstormy16", 32, 32, 16, 32 },
{ 0, 0, 0, 0, 0 }
};
static const CGEN_MACH xstormy16_cgen_mach_table[] = {
{ "xstormy16", "xstormy16", MACH_XSTORMY16, 16 },
{ 0, 0, 0, 0 }
};
static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] =
{
{ "r0", 0, {0, {0}}, 0, 0 },
{ "r1", 1, {0, {0}}, 0, 0 },
{ "r2", 2, {0, {0}}, 0, 0 },
{ "r3", 3, {0, {0}}, 0, 0 },
{ "r4", 4, {0, {0}}, 0, 0 },
{ "r5", 5, {0, {0}}, 0, 0 },
{ "r6", 6, {0, {0}}, 0, 0 },
{ "r7", 7, {0, {0}}, 0, 0 },
{ "r8", 8, {0, {0}}, 0, 0 },
{ "r9", 9, {0, {0}}, 0, 0 },
{ "r10", 10, {0, {0}}, 0, 0 },
{ "r11", 11, {0, {0}}, 0, 0 },
{ "r12", 12, {0, {0}}, 0, 0 },
{ "r13", 13, {0, {0}}, 0, 0 },
{ "r14", 14, {0, {0}}, 0, 0 },
{ "r15", 15, {0, {0}}, 0, 0 },
{ "psw", 14, {0, {0}}, 0, 0 },
{ "sp", 15, {0, {0}}, 0, 0 }
};
CGEN_KEYWORD xstormy16_cgen_opval_gr_names =
{
& xstormy16_cgen_opval_gr_names_entries[0],
18,
0, 0, 0, 0, ""
};
static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] =
{
{ "r8", 0, {0, {0}}, 0, 0 },
{ "r9", 1, {0, {0}}, 0, 0 },
{ "r10", 2, {0, {0}}, 0, 0 },
{ "r11", 3, {0, {0}}, 0, 0 },
{ "r12", 4, {0, {0}}, 0, 0 },
{ "r13", 5, {0, {0}}, 0, 0 },
{ "r14", 6, {0, {0}}, 0, 0 },
{ "r15", 7, {0, {0}}, 0, 0 },
{ "psw", 6, {0, {0}}, 0, 0 },
{ "sp", 7, {0, {0}}, 0, 0 }
};
CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names =
{
& xstormy16_cgen_opval_gr_Rb_names_entries[0],
10,
0, 0, 0, 0, ""
};
static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] =
{
{ "ge", 0, {0, {0}}, 0, 0 },
{ "nc", 1, {0, {0}}, 0, 0 },
{ "lt", 2, {0, {0}}, 0, 0 },
{ "c", 3, {0, {0}}, 0, 0 },
{ "gt", 4, {0, {0}}, 0, 0 },
{ "hi", 5, {0, {0}}, 0, 0 },
{ "le", 6, {0, {0}}, 0, 0 },
{ "ls", 7, {0, {0}}, 0, 0 },
{ "pl", 8, {0, {0}}, 0, 0 },
{ "nv", 9, {0, {0}}, 0, 0 },
{ "mi", 10, {0, {0}}, 0, 0 },
{ "v", 11, {0, {0}}, 0, 0 },
{ "nz.b", 12, {0, {0}}, 0, 0 },
{ "nz", 13, {0, {0}}, 0, 0 },
{ "z.b", 14, {0, {0}}, 0, 0 },
{ "z", 15, {0, {0}}, 0, 0 }
};
CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond =
{
& xstormy16_cgen_opval_h_branchcond_entries[0],
16,
0, 0, 0, 0, ""
};
static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] =
{
{ ".b", 0, {0, {0}}, 0, 0 },
{ ".w", 1, {0, {0}}, 0, 0 },
{ "", 1, {0, {0}}, 0, 0 }
};
CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize =
{
& xstormy16_cgen_opval_h_wordsize_entries[0],
3,
0, 0, 0, 0, ""
};
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_HW_##a)
#else
#define A(a) (1 << CGEN_HW_a)
#endif
const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
{
{ "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { (1<<MACH_BASE) } } },
{ "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { (1<<MACH_BASE) } } },
{ "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { (1<<MACH_BASE) } } },
{ 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
};
#undef A
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_IFLD_##a)
#else
#define A(a) (1 << CGEN_IFLD_a)
#endif
const CGEN_IFLD xstormy16_cgen_ifld_table[] =
{
{ XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
{ XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
{ XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
{ XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
{ XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
{ XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
{ XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
{ XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
{ XSTORMY16_F_ABS24, "f-abs24", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, 0, {0, {0}} }
};
#undef A
const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_1] } },
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_2] } },
{ 0, { (const PTR) 0 } }
};
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_OPERAND_##a)
#else
#define A(a) (1 << CGEN_OPERAND_a)
#endif
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define OPERAND(op) XSTORMY16_OPERAND_##op
#else
#define OPERAND(op) XSTORMY16_OPERAND_op
#endif
const CGEN_OPERAND xstormy16_cgen_operand_table[] =
{
{ "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } },
{ 0, { (1<<MACH_BASE) } } },
{ "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } },
{ 0, { (1<<MACH_BASE) } } },
{ "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } },
{ 0, { (1<<MACH_BASE) } } },
{ "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } },
{ 0, { (1<<MACH_BASE) } } },
{ "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } },
{ 0, { (1<<MACH_BASE) } } },
{ "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } },
{ 0, { (1<<MACH_BASE) } } },
{ "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } },
{ 0, { (1<<MACH_BASE) } } },
{ "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } },
{ 0, { (1<<MACH_BASE) } } },
{ "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } },
{ 0, { (1<<MACH_BASE) } } },
{ "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } },
{ 0, { (1<<MACH_BASE) } } },
{ "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } },
{ 0, { (1<<MACH_BASE) } } },
{ "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } },
{ 0, { (1<<MACH_BASE) } } },
{ "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } },
{ 0, { (1<<MACH_BASE) } } },
{ "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
{ 0, { (1<<MACH_BASE) } } },
{ "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } },
{ 0, { (1<<MACH_BASE) } } },
{ "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } },
{ 0, { (1<<MACH_BASE) } } },
{ "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
{ "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } },
{ 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
{ "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } },
{ 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
{ "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
{ "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
{ "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
{ "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
{ 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
{ "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
{ 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } },
{ 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } } }
};
#undef A
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_INSN_##a)
#else
#define A(a) (1 << CGEN_INSN_a)
#endif
static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] =
{
{ 0, 0, 0, 0, {0, {0}} },
{
XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_POPGR, "popgr", "pop", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SWPN, "swpn", "swpn", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SWPB, "swpb", "swpb", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SWPW, "swpw", "swpw", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_NOTGR, "notgr", "not", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_REVGR, "revgr", "rev", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BCC, "bcc", "b", 16,
{ 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BGR, "bgr", "br", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BR, "br", "br", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_JMP, "jmp", "jmp", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_CALLGR, "callgr", "call", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_IRET, "iret", "iret", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_RET, "ret", "ret", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_MUL, "mul", "mul", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_DIV, "div", "div", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SDIV, "sdiv", "sdiv", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SDIVLH, "sdivlh", "sdivlh", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_DIVLH, "divlh", "divlh", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_RESET, "reset", "reset", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_NOP, "nop", "nop", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_HALT, "halt", "halt", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_HOLD, "hold", "hold", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_HOLDX, "holdx", "holdx", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_BRK, "brk", "brk", 16,
{ 0, { (1<<MACH_BASE) } }
},
{
XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16,
{ 0, { (1<<MACH_BASE) } }
},
};
#undef OP
#undef A
static void
init_tables (void)
{
}
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
static void build_hw_table (CGEN_CPU_TABLE *);
static void build_ifield_table (CGEN_CPU_TABLE *);
static void build_operand_table (CGEN_CPU_TABLE *);
static void build_insn_table (CGEN_CPU_TABLE *);
static void xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *);
static const CGEN_MACH *
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
{
while (table->name)
{
if (strcmp (name, table->bfd_name) == 0)
return table;
++table;
}
abort ();
}
static void
build_hw_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0];
const CGEN_HW_ENTRY **selected =
(const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
cd->hw_table.init_entries = init;
cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
for (i = 0; init[i].name != NULL; ++i)
if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
& machs)
selected[init[i].type] = &init[i];
cd->hw_table.entries = selected;
cd->hw_table.num_entries = MAX_HW;
}
static void
build_ifield_table (CGEN_CPU_TABLE *cd)
{
cd->ifld_table = & xstormy16_cgen_ifld_table[0];
}
static void
build_operand_table (CGEN_CPU_TABLE *cd)
{
int i;
int machs = cd->machs;
const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0];
const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
cd->operand_table.init_entries = init;
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
for (i = 0; init[i].name != NULL; ++i)
if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
& machs)
selected[init[i].type] = &init[i];
cd->operand_table.entries = selected;
cd->operand_table.num_entries = MAX_OPERANDS;
}
static void
build_insn_table (CGEN_CPU_TABLE *cd)
{
int i;
const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0];
CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
for (i = 0; i < MAX_INSNS; ++i)
insns[i].base = &ib[i];
cd->insn_table.init_entries = insns;
cd->insn_table.entry_size = sizeof (CGEN_IBASE);
cd->insn_table.num_init_entries = MAX_INSNS;
}
static void
xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
unsigned int isas = cd->isas;
unsigned int machs = cd->machs;
cd->int_insn_p = CGEN_INT_INSN_P;
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
cd->default_insn_bitsize = UNSET;
cd->base_insn_bitsize = UNSET;
cd->min_insn_bitsize = 65535;
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
if (((1 << i) & isas) != 0)
{
const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i];
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
;
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
;
else
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
if (isa->min_insn_bitsize < cd->min_insn_bitsize)
cd->min_insn_bitsize = isa->min_insn_bitsize;
if (isa->max_insn_bitsize > cd->max_insn_bitsize)
cd->max_insn_bitsize = isa->max_insn_bitsize;
}
for (i = 0; i < MAX_MACHS; ++i)
if (((1 << i) & machs) != 0)
{
const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i];
if (mach->insn_chunk_bitsize != 0)
{
if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
{
fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
abort ();
}
cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
}
}
build_hw_table (cd);
build_ifield_table (cd);
build_operand_table (cd);
build_insn_table (cd);
}
CGEN_CPU_DESC
xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
{
CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
static int init_p;
unsigned int isas = 0;
unsigned int machs = 0;
enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
va_list ap;
if (! init_p)
{
init_tables ();
init_p = 1;
}
memset (cd, 0, sizeof (*cd));
va_start (ap, arg_type);
while (arg_type != CGEN_CPU_OPEN_END)
{
switch (arg_type)
{
case CGEN_CPU_OPEN_ISAS :
isas = va_arg (ap, unsigned int);
break;
case CGEN_CPU_OPEN_MACHS :
machs = va_arg (ap, unsigned int);
break;
case CGEN_CPU_OPEN_BFDMACH :
{
const char *name = va_arg (ap, const char *);
const CGEN_MACH *mach =
lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name);
machs |= 1 << mach->num;
break;
}
case CGEN_CPU_OPEN_ENDIAN :
endian = va_arg (ap, enum cgen_endian);
break;
default :
fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n",
arg_type);
abort ();
}
arg_type = va_arg (ap, enum cgen_cpu_open_arg);
}
va_end (ap);
if (machs == 0)
machs = (1 << MAX_MACHS) - 1;
machs |= 1;
if (isas == 0)
isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
{
fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n");
abort ();
}
cd->isas = isas;
cd->machs = machs;
cd->endian = endian;
cd->insn_endian = endian;
cd->rebuild_tables = xstormy16_cgen_rebuild_tables;
xstormy16_cgen_rebuild_tables (cd);
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
CGEN_CPU_DESC
xstormy16_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
{
return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, endian,
CGEN_CPU_OPEN_END);
}
void
xstormy16_cgen_cpu_close (CGEN_CPU_DESC cd)
{
unsigned int i;
const CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
if (cd->insn_table.init_entries)
free ((CGEN_INSN *) cd->insn_table.init_entries);
if (cd->hw_table.entries)
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
if (cd->operand_table.entries)
free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
free (cd);
}