#include <stdio.h>
#include "ansidecl.h"
#include "opcode/s390.h"
const struct s390_operand s390_operands[] =
{
#define UNUSED 0
{ 0, 0, 0 },
#define R_8 1
{ 4, 8, S390_OPERAND_GPR },
#define R_12 2
{ 4, 12, S390_OPERAND_GPR },
#define R_16 3
{ 4, 16, S390_OPERAND_GPR },
#define R_20 4
{ 4, 20, S390_OPERAND_GPR },
#define R_24 5
{ 4, 24, S390_OPERAND_GPR },
#define R_28 6
{ 4, 28, S390_OPERAND_GPR },
#define R_32 7
{ 4, 32, S390_OPERAND_GPR },
#define F_8 8
{ 4, 8, S390_OPERAND_FPR },
#define F_12 9
{ 4, 12, S390_OPERAND_FPR },
#define F_16 10
{ 4, 16, S390_OPERAND_FPR },
#define F_20 11
{ 4, 16, S390_OPERAND_FPR },
#define F_24 12
{ 4, 24, S390_OPERAND_FPR },
#define F_28 13
{ 4, 28, S390_OPERAND_FPR },
#define F_32 14
{ 4, 32, S390_OPERAND_FPR },
#define A_8 15
{ 4, 8, S390_OPERAND_AR },
#define A_12 16
{ 4, 12, S390_OPERAND_AR },
#define A_24 17
{ 4, 24, S390_OPERAND_AR },
#define A_28 18
{ 4, 28, S390_OPERAND_AR },
#define C_8 19
{ 4, 8, S390_OPERAND_CR },
#define C_12 20
{ 4, 12, S390_OPERAND_CR },
#define B_16 21
{ 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
#define B_32 22
{ 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
#define X_12 23
{ 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
#define D_20 24
{ 12, 20, S390_OPERAND_DISP },
#define D_36 25
{ 12, 36, S390_OPERAND_DISP },
#define D20_20 26
{ 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
#define L4_8 27
{ 4, 8, S390_OPERAND_LENGTH },
#define L4_12 28
{ 4, 12, S390_OPERAND_LENGTH },
#define L8_8 29
{ 8, 8, S390_OPERAND_LENGTH },
#define U4_8 30
{ 4, 8, 0 },
#define U4_12 31
{ 4, 12, 0 },
#define U4_16 32
{ 4, 16, 0 },
#define U4_20 33
{ 4, 20, 0 },
#define U8_8 34
{ 8, 8, 0 },
#define U8_16 35
{ 8, 16, 0 },
#define I16_16 36
{ 16, 16, S390_OPERAND_SIGNED },
#define U16_16 37
{ 16, 16, 0 },
#define J16_16 38
{ 16, 16, S390_OPERAND_PCREL },
#define J32_16 39
{ 32, 16, S390_OPERAND_PCREL },
#define I32_16 40
{ 32, 16, S390_OPERAND_SIGNED },
#define U32_16 41
{ 32, 16, 0 },
#define M_16 42
{ 4, 16, S390_OPERAND_OPTIONAL }
};
#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }
#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
(x >> 16) & 255, (x >> 8) & 255, x & 255}
#define INSTR_E 2, { 0,0,0,0,0,0 }
#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 }
#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 }
#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 }
#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 }
#define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 }
#define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 }
#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 }
#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 }
#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 }
#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 }
#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 }
#define INSTR_RRE_00 4, { 0,0,0,0,0,0 }
#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 }
#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 }
#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 }
#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 }
#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 }
#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 }
#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 }
#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 }
#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 }
#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 }
#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 }
#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 }
#define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 }
#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 }
#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 }
#define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 }
#define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 }
#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 }
#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 }
#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 }
#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 }
#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 }
#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 }
#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 }
#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 }
#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 }
#define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 }
#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 }
#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 }
#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 }
#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 }
#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 }
#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 }
#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 }
#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 }
#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 }
#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 }
#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 }
#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 }
#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 }
#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 }
#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 }
#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 }
#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 }
#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 }
#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 }
#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 }
#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 }
#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 }
#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 }
#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 }
#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 }
#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 }
#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 }
#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 }
#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 }
#define INSTR_S_00 4, { 0,0,0,0,0,0 }
#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 }
#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 }
#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SSF_RRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
const struct s390_opcode s390_opformats[] =
{
{ "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 },
{ "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 },
{ "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 },
{ "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 },
{ "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 },
{ "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 },
{ "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 },
{ "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 },
{ "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 },
{ "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 },
{ "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 },
{ "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 },
{ "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 },
{ "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 },
{ "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 },
{ "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 },
{ "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 },
{ "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 },
{ "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 },
{ "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 },
{ "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 },
{ "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 },
};
const int s390_num_opformats =
sizeof (s390_opformats) / sizeof (s390_opformats[0]);
#include "s390-opc.tab"