:option:::insn-bit-size:8
:option:::insn-specifying-widths:true
:option:::hi-bit-nr:7
:model:::mn10300:mn10300:
:model:::am33:am33:
:internal::::illegal:
{
PC = cia;
program_interrupt(SD, CPU, cia, SIM_SIGILL);
}
4.0x8,2.DM1,2.DN0=DM1+8.IMM8:S0i:::mov
"mov"
*mn10300
*am33
{
signed32 immed = EXTEND8 (IMM8);
State.regs[REG_D0+DN0] = immed;
PC = cia;
}
4.0x8,2.DM1,2.DN0!DM1:S0:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0+DN0] = State.regs[REG_D0+DM1];
}
8.0xf1+1110,2.DM1,2.AN0:D0:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_D0 + DM1];
}
8.0xf1+1101,2.AM1,2.DN0:D0a:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] = State.regs[REG_A0 + AM1];
}
4.0x9,2.AM1,2.AN0=AM1+8.IMM8:S0ai:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0+AN0] = IMM8;
}
4.0x9,2.AM1,2.AN0!AM1:S0a:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0+AN0] = State.regs[REG_A0+AM1];
}
4.0x3,11,2.AN0:S0b:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN0] = State.regs[REG_SP];
}
8.0xf2+4.0xf,2.AM1,00:D0b:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_SP] = State.regs[REG_A0 + AM1];
}
8.0xf2+4.0xe,01,2.DN0:D0c:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] = PSW;
}
8.0xf2+4.0xf,2.DM1,11:D0d:::mov
"mov"
*mn10300
*am33
{
PC = cia;
PSW = State.regs[REG_D0 + DM1];
}
8.0xf2+4.0xe,00,2.DN0:D0e:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] = State.regs[REG_MDR];
}
8.0xf2+4.0xf,2.DM1,10:D0f:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_MDR] = State.regs[REG_D0 + DM1];
}
4.0x7,2.DN1,2.AM0:S0c:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1] = load_word (State.regs[REG_A0 + AM0]);
}
8.0xf8+4.0x0,2.DN1,2.AM0+8.D8:D1:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1]
= load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
}
8.0xfa+4.0x0,2.DN1,2.AM0+8.D16A+8.D16B:D2:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1]
= load_word ((State.regs[REG_A0 + AM0] + EXTEND16 (FETCH16(D16A, D16B))));
}
8.0xfc+4.0x0,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1]
= load_word ((State.regs[REG_A0 + AM0]
+ FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
}
4.0x5,10,2.DN0+8.D8:S1:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] = load_word (State.regs[REG_SP] + D8);
}
8.0xfa+4.0xb,01,2.DN0+8.IMM16A+8.IMM16B:D2a:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0]
= load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
}
8.0xfc+4.0xb,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0]
= load_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
}
8.0xf3+00,2.DN2,2.DI,2.AM0:D0g:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN2]
= load_word ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
}
4.0x3,00,2.DN0+8.IMM16A+8.IMM16B:S2:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] = load_word (FETCH16(IMM16A, IMM16B));
}
8.0xfc+4.0xa,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] = load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
}
8.0xf0+4.0x0,2.AN1,2.AM0:D0h:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN1] = load_word (State.regs[REG_A0 + AM0]);
}
8.0xf8+4.0x2,2.AN1,2.AM0+8.D8:D1a:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN1]
= load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
}
8.0xfa+4.0x2,2.AN1,2.AM0+8.D16A+8.D16B:D2b:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN1]
= load_word ((State.regs[REG_A0 + AM0]
+ EXTEND16 (FETCH16(D16A, D16B))));
}
8.0xfc+4.0x2,2.AN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN1]
= load_word ((State.regs[REG_A0 + AM0]
+ FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
}
4.0x5,11,2.AN0+8.D8:S1a:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN0]
= load_word (State.regs[REG_SP] + D8);
}
8.0xfa+4.0xb,00,2.AN0+8.IMM16A+8.IMM16B:D2c:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN0]
= load_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B));
}
8.0xfc+4.0xb,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN0]
= load_word (State.regs[REG_SP]
+ FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
}
8.0xf3+10,2.AN2,2.DI,2.AM0:D0i:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN2]
= load_word ((State.regs[REG_A0 + AM0]
+ State.regs[REG_D0 + DI]));
}
8.0xfa+4.0xa,00,2.AN0+8.IMM16A+8.IMM16B:D2d:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN0] = load_word (FETCH16(IMM16A, IMM16B));
}
8.0xfc+4.0xa,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN0]
= load_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
}
8.0xf8+4.0xf,00,2.AM0+8.D8:D1b:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_SP]
= load_word ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
}
4.0x6,2.DM1,2.AN0:S0d:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
}
8.0xf8+4.0x1,2.DM1,2.AN0+8.D8:D1c:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
State.regs[REG_D0 + DM1]);
}
8.0xfa+4.0x1,2.DM1,2.AN0+8.D16A+8.D16B:D2e:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
State.regs[REG_D0 + DM1]);
}
8.0xfc+4.0x1,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4f:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word ((State.regs[REG_A0 + AN0]
+ FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
State.regs[REG_D0 + DM1]);
}
4.0x4,2.DM1,10+8.D8:S1b:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (State.regs[REG_SP] + D8, State.regs[REG_D0 + DM1]);
}
8.0xfa+4.0x9,2.DM1,01+8.IMM16A+8.IMM16B:D2f:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
State.regs[REG_D0 + DM1]);
}
8.0xfc+4.0x9,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4g:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[REG_D0 + DM1]);
}
8.0xf3+01,2.DM2,2.DI,2.AN0:D0j:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
State.regs[REG_D0 + DM2]);
}
4.0x0,2.DM1,01+8.IMM16A+8.IMM16B:S2a:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
}
8.0xfc+4.0x8,2.DM1,01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4h:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[REG_D0 + DM1]);
}
8.0xf0+4.0x1,2.AM1,2.AN0:D0k:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (State.regs[REG_A0 + AN0], State.regs[REG_A0 + AM1]);
}
8.0xf8+4.0x3,2.AM1,2.AN0+8.D8:D1d:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
State.regs[REG_A0 + AM1]);
}
8.0xfa+4.0x3,2.AM1,2.AN0+8.D16A+8.D16B:D2g:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
State.regs[REG_A0 + AM1]);
}
8.0xfc+4.0x3,2.AM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4i:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word ((State.regs[REG_A0 + AN0]
+ FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
State.regs[REG_A0 + AM1]);
}
4.0x4,2.AM1,11+8.D8:S1c:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (State.regs[REG_SP] + (D8), State.regs[REG_A0 + (AM1)]);
}
8.0xfa+4.0x9,2.AM1,00+8.IMM16A+8.IMM16B:D2h:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
State.regs[REG_A0 + AM1]);
}
8.0xfc+4.0x9,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4j:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[REG_A0 + AM1]);
}
8.0xf3+11,2.AM2,2.DI,2.AN0:D0l:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
State.regs[REG_A0 + AM2]);
}
8.0xfa+4.0x8,2.AM1,00+8.IMM16A+8.IMM16B:D2i:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (FETCH16(IMM16A, IMM16B),
State.regs[REG_A0 + AM1]);
}
8.0xfc+4.0x8,2.AM1,00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4k:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[REG_A0 + AM1]);
}
8.0xf8+4.0xf,01,2.AN0+8.D8:D1e:::mov
"mov"
*mn10300
*am33
{
PC = cia;
store_word (State.regs[REG_A0 + AN0] + EXTEND8 (D8),
State.regs[REG_SP]);
}
4.0x2,11,2.DN0+8.IMM16A+8.IMM16B:S2b:::mov
"mov"
*mn10300
*am33
{
unsigned32 value;
PC = cia;
value = EXTEND16 (FETCH16(IMM16A, IMM16B));
State.regs[REG_D0 + DN0] = value;
}
8.0xfc+4.0xc,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4l:::mov
"mov"
*mn10300
*am33
{
unsigned32 value;
PC = cia;
value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
State.regs[REG_D0 + DN0] = value;
}
4.0x2,01,2.AN0+8.IMM16A+8.IMM16B:S2c:::mov
"mov"
*mn10300
*am33
{
unsigned32 value;
PC = cia;
value = FETCH16(IMM16A, IMM16B);
State.regs[REG_A0 + AN0] = value;
}
8.0xfc+4.0xd,11,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4m:::mov
"mov"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN0] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
}
8.0xf0+4.0x4,2.DN1,2.AM0:D0:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1]
= load_byte (State.regs[REG_A0 + AM0]);
}
8.0xf8+4.0x4,2.DN1,2.AM0+8.D8:D1f:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1]
= load_byte ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
}
8.0xfa+4.0x4,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1]
= load_byte ((State.regs[REG_A0 + AM0]
+ EXTEND16 (FETCH16(D16A, D16B))));
}
8.0xfc+4.0x4,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1]
= load_byte ((State.regs[REG_A0 + AM0]
+ FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
}
8.0xf8+4.0xb,10,2.DN0+8.D8:D1a:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0]
= load_byte ((State.regs[REG_SP] + (D8)));
}
8.0xfa+4.0xb,10,2.DN0+8.IMM16A+8.IMM16B:D2a:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0]
= load_byte ((State.regs[REG_SP]
+ FETCH16(IMM16A, IMM16B)));
}
8.0xfc+4.0xb,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0]
= load_byte (State.regs[REG_SP]
+ FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
}
8.0xf4+00,2.DN2,2.DI,2.AM0:D0a:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN2]
= load_byte ((State.regs[REG_A0 + AM0]
+ State.regs[REG_D0 + DI]));
}
4.0x3,01,2.DN0+8.IMM16A+8.IMM16B:S2:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] = load_byte (FETCH16(IMM16A, IMM16B));
}
8.0xfc+4.0xa,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0]
= load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
}
8.0xf0+4.0x5,2.DM1,2.AN0:D0b:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
store_byte (State.regs[REG_A0 + AN0], State.regs[REG_D0 + DM1]);
}
8.0xf8+4.0x5,2.DM1,2.AN0+8.D8:D1b:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
State.regs[REG_D0 + DM1]);
}
8.0xfa+4.0x5,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
store_byte ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
State.regs[REG_D0 + DM1]);
}
8.0xfc+4.0x5,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
store_byte ((State.regs[REG_A0 + AN0]
+ FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
State.regs[REG_D0 + DM1]);
}
8.0xf8+4.0x9,2.DM1,10+8.D8:D1c:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
store_byte (State.regs[REG_SP] + (D8), State.regs[REG_D0 + DM1]);
}
8.0xfa+4.0x9,2.DM1,10+8.IMM16A+8.IMM16B:D2c:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
store_byte (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
State.regs[REG_D0 + DM1]);
}
8.0xfc+4.0x9,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
store_byte (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[REG_D0 + DM1]);
}
8.0xf4+01,2.DM2,2.DI,2.AN0:D0c:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
store_byte ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
State.regs[REG_D0 + DM2]);
}
4.0x0,2.DM1,10+8.IMM16A+8.IMM16B:S2a:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
store_byte (FETCH16(IMM16A, IMM16B),
State.regs[REG_D0 + DM1]);
}
8.0xfc+4.0x8,2.DM1,10+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movbu
"movbu"
*mn10300
*am33
{
PC = cia;
store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[REG_D0 + DM1]);
}
8.0xf0+4.0x6,2.DN1,2.AM0:D0:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1]
= load_half (State.regs[REG_A0 + AM0]);
}
8.0xf8+4.0x6,2.DN1,2.AM0+8.D8:D1d:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1]
= load_half ((State.regs[REG_A0 + AM0] + EXTEND8 (D8)));
}
8.0xfa+4.0x6,2.DN1,2.AM0+8.D16A+8.D16B:D2:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1]
= load_half ((State.regs[REG_A0 + AM0]
+ EXTEND16 (FETCH16(D16A, D16B))));
}
8.0xfc+4.0x6,2.DN1,2.AM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1]
= load_half ((State.regs[REG_A0 + AM0]
+ FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
}
8.0xf8+4.0xb,11,2.DN0+8.D8:D1a:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0]
= load_half ((State.regs[REG_SP] + (D8)));
}
8.0xfa+4.0xb,11,2.DN0+8.IMM16A+8.IMM16B:D2a:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0]
= load_half ((State.regs[REG_SP] + FETCH16(IMM16A, IMM16B)));
}
8.0xfc+4.0xb,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0]
= load_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
}
8.0xf4+10,2.DN2,2.DI,2.AM0:D0a:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN2]
= load_half ((State.regs[REG_A0 + AM0] + State.regs[REG_D0 + DI]));
}
4.0x3,10,2.DN0+8.IMM16A+8.IMM16B:S2:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] = load_half (FETCH16(IMM16A, IMM16B));
}
8.0xfc+4.0xa,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0]
= load_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
}
8.0xf0+4.0x7,2.DM1,2.AN0:D0b:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
store_half (State.regs[REG_A0 + AN0],
State.regs[REG_D0 + DM1]);
}
8.0xf8+4.0x7,2.DM1,2.AN0+8.D8:D1b:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
store_half ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)),
State.regs[REG_D0 + DM1]);
}
8.0xfa+4.0x7,2.DM1,2.AN0+8.D16A+8.D16B:D2b:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
store_half ((State.regs[REG_A0 + AN0] + EXTEND16 (FETCH16(D16A, D16B))),
State.regs[REG_D0 + DM1]);
}
8.0xfc+4.0x7,2.DM1,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4c:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
store_half ((State.regs[REG_A0 + AN0]
+ FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)),
State.regs[REG_D0 + DM1]);
}
8.0xf8+4.0x9,2.DM1,11+8.D8:D1c:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
store_half (State.regs[REG_SP] + (D8),
State.regs[REG_D0 + DM1]);
}
8.0xfa+4.0x9,2.DM1,11+8.IMM16A+8.IMM16B:D2c:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
store_half (State.regs[REG_SP] + FETCH16(IMM16A, IMM16B),
State.regs[REG_D0 + DM1]);
}
8.0xfc+4.0x9,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4d:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
store_half (State.regs[REG_SP] + FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[REG_D0 + DM1]);
}
8.0xf4+11,2.DM2,2.DI,2.AN0:D0c:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
store_half ((State.regs[REG_A0 + AN0] + State.regs[REG_D0 + DI]),
State.regs[REG_D0 + DM2]);
}
4.0x0,2.DM1,11+8.IMM16A+8.IMM16B:S2a:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
store_half (FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DM1]);
}
8.0xfc+4.0x8,2.DM1,11+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4e:::movhu
"movhu"
*mn10300
*am33
{
PC = cia;
store_half (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[REG_D0 + DM1]);
}
8.0xf2+4.0xd,00,2.DN0:D0:::ext
"ext"
*mn10300
*am33
{
PC = cia;
if (State.regs[REG_D0 + DN0] & 0x80000000)
State.regs[REG_MDR] = -1;
else
State.regs[REG_MDR] = 0;
}
4.0x1,00,2.DN0:S0:::extb
"extb"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] = EXTEND8 (State.regs[REG_D0 + DN0]);
}
4.0x1,01,2.DN0:S0:::extbu
"extbu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] &= 0xff;
}
4.0x1,10,2.DN0:S0:::exth
"exth"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] = EXTEND16 (State.regs[REG_D0 + DN0]);
}
4.0x1,11,2.DN0:S0:::exthu
"exthu"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN0] &= 0xffff;
}
4.0x0,2.DN1,00:S0:::clr
"clr"
*mn10300
*am33
{
PC = cia;
State.regs[REG_D0 + DN1] = 0;
PSW |= PSW_Z;
PSW &= ~(PSW_V | PSW_C | PSW_N);
}
4.0xe,2.DM1,2.DN0:S0:::add
"add"
*mn10300
*am33
{
PC = cia;
genericAdd(State.regs[REG_D0 + DM1], REG_D0 + DN0);
}
8.0xf1+4.0x6,2.DM1,2.AN0:D0:::add
"add"
*mn10300
*am33
{
PC = cia;
genericAdd(State.regs[REG_D0 + DM1], REG_A0 + AN0);
}
8.0xf1+4.0x5,2.AM1,2.DN0:D0a:::add
"add"
*mn10300
*am33
{
PC = cia;
genericAdd(State.regs[REG_A0 + AM1], REG_D0 + DN0);
}
8.0xf1+4.0x7,2.AM1,2.AN0:D0b:::add
"add"
*mn10300
*am33
{
PC = cia;
genericAdd(State.regs[REG_A0 + AM1], REG_A0 + AN0);
}
4.0x2,10,2.DN0+8.IMM8:S1:::add
"add"
*mn10300
*am33
{
PC = cia;
genericAdd(EXTEND8(IMM8), REG_D0 + DN0);
}
8.0xfa+4.0xc,00,2.DN0+8.IMM16A+8.IMM16B:D2:::add
"add"
*mn10300
*am33
{
PC = cia;
genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_D0 + DN0);
}
8.0xfc+4.0xc,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::add
"add"
*mn10300
*am33
{
PC = cia;
genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
}
4.0x2,00,2.AN0+8.IMM8:S1a:::add
"add"
*mn10300
*am33
{
PC = cia;
genericAdd(EXTEND8(IMM8), REG_A0 + AN0);
}
8.0xfa+4.0xd,00,2.AN0+8.IMM16A+8.IMM16B:D2a:::add
"add"
*mn10300
*am33
{
PC = cia;
genericAdd(EXTEND16(FETCH16(IMM16A, IMM16B)), REG_A0 + AN0);
}
8.0xfc+4.0xd,00,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::add
"add"
*mn10300
*am33
{
PC = cia;
genericAdd(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
}
8.0xf8+8.0xfe+8.IMM8:D1:::add
"add"
*mn10300
*am33
{
unsigned32 imm;
PC = cia;
imm = EXTEND8 (IMM8);
State.regs[REG_SP] += imm;
}
8.0xfa+8.0xfe+8.IMM16A+8.IMM16B:D2b:::add
"add"
*mn10300
*am33
{
unsigned32 imm;
PC = cia;
imm = EXTEND16 (FETCH16(IMM16A, IMM16B));
State.regs[REG_SP] += imm;
}
8.0xfc+8.0xfe+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4b:::add
"add"
*mn10300
*am33
{
unsigned32 imm;
PC = cia;
imm = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
State.regs[REG_SP] += imm;
}
8.0xf1+4.0x4,2.DM1,2.DN0:D0:::addc
"addc"
*mn10300
*am33
{
int z, c, n, v;
unsigned32 reg1, reg2, sum;
PC = cia;
reg1 = State.regs[REG_D0 + DM1];
reg2 = State.regs[REG_D0 + DN0];
sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
State.regs[REG_D0 + DN0] = sum;
z = ((PSW & PSW_Z) != 0) && (sum == 0);
n = (sum & 0x80000000);
c = (sum < reg1) || (sum < reg2);
v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
&& (reg2 & 0x80000000) != (sum & 0x80000000));
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
}
8.0xf1+4.0x0,2.DM1,2.DN0:D0:::sub
"sub"
*mn10300
*am33
{
PC = cia;
genericSub(State.regs[REG_D0 + DM1], REG_D0 + DN0);
}
8.0xf1+4.0x2,2.DM1,2.AN0:D0a:::sub
"sub"
*mn10300
*am33
{
PC = cia;
genericSub(State.regs[REG_D0 + DM1], REG_A0 + AN0);
}
8.0xf1+4.0x1,2.AM1,2.DN0:D0b:::sub
"sub"
*mn10300
*am33
{
PC = cia;
genericSub(State.regs[REG_A0 + AM1], REG_D0 + DN0);
}
8.0xf1+4.0x3,2.AM1,2.AN0:D0c:::sub
"sub"
*mn10300
*am33
{
PC = cia;
genericSub(State.regs[REG_A0 + AM1], REG_A0 + AN0);
}
8.0xfc+4.0xc,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::sub
"sub"
*mn10300
*am33
{
PC = cia;
genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
}
8.0xfc+4.0xd,01,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::sub
"sub"
*mn10300
*am33
{
PC = cia;
genericSub(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_A0 + AN0);
}
8.0xf1+4.0x8,2.DM1,2.DN0:D0:::subc
"subc"
*mn10300
*am33
{
int z, c, n, v;
unsigned32 reg1, reg2, difference;
PC = cia;
reg1 = State.regs[REG_D0 + DM1];
reg2 = State.regs[REG_D0 + DN0];
difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
State.regs[REG_D0 + DN0] = difference;
z = ((PSW & PSW_Z) != 0) && (difference == 0);
n = (difference & 0x80000000);
c = (reg1 > reg2);
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
&& (reg2 & 0x80000000) != (difference & 0x80000000));
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
}
8.0xf2+4.0x4,2.DM1,2.DN0:D0:::mul
"mul"
*mn10300
*am33
{
unsigned64 temp;
int n, z;
PC = cia;
temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
* (signed64)(signed32)State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xf2+4.0x5,2.DM1,2.DN0:D0:::mulu
"mulu"
*mn10300
*am33
{
unsigned64 temp;
int n, z;
PC = cia;
temp = ((unsigned64)State.regs[REG_D0 + DN0]
* (unsigned64)State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xf2+4.0x6,2.DM1,2.DN0:D0:::div
"div"
*mn10300
*am33
{
signed64 temp;
signed32 denom;
int n, z, v;
PC = cia;
denom = (signed32)State.regs[REG_D0 + DM1];
temp = State.regs[REG_MDR];
temp <<= 32;
temp |= State.regs[REG_D0 + DN0];
if ( !(v = (0 == denom)) )
{
State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
temp /= (signed32)State.regs[REG_D0 + DM1];
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
}
else
{
State.regs[REG_MDR] = temp;
State.regs[REG_D0 + DN0] = 0xff;
}
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
}
8.0xf2+4.0x7,2.DM1,2.DN0:D0:::divu
"divu"
*mn10300
*am33
{
unsigned64 temp;
unsigned32 denom;
int n, z, v;
PC = cia;
denom = (unsigned32)State.regs[REG_D0 + DM1];
temp = State.regs[REG_MDR];
temp <<= 32;
temp |= State.regs[REG_D0 + DN0];
if ( !(v = (0 == denom)) )
{
State.regs[REG_MDR] = temp % State.regs[REG_D0 + DM1];
temp /= State.regs[REG_D0 + DM1];
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
}
else
{
State.regs[REG_MDR] = temp;
State.regs[REG_D0 + DN0] = 0xff;
}
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (v ? PSW_V : 0));
}
4.0x4,2.DN1,00:S0:::inc
"inc"
*mn10300
*am33
{
unsigned32 imm;
PC = cia;
imm = 1;
genericAdd(imm, REG_D0 + DN1);
}
4.0x4,2.AN1,01:S0a:::inc
"inc"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN1] += 1;
}
4.0x5,00,2.AN0:S0:::inc4
"inc4"
*mn10300
*am33
{
PC = cia;
State.regs[REG_A0 + AN0] += 4;
}
4.0xa,2.DM1,2.DN0=DM1+IMM8:S0i:::cmp
"cmp"
*mn10300
*am33
{
PC = cia;
genericCmp(EXTEND8 (IMM8), State.regs[REG_D0 + DN0]);
}
4.0xa,2.DM1,2.DN0!DM1:S0:::cmp
"cmp"
*mn10300
*am33
{
PC = cia;
genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_D0 + DN0]);
}
8.0xf1+4.0xa,2.DM1,2.AN0:D0:::cmp
"cmp"
*mn10300
*am33
{
PC = cia;
genericCmp(State.regs[REG_D0 + DM1], State.regs[REG_A0 + AN0]);
}
8.0xf1+4.0x9,2.AM1,2.DN0:D0a:::cmp
"cmp"
*mn10300
*am33
{
PC = cia;
genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_D0 + DN0]);
}
4.0xb,2.AM1,2.AN0=AM1+IMM8:S0ai:::cmp
"cmp"
*mn10300
*am33
{
PC = cia;
genericCmp(IMM8,
State.regs[REG_A0 + AN0]);
}
4.0xb,2.AM1,2.AN0!AM1:S0a:::cmp
"cmp"
*mn10300
*am33
{
PC = cia;
genericCmp(State.regs[REG_A0 + AM1], State.regs[REG_A0 + AN0]);
}
8.0xfa+4.0xc,10,2.DN0+8.IMM16A+8.IMM16B:D2:::cmp
"cmp"
*mn10300
*am33
{
PC = cia;
genericCmp(EXTEND16(FETCH16(IMM16A, IMM16B)),
State.regs[REG_D0 + DN0]);
}
8.0xfc+4.0xc,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::cmp
"cmp"
*mn10300
*am33
{
PC = cia;
genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[REG_D0 + DN0]);
}
8.0xfa+4.0xd,10,2.AN0+8.IMM16A+8.IMM16B:D2a:::cmp
"cmp"
*mn10300
*am33
{
PC = cia;
genericCmp(FETCH16(IMM16A, IMM16B),
State.regs[REG_A0 + AN0]);
}
8.0xfc+4.0xd,10,2.AN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::cmp
"cmp"
*mn10300
*am33
{
PC = cia;
genericCmp(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[REG_A0 + AN0]);
}
8.0xf2+4.0x0,2.DM1,2.DN0:D0:::and
"and"
*mn10300
*am33
{
int n, z;
PC = cia;
State.regs[REG_D0 + DN0] &= State.regs[REG_D0 + DM1];
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xf8+4.0xe,00,2.DN0+8.IMM8:D1:::and
"and"
*mn10300
*am33
{
int n, z;
PC = cia;
State.regs[REG_D0 + DN0] &= IMM8;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xfa+4.0xe,00,2.DN0+8.IMM16A+8.IMM16B:D2:::and
"and"
*mn10300
*am33
{
int n, z;
PC = cia;
State.regs[REG_D0 + DN0] &= FETCH16(IMM16A, IMM16B);
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xfc+4.0xe,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::and
"and"
*mn10300
*am33
{
int n, z;
PC = cia;
State.regs[REG_D0 + DN0]
&= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xfa+8.0xfc+8.IMM16A+8.IMM16B:D2a:::and
"and"
*mn10300
*am33
{
PC = cia;
PSW &= FETCH16(IMM16A, IMM16B);
}
8.0xf2+4.0x1,2.DM1,2.DN0:D0:::or
"or"
*mn10300
*am33
{
PC = cia;
genericOr(State.regs[REG_D0 + DM1], REG_D0 + DN0);
}
8.0xf8+4.0xe,01,2.DN0+8.IMM8:D1:::or
"or"
*mn10300
*am33
{
PC = cia;
genericOr(IMM8, REG_D0 + DN0);
}
8.0xfa+4.0xe,01,2.DN0+8.IMM16A+8.IMM16B:D2:::or
"or"
*mn10300
*am33
{
PC = cia;
genericOr(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
}
8.0xfc+4.0xe,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::or
"or"
*mn10300
*am33
{
PC = cia;
genericOr(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
}
8.0xfa+8.0xfd+8.IMM16A+8.IMM16B:D2a:::or
"or"
*mn10300
*am33
{
PC = cia;
PSW |= FETCH16(IMM16A, IMM16B);
}
8.0xf2+4.0x2,2.DM1,2.DN0:D0:::xor
"xor"
*mn10300
*am33
{
PC = cia;
genericXor(State.regs[REG_D0 + DM1], REG_D0 + DN0);
}
8.0xfa+4.0xe,10,2.DN0+8.IMM16A+8.IMM16B:D2:::xor
"xor"
*mn10300
*am33
{
PC = cia;
genericXor(FETCH16(IMM16A, IMM16B), REG_D0 + DN0);
}
8.0xfc+4.0xe,10,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::xor
"xor"
*mn10300
*am33
{
PC = cia;
genericXor(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), REG_D0 + DN0);
}
8.0xf2+4.0x3,00,2.DN0:D0:::not
"not"
*mn10300
*am33
{
int n, z;
PC = cia;
State.regs[REG_D0 + DN0] = ~State.regs[REG_D0 + DN0];
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xf8+4.0xe,11,2.DN0+8.IMM8:D1:::btst
"btst"
*mn10300
*am33
{
PC = cia;
genericBtst(IMM8, State.regs[REG_D0 + DN0]);
}
8.0xfa+4.0xe,11,2.DN0+8.IMM16A+8.IMM16B:D2:::btst
"btst"
*mn10300
*am33
{
PC = cia;
genericBtst(FETCH16(IMM16A, IMM16B), State.regs[REG_D0 + DN0]);
}
8.0xfc+4.0xe,11,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::btst
"btst"
*mn10300
*am33
{
PC = cia;
genericBtst(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[REG_D0 + DN0]);
}
8.0xfe+8.0x02+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::btst
"btst"
*mn10300
*am33
{
PC = cia;
genericBtst(IMM8,
load_byte(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
}
8.0xfa+4.0xf,10,2.AN0+8.D8+8.IMM8:D2a:::btst
"btst"
*mn10300
*am33
{
PC = cia;
genericBtst(IMM8,
load_byte(State.regs[REG_A0 + AN0] + EXTEND8(D8)));
}
8.0xf0+4.8,2.DM1,2.AN0:D0:::bset
"bset"
*mn10300
*am33
{
unsigned32 temp;
int z;
PC = cia;
temp = load_byte (State.regs[REG_A0 + AN0]);
z = (temp & State.regs[REG_D0 + DM1]) == 0;
temp |= State.regs[REG_D0 + DM1];
store_byte (State.regs[REG_A0 + AN0], temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
8.0xfe+8.0x00+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bset
"bset"
*mn10300
*am33
{
unsigned32 temp;
int z;
PC = cia;
temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
z = (temp & IMM8) == 0;
temp |= IMM8;
store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
8.0xfa+4.0xf,00,2.AN0+8.D8+8.IMM8:D2:::bset
"bset"
*mn10300
*am33
{
unsigned32 temp;
int z;
PC = cia;
temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
z = (temp & (IMM8)) == 0;
temp |= (IMM8);
store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
8.0xf0+4.0x9,2.DM1,2.AN0:D0:::bclr
"bclr"
*mn10300
*am33
{
unsigned32 temp;
int z;
PC = cia;
temp = load_byte (State.regs[REG_A0 + AN0]);
z = (temp & State.regs[REG_D0 + DM1]) == 0;
temp = temp & ~State.regs[REG_D0 + DM1];
store_byte (State.regs[REG_A0 + AN0], temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
8.0xfe+8.0x01+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D+8.IMM8:D5:::bclr
"bclr"
*mn10300
*am33
{
unsigned32 temp;
int z;
PC = cia;
temp = load_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D));
z = (temp & IMM8) == 0;
temp = temp & ~(IMM8);
store_byte (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
8.0xfa+4.0xf,01,2.AN0+8.D8+8.IMM8:D2:::bclr
"bclr"
*mn10300
*am33
{
unsigned32 temp;
int z;
PC = cia;
temp = load_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)));
z = (temp & (IMM8)) == 0;
temp = temp & ~(IMM8);
store_byte ((State.regs[REG_A0 + AN0] + EXTEND8 (D8)), temp);
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0);
}
8.0xf2+4.0xb,2.DM1,2.DN0:D0:::asr
"asr"
*mn10300
*am33
{
signed32 temp;
int z, n, c;
PC = cia;
temp = State.regs[REG_D0 + DN0];
c = temp & 1;
temp >>= State.regs[REG_D0 + DM1];
State.regs[REG_D0 + DN0] = temp;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}
8.0xf8+4.0xc,10,2.DN0+8.IMM8:D1:::asr
"asr"
*mn10300
*am33
{
signed32 temp;
int z, n, c;
PC = cia;
temp = State.regs[REG_D0 + DN0];
c = temp & 1;
temp >>= IMM8;
State.regs[REG_D0 + DN0] = temp;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}
8.0xf2+4.0xa,2.DM1,2.DN0:D0:::lsr
"lsr"
*mn10300
*am33
{
int z, n, c;
PC = cia;
c = State.regs[REG_D0 + DN0] & 1;
State.regs[REG_D0 + DN0]
>>= State.regs[REG_D0 + DM1];
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}
8.0xf8+4.0xc,01,2.DN0+8.IMM8:D1:::lsr
"lsr"
*mn10300
*am33
{
int z, n, c;
PC = cia;
c = State.regs[REG_D0 + DN0] & 1;
State.regs[REG_D0 + DN0] >>= IMM8;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}
8.0xf2+4.0x9,2.DM1,2.DN0:D0:::asl
"asl"
*mn10300
*am33
{
int n, z;
PC = cia;
State.regs[REG_D0 + DN0]
<<= State.regs[REG_D0 + DM1];
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xf8+4.0xc,00,2.DN0+8.IMM8:D1:::asl
"asl"
*mn10300
*am33
{
int n, z;
PC = cia;
State.regs[REG_D0 + DN0] <<= IMM8;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
4.0x5,01,2.DN0:S0:::asl2
"asl2"
*mn10300
*am33
{
int n, z;
PC = cia;
State.regs[REG_D0 + DN0] <<= 2;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xf2+4.0x8,01,2.DN0:D0:::ror
"ror"
*mn10300
*am33
{
unsigned32 value;
int c,n,z;
PC = cia;
value = State.regs[REG_D0 + DN0];
c = (value & 0x1);
value >>= 1;
value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
State.regs[REG_D0 + DN0] = value;
z = (value == 0);
n = (value & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}
8.0xf2+4.0x8,00,2.DN0:D0:::rol
"rol"
*mn10300
*am33
{
unsigned32 value;
int c,n,z;
PC = cia;
value = State.regs[REG_D0 + DN0];
c = (value & 0x80000000) ? 1 : 0;
value <<= 1;
value |= ((PSW & PSW_C) != 0);
State.regs[REG_D0 + DN0] = value;
z = (value == 0);
n = (value & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
}
8.0xc8+8.D8:S1:::beq
"beq"
*mn10300
*am33
{
PC = cia;
if ((PSW & PSW_Z))
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xc9+8.D8:S1:::bne
"bne"
*mn10300
*am33
{
PC = cia;
if (!(PSW & PSW_Z))
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xc1+8.D8:S1:::bgt
"bgt"
*mn10300
*am33
{
PC = cia;
if (!((PSW & PSW_Z)
|| (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xc2+8.D8:S1:::bge
"bge"
*mn10300
*am33
{
PC = cia;
if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xc3+8.D8:S1:::ble
"ble"
*mn10300
*am33
{
PC = cia;
if ((PSW & PSW_Z)
|| (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xc0+8.D8:S1:::blt
"blt"
*mn10300
*am33
{
PC = cia;
if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xc5+8.D8:S1:::bhi
"bhi"
*mn10300
*am33
{
PC = cia;
if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xc6+8.D8:S1:::bcc
"bcc"
*mn10300
*am33
{
PC = cia;
if (!(PSW & PSW_C))
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xc7+8.D8:S1:::bls
"bls"
*mn10300
*am33
{
PC = cia;
if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xc4+8.D8:S1:::bcs
"bcs"
*mn10300
*am33
{
PC = cia;
if (PSW & PSW_C)
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xf8+8.0xe8+8.D8:D1:::bvc
"bvc"
*mn10300
*am33
{
PC = cia;
if (!(PSW & PSW_V))
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xf8+8.0xe9+8.D8:D1:::bvs
"bvs"
*mn10300
*am33
{
PC = cia;
if (PSW & PSW_V)
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xf8+8.0xea+8.D8:D1:::bnc
"bnc"
*mn10300
*am33
{
PC = cia;
if (!(PSW & PSW_N))
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xf8+8.0xeb+8.D8:D1:::bns
"bns"
*mn10300
*am33
{
PC = cia;
if (PSW & PSW_N)
{
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
}
8.0xca+8.D8:S1:::bra
"bra"
*mn10300
*am33
{
PC = cia;
State.regs[REG_PC] += EXTEND8 (D8);
nia = PC;
}
8.0xd8:S0:::leq
"leq"
*mn10300
*am33
{
PC = cia;
if (PSW & PSW_Z)
{
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
}
8.0xd9:S0:::lne
"lne"
*mn10300
*am33
{
PC = cia;
if (!(PSW & PSW_Z))
{
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
}
8.0xd1:S0:::lgt
"lgt"
*mn10300
*am33
{
PC = cia;
if (!((PSW & PSW_Z)
|| (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
{
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
}
8.0xd2:S0:::lge
"lge"
*mn10300
*am33
{
PC = cia;
if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
{
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
}
8.0xd3:S0:::lle
"lle"
*mn10300
*am33
{
PC = cia;
if ((PSW & PSW_Z)
|| (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
{
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
}
8.0xd0:S0:::llt
"llt"
*mn10300
*am33
{
PC = cia;
if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
{
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
}
8.0xd5:S0:::lhi
"lhi"
*mn10300
*am33
{
PC = cia;
if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
{
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
}
8.0xd6:S0:::lcc
"lcc"
*mn10300
*am33
{
PC = cia;
if (!(PSW & PSW_C))
{
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
}
8.0xd7:S0:::lls
"lls"
*mn10300
*am33
{
PC = cia;
if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
{
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
}
8.0xd4:S0:::lcs
"lcs"
*mn10300
*am33
{
PC = cia;
if (PSW & PSW_C)
{
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
}
8.0xda:S0:::lra
"lra"
*mn10300
*am33
{
PC = cia;
State.regs[REG_PC] = State.regs[REG_LAR] - 4;
nia = PC;
}
8.0xdb:S0:::setlb
"setlb"
*mn10300
*am33
{
PC = cia;
State.regs[REG_LIR] = load_word (State.regs[REG_PC] + 1);
State.regs[REG_LAR] = State.regs[REG_PC] + 5;
}
8.0xf0+4.0xf,01,2.AN0:D0:::jmp
"jmp"
*mn10300
*am33
{
PC = State.regs[REG_A0 + AN0];
nia = PC;
}
8.0xcc+8.D16A+8.D16B:S2:::jmp
"jmp"
*mn10300
*am33
{
PC = cia + EXTEND16(FETCH16(D16A, D16B));
nia = PC;
}
8.0xdc+8.D32A+8.D32B+8.D32C+8.D32D:S4:::jmp
"jmp"
*mn10300
*am33
{
PC = cia + FETCH32(D32A, D32B, D32C, D32D);
nia = PC;
}
8.0xf0+4.0xf,00,2.AN0:D0:::calls
"calls"
*mn10300
*am33
{
unsigned32 next_pc, sp;
PC = cia;
sp = State.regs[REG_SP];
next_pc = State.regs[REG_PC] + 2;
store_word(sp, next_pc);
State.regs[REG_MDR] = next_pc;
State.regs[REG_PC] = State.regs[REG_A0 + AN0];
nia = PC;
}
8.0xfa+8.0xff+8.D16A+8.D16B:D2:::calls
"calls"
*mn10300
*am33
{
unsigned32 next_pc, sp;
PC = cia;
sp = State.regs[REG_SP];
next_pc = State.regs[REG_PC] + 4;
store_word(sp, next_pc);
State.regs[REG_MDR] = next_pc;
State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
nia = PC;
}
8.0xfc+8.0xff+8.D32A+8.D32B+8.D32C+8.D32D:D4:::calls
"calls"
*mn10300
*am33
{
unsigned32 next_pc, sp;
PC = cia;
sp = State.regs[REG_SP];
next_pc = State.regs[REG_PC] + 6;
store_word(sp, next_pc);
State.regs[REG_MDR] = next_pc;
State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
nia = PC;
}
8.0xf0+8.0xfc:D0:::rets
"rets"
*mn10300
*am33
{
unsigned32 sp;
sp = State.regs[REG_SP];
State.regs[REG_PC] = load_word(sp);
nia = PC;
}
8.0xf0+8.0xfd:D0:::rti
"rti"
*mn10300
*am33
{
unsigned32 sp;
sp = State.regs[REG_SP];
PSW = load_half(sp);
State.regs[REG_PC] = load_word(sp+4);
State.regs[REG_SP] +=8;
nia = PC;
}
8.0xf0+8.0xfe:D0:::trap
"trap"
*mn10300
*am33
{
unsigned32 sp, next_pc;
PC = cia;
sp = State.regs[REG_SP];
next_pc = State.regs[REG_PC] + 2;
store_word(sp, next_pc);
nia = PC;
}
8.0xf0+8.0xff:D0:::rtm
"rtm"
*mn10300
*am33
{
PC = cia;
abort ();
}
8.0xcb:S0:::nop
"nop"
*mn10300
*am33
{
PC = cia;
}
8.0xf5+4.0x0,2.DM1,2.DN0:D0:::putx
"putx"
*mn10300
{
PC = cia;
State.regs[REG_MDRQ] = State.regs[REG_D0 + DN0];
}
8.0xf6+4.0xf,2.DM1,2.DN0:D0:::getx
"getx"
*mn10300
*am33
{
int z, n;
PC = cia;
z = (State.regs[REG_MDRQ] == 0);
n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
State.regs[REG_D0 + DN0] = State.regs[REG_MDRQ];
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
}
8.0xf6+4.0x0,2.DM1,2.DN0:D0:::mulq
"mulq"
*mn10300
*am33
{
unsigned64 temp;
int n, z;
PC = cia;
temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
* (signed64)(signed32)State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xf9+4.0x,00,2.DN0+8.IMM8:D1:::mulq
"mulq"
*mn10300
*am33
{
unsigned64 temp;
int n, z;
PC = cia;
temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
* (signed64)(signed32)EXTEND8 (IMM8));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xfb+4.0x0,00,2.DN0+8.IMM16A+8.IMM16B:D2:::mulq
"mulq"
*mn10300
*am33
{
unsigned64 temp;
int n, z;
PC = cia;
temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
* (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xfd+4.0x0,00,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulq
"mulq"
*mn10300
*am33
{
unsigned64 temp;
int n, z;
PC = cia;
temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
* (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xf6+4.0x1,2.DM1,2.DN0:D0:::mulqu
"mulqu"
*mn10300
*am33
{
unsigned64 temp;
int n, z;
PC = cia;
temp = ((unsigned64) State.regs[REG_D0 + DN0]
* (unsigned64) State.regs[REG_D0 + DM1]);
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xf9+4.0x1,01,2.DN0+8.IMM8:D1:::mulqu
"mulqu"
*mn10300
*am33
{
unsigned64 temp;
int n, z;
PC = cia;
temp = ((unsigned64)State.regs[REG_D0 + DN0]
* (unsigned64)EXTEND8 (IMM8));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xfb+4.0x1,01,2.DN0+8.IMM16A+8.IMM16B:D2:::mulqu
"mulqu"
*mn10300
*am33
{
unsigned64 temp;
int n, z;
PC = cia;
temp = ((unsigned64)State.regs[REG_D0 + DN0]
* (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xfd+4.0x1,01,2.DN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4:::mulqu
"mulqu"
*mn10300
*am33
{
unsigned64 temp;
int n, z;
PC = cia;
temp = ((unsigned64)State.regs[REG_D0 + DN0]
* (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
State.regs[REG_D0 + DN0] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + DN0] == 0);
n = (State.regs[REG_D0 + DN0] & 0x80000000) != 0;
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
}
8.0xf6+4.0x4,2.DM1,2.DN0:D0:::sat16
"sat16"
*mn10300
*am33
{
int temp;
PC = cia;
temp = State.regs[REG_D0 + DM1];
temp = (temp > 0x7fff ? 0x7fff : temp);
temp = (temp < -0x8000 ? -0x8000 : temp);
State.regs[REG_D0 + DN0] = temp;
}
8.0xf6+4.0x5,2.DM1,2.DN0:D0:::sat24
"sat24"
*mn10300
*am33
{
int temp;
PC = cia;
temp = State.regs[REG_D0 + DM1];
temp = (temp > 0x7fffff ? 0x7fffff : temp);
temp = (temp < -0x800000 ? -0x800000 : temp);
State.regs[REG_D0 + DN0] = temp;
}
8.0xf6+4.0x7,2.DM1,2.DN0:D0:::bsch
"bsch"
*mn10300
*am33
{
int temp, c;
PC = cia;
temp = State.regs[REG_D0 + DM1];
temp <<= (State.regs[REG_D0 + DN0] & 0x1f);
c = (temp != 0 ? 1 : 0);
PSW &= ~(PSW_C);
PSW |= (c ? PSW_C : 0);
}
8.0xf0+8.0xc0:D0:::syscall
"syscall"
*mn10300
*am33
{
PC = cia;
do_syscall ();
}
8.0xff:S0:::break
"break"
*mn10300
*am33
{
PC = cia;
program_interrupt(SD, CPU, cia, SIM_SIGTRAP);
}
8.0xce+8.REGS:S1:::movm
"movm"
*mn10300
*am33
{
unsigned32 sp = State.regs[REG_SP];
unsigned32 mask;
PC = cia;
mask = REGS;
if (mask & 0x8)
{
sp += 4;
State.regs[REG_LAR] = load_word (sp);
sp += 4;
State.regs[REG_LIR] = load_word (sp);
sp += 4;
State.regs[REG_MDR] = load_word (sp);
sp += 4;
State.regs[REG_A0 + 1] = load_word (sp);
sp += 4;
State.regs[REG_A0] = load_word (sp);
sp += 4;
State.regs[REG_D0 + 1] = load_word (sp);
sp += 4;
State.regs[REG_D0] = load_word (sp);
sp += 4;
}
if (mask & 0x10)
{
State.regs[REG_A0 + 3] = load_word (sp);
sp += 4;
}
if (mask & 0x20)
{
State.regs[REG_A0 + 2] = load_word (sp);
sp += 4;
}
if (mask & 0x40)
{
State.regs[REG_D0 + 3] = load_word (sp);
sp += 4;
}
if (mask & 0x80)
{
State.regs[REG_D0 + 2] = load_word (sp);
sp += 4;
}
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
)
{
if (mask & 0x1)
{
sp += 16;
State.regs[REG_E0 + 1] = load_word (sp);
sp += 4;
State.regs[REG_E0 + 0] = load_word (sp);
sp += 4;
}
if (mask & 0x2)
{
State.regs[REG_E0 + 7] = load_word (sp);
sp += 4;
State.regs[REG_E0 + 6] = load_word (sp);
sp += 4;
State.regs[REG_E0 + 5] = load_word (sp);
sp += 4;
State.regs[REG_E0 + 4] = load_word (sp);
sp += 4;
}
if (mask & 0x4)
{
State.regs[REG_E0 + 3] = load_word (sp);
sp += 4;
State.regs[REG_E0 + 2] = load_word (sp);
sp += 4;
}
}
State.regs[REG_SP] = sp;
}
8.0xcf+8.REGS:S1a:::movm
"movm"
*mn10300
*am33
{
unsigned32 sp = State.regs[REG_SP];
unsigned32 mask;
PC = cia;
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
)
{
if (mask & 0x4)
{
sp -= 4;
store_word (sp, State.regs[REG_E0 + 2]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 3]);
}
if (mask & 0x2)
{
sp -= 4;
store_word (sp, State.regs[REG_E0 + 4]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 5]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 6]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 7]);
}
if (mask & 0x1)
{
sp -= 4;
store_word (sp, State.regs[REG_E0 + 0]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 1]);
sp -= 16;
}
}
if (mask & 0x80)
{
sp -= 4;
store_word (sp, State.regs[REG_D0 + 2]);
}
if (mask & 0x40)
{
sp -= 4;
store_word (sp, State.regs[REG_D0 + 3]);
}
if (mask & 0x20)
{
sp -= 4;
store_word (sp, State.regs[REG_A0 + 2]);
}
if (mask & 0x10)
{
sp -= 4;
store_word (sp, State.regs[REG_A0 + 3]);
}
if (mask & 0x8)
{
sp -= 4;
store_word (sp, State.regs[REG_D0]);
sp -= 4;
store_word (sp, State.regs[REG_D0 + 1]);
sp -= 4;
store_word (sp, State.regs[REG_A0]);
sp -= 4;
store_word (sp, State.regs[REG_A0 + 1]);
sp -= 4;
store_word (sp, State.regs[REG_MDR]);
sp -= 4;
store_word (sp, State.regs[REG_LIR]);
sp -= 4;
store_word (sp, State.regs[REG_LAR]);
sp -= 4;
}
State.regs[REG_SP] = sp;
}
8.0xcd+8.D16A+8.D16B+8.REGS+8.IMM8:S4:::call
"call"
*mn10300
*am33
{
unsigned32 next_pc, sp;
unsigned32 mask;
PC = cia;
sp = State.regs[REG_SP];
next_pc = PC + 5;
store_word(sp, next_pc);
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
)
{
if (mask & 0x4)
{
sp -= 4;
store_word (sp, State.regs[REG_E0 + 2]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 3]);
}
if (mask & 0x2)
{
sp -= 4;
store_word (sp, State.regs[REG_E0 + 4]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 5]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 6]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 7]);
}
if (mask & 0x1)
{
sp -= 4;
store_word (sp, State.regs[REG_E0 + 0]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 1]);
sp -= 16;
}
}
if (mask & 0x80)
{
sp -= 4;
store_word (sp, State.regs[REG_D0 + 2]);
}
if (mask & 0x40)
{
sp -= 4;
store_word (sp, State.regs[REG_D0 + 3]);
}
if (mask & 0x20)
{
sp -= 4;
store_word (sp, State.regs[REG_A0 + 2]);
}
if (mask & 0x10)
{
sp -= 4;
store_word (sp, State.regs[REG_A0 + 3]);
}
if (mask & 0x8)
{
sp -= 4;
store_word (sp, State.regs[REG_D0]);
sp -= 4;
store_word (sp, State.regs[REG_D0 + 1]);
sp -= 4;
store_word (sp, State.regs[REG_A0]);
sp -= 4;
store_word (sp, State.regs[REG_A0 + 1]);
sp -= 4;
store_word (sp, State.regs[REG_MDR]);
sp -= 4;
store_word (sp, State.regs[REG_LIR]);
sp -= 4;
store_word (sp, State.regs[REG_LAR]);
sp -= 4;
}
State.regs[REG_SP] -= IMM8;
State.regs[REG_MDR] = next_pc;
State.regs[REG_PC] += EXTEND16 (FETCH16(D16A, D16B));
nia = PC;
}
8.0xdd+8.D32A+8.D32B+8.D32C+8.D32D+8.REGS+8.IMM8:S6:::call
"call"
*mn10300
*am33
{
unsigned32 next_pc, sp;
unsigned32 mask;
PC = cia;
sp = State.regs[REG_SP];
next_pc = State.regs[REG_PC] + 7;
store_word(sp, next_pc);
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
)
{
if (mask & 0x4)
{
sp -= 4;
store_word (sp, State.regs[REG_E0 + 2]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 3]);
}
if (mask & 0x2)
{
sp -= 4;
store_word (sp, State.regs[REG_E0 + 4]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 5]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 6]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 7]);
}
if (mask & 0x1)
{
sp -= 4;
store_word (sp, State.regs[REG_E0 + 0]);
sp -= 4;
store_word (sp, State.regs[REG_E0 + 1]);
sp -= 16;
}
}
if (mask & 0x80)
{
sp -= 4;
store_word (sp, State.regs[REG_D0 + 2]);
}
if (mask & 0x40)
{
sp -= 4;
store_word (sp, State.regs[REG_D0 + 3]);
}
if (mask & 0x20)
{
sp -= 4;
store_word (sp, State.regs[REG_A0 + 2]);
}
if (mask & 0x10)
{
sp -= 4;
store_word (sp, State.regs[REG_A0 + 3]);
}
if (mask & 0x8)
{
sp -= 4;
store_word (sp, State.regs[REG_D0]);
sp -= 4;
store_word (sp, State.regs[REG_D0 + 1]);
sp -= 4;
store_word (sp, State.regs[REG_A0]);
sp -= 4;
store_word (sp, State.regs[REG_A0 + 1]);
sp -= 4;
store_word (sp, State.regs[REG_MDR]);
sp -= 4;
store_word (sp, State.regs[REG_LIR]);
sp -= 4;
store_word (sp, State.regs[REG_LAR]);
sp -= 4;
}
State.regs[REG_SP] -= IMM8;
State.regs[REG_MDR] = next_pc;
State.regs[REG_PC] += FETCH32(D32A, D32B, D32C, D32D);
nia = PC;
}
8.0xdf+8.REGS+8.IMM8:S2:::ret
"ret"
*mn10300
*am33
{
unsigned32 sp, offset;
unsigned32 mask;
PC = cia;
State.regs[REG_SP] += IMM8;
sp = State.regs[REG_SP];
offset = -4;
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
)
{
if (mask & 0x4)
{
State.regs[REG_E0 + 2] = load_word (sp + offset);
offset -= 4;
State.regs[REG_E0 + 3] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x2)
{
State.regs[REG_E0 + 4] = load_word (sp + offset);
offset -= 4;
State.regs[REG_E0 + 5] = load_word (sp + offset);
offset -= 4;
State.regs[REG_E0 + 6] = load_word (sp + offset);
offset -= 4;
State.regs[REG_E0 + 7] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x1)
{
offset -= 16;
State.regs[REG_E0 + 0] = load_word (sp + offset);
offset -= 4;
State.regs[REG_E0 + 1] = load_word (sp + offset);
offset -= 4;
}
}
if (mask & 0x80)
{
State.regs[REG_D0 + 2] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x40)
{
State.regs[REG_D0 + 3] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x20)
{
State.regs[REG_A0 + 2] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x10)
{
State.regs[REG_A0 + 3] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x8)
{
State.regs[REG_D0] = load_word (sp + offset);
offset -= 4;
State.regs[REG_D0 + 1] = load_word (sp + offset);
offset -= 4;
State.regs[REG_A0] = load_word (sp + offset);
offset -= 4;
State.regs[REG_A0 + 1] = load_word (sp + offset);
offset -= 4;
State.regs[REG_MDR] = load_word (sp + offset);
offset -= 4;
State.regs[REG_LIR] = load_word (sp + offset);
offset -= 4;
State.regs[REG_LAR] = load_word (sp + offset);
offset -= 4;
}
State.regs[REG_PC] = load_word(sp);
nia = PC;
}
8.0xde+8.REGS+8.IMM8:S2:::retf
"retf"
*mn10300
*am33
{
unsigned32 sp, offset;
unsigned32 mask;
PC = cia;
State.regs[REG_SP] += IMM8;
sp = State.regs[REG_SP];
State.regs[REG_PC] = State.regs[REG_MDR];
offset = -4;
mask = REGS;
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
)
{
if (mask & 0x4)
{
State.regs[REG_E0 + 2] = load_word (sp + offset);
offset -= 4;
State.regs[REG_E0 + 3] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x2)
{
State.regs[REG_E0 + 4] = load_word (sp + offset);
offset -= 4;
State.regs[REG_E0 + 5] = load_word (sp + offset);
offset -= 4;
State.regs[REG_E0 + 6] = load_word (sp + offset);
offset -= 4;
State.regs[REG_E0 + 7] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x1)
{
offset -= 16;
State.regs[REG_E0 + 0] = load_word (sp + offset);
offset -= 4;
State.regs[REG_E0 + 1] = load_word (sp + offset);
offset -= 4;
}
}
if (mask & 0x80)
{
State.regs[REG_D0 + 2] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x40)
{
State.regs[REG_D0 + 3] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x20)
{
State.regs[REG_A0 + 2] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x10)
{
State.regs[REG_A0 + 3] = load_word (sp + offset);
offset -= 4;
}
if (mask & 0x8)
{
State.regs[REG_D0] = load_word (sp + offset);
offset -= 4;
State.regs[REG_D0 + 1] = load_word (sp + offset);
offset -= 4;
State.regs[REG_A0] = load_word (sp + offset);
offset -= 4;
State.regs[REG_A0 + 1] = load_word (sp + offset);
offset -= 4;
State.regs[REG_MDR] = load_word (sp + offset);
offset -= 4;
State.regs[REG_LIR] = load_word (sp + offset);
offset -= 4;
State.regs[REG_LAR] = load_word (sp + offset);
offset -= 4;
}
nia = PC;
}
:include::am33:am33.igen