#ifndef TM_D30V_H
#define TM_D30V_H
#define TARGET_BYTE_ORDER BIG_ENDIAN
#define FUNCTION_START_OFFSET 0
#define DMEM_START 0x20000000
#define IMEM_START 0x00000000
#define STACK_START 0x20007ffe
struct frame_info;
struct frame_saved_regs;
struct type;
struct value;
extern CORE_ADDR d30v_skip_prologue (CORE_ADDR);
#define SKIP_PROLOGUE(ip) (d30v_skip_prologue (ip))
#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
#define BREAKPOINT {0x00, 0xb0, 0x00, 0x00,\
0x00, 0xf0, 0x00, 0x00}
#define DECR_PC_AFTER_BREAK 0
#define REGISTER_NAMES \
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
"r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
"spi", "spu", \
"psw", "bpsw", "pc", "bpc", "dpsw", "dpc", "cr6", "rpt_c", \
"rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "eit_vb",\
"int_s", "int_m", "a0", "a1" \
}
#define NUM_REGS 86
#define R0_REGNUM 0
#define FP_REGNUM 61
#define LR_REGNUM 62
#define SP_REGNUM 63
#define SPI_REGNUM 64
#define SPU_REGNUM 65
#define CREGS_START 66
#define PSW_REGNUM (CREGS_START + 0)
#define PSW_SM (((unsigned long)0x80000000) >> 0)
#define PSW_EA (((unsigned long)0x80000000) >> 2)
#define PSW_DB (((unsigned long)0x80000000) >> 3)
#define PSW_DS (((unsigned long)0x80000000) >> 4)
#define PSW_IE (((unsigned long)0x80000000) >> 5)
#define PSW_RP (((unsigned long)0x80000000) >> 6)
#define PSW_MD (((unsigned long)0x80000000) >> 7)
#define PSW_F0 (((unsigned long)0x80000000) >> 17)
#define PSW_F1 (((unsigned long)0x80000000) >> 19)
#define PSW_F2 (((unsigned long)0x80000000) >> 21)
#define PSW_F3 (((unsigned long)0x80000000) >> 23)
#define PSW_S (((unsigned long)0x80000000) >> 25)
#define PSW_V (((unsigned long)0x80000000) >> 27)
#define PSW_VA (((unsigned long)0x80000000) >> 29)
#define PSW_C (((unsigned long)0x80000000) >> 31)
#define BPSW_REGNUM (CREGS_START + 1)
#define PC_REGNUM (CREGS_START + 2)
#define BPC_REGNUM (CREGS_START + 3)
#define DPSW_REGNUM (CREGS_START + 4)
#define DPC_REGNUM (CREGS_START + 5)
#define RPT_C_REGNUM (CREGS_START + 7)
#define RPT_S_REGNUM (CREGS_START + 8)
#define RPT_E_REGNUM (CREGS_START + 9)
#define MOD_S_REGNUM (CREGS_START + 10)
#define MOD_E_REGNUM (CREGS_START + 11)
#define IBA_REGNUM (CREGS_START + 14)
#define EIT_VB_REGNUM (CREGS_START + 15)
#define INT_S_REGNUM (CREGS_START + 16)
#define INT_M_REGNUM (CREGS_START + 17)
#define A0_REGNUM 84
#define A1_REGNUM 85
#define REGISTER_BYTES ((NUM_REGS - 2) * 4 + 2 * 8)
#define REGISTER_BYTE(N) \
( ((N) >= A0_REGNUM) ? ( ((N) - A0_REGNUM) * 8 + A0_REGNUM * 4 ) : ((N) * 4) )
#define REGISTER_RAW_SIZE(N) ( ((N) >= A0_REGNUM) ? 8 : 4 )
#define REGISTER_VIRTUAL_SIZE(N) REGISTER_RAW_SIZE(N)
#define MAX_REGISTER_RAW_SIZE 8
#define MAX_REGISTER_VIRTUAL_SIZE 8
#define REGISTER_VIRTUAL_TYPE(N) \
( ((N) < A0_REGNUM ) ? builtin_type_long : builtin_type_long_long)
#define CANNOT_STORE_REGISTER(regno) ((regno) == R0_REGNUM)
void d30v_do_registers_info (int regnum, int fpregs);
#define DO_REGISTERS_INFO d30v_do_registers_info
#define STORE_STRUCT_RETURN(ADDR, SP) \
{ write_register (2, (ADDR)); }
#define STORE_RETURN_VALUE(TYPE,VALBUF) \
write_register_bytes (REGISTER_BYTE(2), VALBUF, TYPE_LENGTH (TYPE))
#define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) (((CORE_ADDR *)(REGBUF))[2])
#define EXTRA_FRAME_INFO \
CORE_ADDR return_pc; \
CORE_ADDR dummy; \
int frameless; \
int size;
#define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \
d30v_init_extra_frame_info(fromleaf, fi)
extern void d30v_init_extra_frame_info (int fromleaf, struct frame_info *fi);
#define FRAMELESS_FUNCTION_INVOCATION(FI) \
(frameless_look_for_prologue (FI))
CORE_ADDR d30v_frame_chain (struct frame_info *frame);
#define FRAME_CHAIN(FRAME) d30v_frame_chain(FRAME)
extern int d30v_frame_chain_valid (CORE_ADDR, struct frame_info *);
#define FRAME_CHAIN_VALID(chain, thisframe) d30v_frame_chain_valid (chain, thisframe)
#define FRAME_SAVED_PC(FRAME) ((FRAME)->return_pc)
#define FRAME_ARGS_ADDRESS(fi) (fi)->frame
#define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
void d30v_init_frame_pc (int fromleaf, struct frame_info *prev);
#define INIT_FRAME_PC_FIRST(fromleaf, prev) d30v_init_frame_pc(fromleaf, prev)
#define INIT_FRAME_PC(fromleaf, prev)
#define SAVED_PC_AFTER_CALL(frame) (read_register(LR_REGNUM))
#define FRAME_NUM_ARGS(fi) (-1)
#define FRAME_ARGS_SKIP 0
#define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
d30v_frame_find_saved_regs(frame_info, &(frame_saved_regs))
extern void d30v_frame_find_saved_regs (struct frame_info *,
struct frame_saved_regs *);
#define CALL_DUMMY { 0 }
#define PUSH_DUMMY_FRAME
#define CALL_DUMMY_START_OFFSET 0
#define CALL_DUMMY_LOCATION AT_ENTRY_POINT
#define CALL_DUMMY_BREAKPOINT_OFFSET (0)
extern CORE_ADDR d30v_call_dummy_address (void);
#define CALL_DUMMY_ADDRESS() d30v_call_dummy_address()
#define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \
sp = d30v_fix_call_dummy (dummyname, pc, fun, nargs, args, type, gcc_p)
#define PC_IN_CALL_DUMMY(pc, sp, frame_address) ( pc == IMEM_START + 4 )
extern CORE_ADDR d30v_fix_call_dummy (char *, CORE_ADDR, CORE_ADDR,
int, struct value **,
struct type *, int);
#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
(d30v_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr)))
extern CORE_ADDR d30v_push_arguments (int, struct value **, CORE_ADDR, int,
CORE_ADDR);
#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
d30v_extract_return_value(TYPE, REGBUF, VALBUF)
extern void d30v_extract_return_value (struct type *, char *, char *);
#define POP_FRAME d30v_pop_frame();
extern void d30v_pop_frame (void);
#define REGISTER_SIZE 4
#if 0
#define TARGET_READ_SP() ((read_register (PSW_REGNUM) & PSW_SM) \
? read_register (SPU_REGNUM) \
: read_register (SPI_REGNUM))
#define TARGET_WRITE_SP(val) ((read_register (PSW_REGNUM) & PSW_SM) \
? write_register (SPU_REGNUM, (val)) \
: write_register (SPI_REGNUM, (val)))
#endif
#define STACK_ALIGN(len) (((len) + 7 ) & ~7)
#define SIM_HAS_BREAKPOINTS
#endif