#ifndef GCC_ARM_H
#define GCC_ARM_H
#ifndef TARGET_MACHO
#define TARGET_MACHO 0
#endif
#define TARGET_INTERWORK (interwork_option == 1)
extern char arm_arch_name[];
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
\
builtin_define ("__arm__"); \
builtin_define ("__APCS_32__"); \
if (TARGET_THUMB) \
builtin_define ("__thumb__"); \
\
if (TARGET_BIG_END) \
{ \
builtin_define ("__ARMEB__"); \
if (TARGET_THUMB) \
builtin_define ("__THUMBEB__"); \
if (TARGET_LITTLE_WORDS) \
builtin_define ("__ARMWEL__"); \
} \
else \
{ \
builtin_define ("__ARMEL__"); \
if (TARGET_THUMB) \
builtin_define ("__THUMBEL__"); \
} \
\
if (TARGET_SOFT_FLOAT) \
builtin_define ("__SOFTFP__"); \
\
if (TARGET_VFP) \
builtin_define ("__VFP_FP__"); \
\
\
if (arm_cpp_interwork) \
builtin_define ("__THUMB_INTERWORK__"); \
\
builtin_assert ("cpu=arm"); \
builtin_assert ("machine=arm"); \
\
builtin_define (arm_arch_name); \
if (arm_arch_cirrus) \
builtin_define ("__MAVERICK__"); \
if (arm_arch_xscale) \
builtin_define ("__XSCALE__"); \
if (arm_arch_iwmmxt) \
builtin_define ("__IWMMXT__"); \
if (TARGET_AAPCS_BASED) \
builtin_define ("__ARM_EABI__"); \
} while (0)
enum processor_type
{
#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
IDENT,
#include "arm-cores.def"
#undef ARM_CORE
arm_none
};
enum target_cpus
{
#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
TARGET_CPU_##IDENT,
#include "arm-cores.def"
#undef ARM_CORE
TARGET_CPU_generic
};
extern enum processor_type arm_tune;
typedef enum arm_cond_code
{
ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
}
arm_cc;
extern arm_cc arm_current_cc;
#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
extern int arm_target_label;
extern int arm_ccfsm_state;
extern GTY(()) rtx arm_target_insn;
extern GTY(()) rtx arm_compare_op0;
extern GTY(()) rtx arm_compare_op1;
extern rtx pool_vector_label;
extern int return_used_this_function;
extern GTY(()) rtx aof_pic_label;
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT TARGET_CPU_generic
#endif
#undef CPP_SPEC
#define CPP_SPEC "%(subtarget_cpp_spec) \
%{msoft-float:%{mhard-float: \
%e-msoft-float and -mhard_float may not be used together}} \
%{mbig-endian:%{mlittle-endian: \
%e-mbig-endian and -mlittle-endian may not be used together}}"
#ifndef CC1_SPEC
#define CC1_SPEC ""
#endif
#define EXTRA_SPECS \
{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
SUBTARGET_EXTRA_SPECS
#ifndef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#endif
#ifndef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC ""
#endif
#ifndef TARGET_VERSION
#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
#endif
#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
#define TARGET_IWMMXT (arm_arch_iwmmxt)
#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
#define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
#define TARGET_ARM (! TARGET_THUMB)
#define TARGET_EITHER 1
#define TARGET_BACKTRACE (leaf_function_p () \
? TARGET_TPCS_LEAF_FRAME \
: TARGET_TPCS_FRAME)
#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
#define TARGET_AAPCS_BASED \
(arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
#define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
#ifndef TARGET_BPABI
#define TARGET_BPABI false
#endif
#define OPTION_DEFAULT_SPECS \
{"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
{"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
{"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
{"float", \
"%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
{"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
{"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
{"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
enum arm_fp_model
{
ARM_FP_MODEL_UNKNOWN,
ARM_FP_MODEL_FPA,
ARM_FP_MODEL_MAVERICK,
ARM_FP_MODEL_VFP
};
extern enum arm_fp_model arm_fp_model;
enum fputype
{
FPUTYPE_NONE,
FPUTYPE_FPA,
FPUTYPE_FPA_EMU2,
FPUTYPE_FPA_EMU3,
FPUTYPE_MAVERICK,
FPUTYPE_VFP
};
#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
extern enum fputype arm_fpu_tune;
extern enum fputype arm_fpu_arch;
enum float_abi_type
{
ARM_FLOAT_ABI_SOFT,
ARM_FLOAT_ABI_SOFTFP,
ARM_FLOAT_ABI_HARD
};
extern enum float_abi_type arm_float_abi;
#ifndef TARGET_DEFAULT_FLOAT_ABI
#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
#endif
enum arm_abi_type
{
ARM_ABI_APCS,
ARM_ABI_ATPCS,
ARM_ABI_AAPCS,
ARM_ABI_IWMMXT,
ARM_ABI_AAPCS_LINUX
};
extern enum arm_abi_type arm_abi;
#ifndef ARM_DEFAULT_ABI
#define ARM_DEFAULT_ABI ARM_ABI_APCS
#endif
enum arm_tp_type {
TP_AUTO,
TP_SOFT,
TP_CP15
};
extern enum arm_tp_type target_thread_pointer;
extern int arm_arch3m;
extern int arm_arch4;
extern int arm_arch4t;
extern int arm_arch5;
extern int arm_arch5e;
extern int arm_arch6;
extern int arm_ld_sched;
extern int thumb_code;
extern int arm_tune_strongarm;
extern int arm_arch_cirrus;
extern int arm_arch_iwmmxt;
extern int arm_arch_xscale;
extern int arm_tune_xscale;
extern int arm_tune_wbuf;
extern int arm_cpp_interwork;
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APCS_FRAME)
#endif
#define CAN_DEBUG_WITHOUT_FP
#define OVERRIDE_OPTIONS arm_override_options ()
#ifndef NEED_GOT_RELOC
#define NEED_GOT_RELOC 0
#endif
#ifndef NEED_PLT_RELOC
#define NEED_PLT_RELOC 0
#endif
#ifndef GOT_PCREL
#define GOT_PCREL 1
#endif
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < 4) \
{ \
if (MODE == QImode) \
UNSIGNEDP = 1; \
else if (MODE == HImode) \
UNSIGNEDP = 1; \
(MODE) = SImode; \
}
#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
if ((GET_MODE_CLASS (MODE) == MODE_INT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
&& GET_MODE_SIZE (MODE) < 4) \
(MODE) = SImode; \
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
#if defined(__ARMEB__) && !defined(__ARMWEL__)
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#else
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#endif
#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
#define UNITS_PER_WORD 4
#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
#define DOUBLEWORD_ALIGNMENT 64
#define PARM_BOUNDARY 32
#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
#define PREFERRED_STACK_BOUNDARY \
(arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
#define FUNCTION_BOUNDARY arm_function_boundary ()
extern int arm_function_boundary (void);
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
#define EMPTY_FIELD_BOUNDARY 32
#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
#ifdef IN_TARGET_LIBS
#define BIGGEST_FIELD_ALIGNMENT 64
#endif
#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
((TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
extern int arm_structure_size_boundary;
#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
#endif
#define STRICT_ALIGNMENT 1
#ifndef WCHAR_TYPE
#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
#define WCHAR_TYPE_SIZE BITS_PER_WORD
#endif
#ifndef SIZE_TYPE
#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
#endif
#ifndef PTRDIFF_TYPE
#define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
#endif
#ifndef PCC_BITFIELD_TYPE_MATTERS
#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
#endif
#define FIXED_REGISTERS \
{ \
0,0,0,0,0,0,0,0, \
0,0,0,0,0,1,0,1, \
0,0,0,0,0,0,0,0, \
1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1 \
}
#define CALL_USED_REGISTERS \
{ \
1,1,1,1,0,0,0,0, \
0,0,0,0,1,1,1,1, \
1,1,1,1,0,0,0,0, \
1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1,1,1,1,1,1,1,1, \
1 \
}
#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
#endif
#define CONDITIONAL_REGISTER_USAGE \
{ \
int regno; \
\
if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
{ \
for (regno = FIRST_FPA_REGNUM; \
regno <= LAST_FPA_REGNUM; ++regno) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
} \
\
if (TARGET_THUMB && optimize_size) \
{ \
\
for (regno = FIRST_HI_REGNUM; \
regno <= LAST_HI_REGNUM; ++regno) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
} \
\
\
if (TARGET_THUMB) \
fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
\
if (TARGET_ARM && TARGET_HARD_FLOAT) \
{ \
if (TARGET_MAVERICK) \
{ \
for (regno = FIRST_FPA_REGNUM; \
regno <= LAST_FPA_REGNUM; ++ regno) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
for (regno = FIRST_CIRRUS_FP_REGNUM; \
regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
{ \
fixed_regs[regno] = 0; \
call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
} \
} \
if (TARGET_VFP) \
{ \
for (regno = FIRST_VFP_REGNUM; \
regno <= LAST_VFP_REGNUM; ++ regno) \
{ \
fixed_regs[regno] = 0; \
call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
} \
} \
} \
\
if (TARGET_REALLY_IWMMXT) \
{ \
regno = FIRST_IWMMXT_GR_REGNUM; \
\
for (regno = FIRST_IWMMXT_GR_REGNUM; \
regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
fixed_regs[regno] = 0; \
\
for (regno = FIRST_IWMMXT_REGNUM; \
regno <= LAST_IWMMXT_REGNUM; ++ regno) \
{ \
fixed_regs[regno] = 0; \
call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
} \
} \
\
if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
{ \
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
} \
else if (TARGET_APCS_STACK) \
{ \
fixed_regs[10] = 1; \
call_used_regs[10] = 1; \
} \
\
if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
|| TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
{ \
fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
if (TARGET_CALLER_INTERWORKING) \
global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
} \
SUBTARGET_CONDITIONAL_REGISTER_USAGE \
}
#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
case '@': \
fputs (ASM_COMMENT_START, FILE); \
break; \
\
case 'r': \
fputs (REGISTER_PREFIX, FILE); \
fputs (reg_names [va_arg (ARGS, int)], FILE); \
break;
#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
#define ARM_NUM_REGS(MODE) \
ARM_NUM_INTS (GET_MODE_SIZE (MODE))
#define ARM_NUM_REGS2(MODE, TYPE) \
ARM_NUM_INTS ((MODE) == BLKmode ? \
int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
#define NUM_ARG_REGS 4
#define ARG_REGISTER(N) (N - 1)
#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
#define FIRST_LO_REGNUM 0
#define LAST_LO_REGNUM 7
#define FIRST_HI_REGNUM 8
#define LAST_HI_REGNUM 11
#ifndef TARGET_UNWIND_INFO
#define MUST_USE_SJLJ_EXCEPTIONS 1
#endif
#define DWARF2_UNWIND_INFO 1
#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
#define ARM_EH_STACKADJ_REGNUM 2
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
#define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
#define ARM_HARD_FRAME_POINTER_REGNUM 7
#define THUMB_HARD_FRAME_POINTER_REGNUM 7
#define HARD_FRAME_POINTER_REGNUM \
(TARGET_ARM \
? ARM_HARD_FRAME_POINTER_REGNUM \
: THUMB_HARD_FRAME_POINTER_REGNUM)
#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
#define STACK_POINTER_REGNUM SP_REGNUM
#define FIRST_FPA_REGNUM 16
#define LAST_FPA_REGNUM 23
#define IS_FPA_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
#define FIRST_IWMMXT_GR_REGNUM 43
#define LAST_IWMMXT_GR_REGNUM 46
#define FIRST_IWMMXT_REGNUM 47
#define LAST_IWMMXT_REGNUM 62
#define IS_IWMMXT_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
#define IS_IWMMXT_GR_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
#define FRAME_POINTER_REGNUM 25
#define ARG_POINTER_REGNUM 26
#define FIRST_CIRRUS_FP_REGNUM 27
#define LAST_CIRRUS_FP_REGNUM 42
#define IS_CIRRUS_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
#define FIRST_VFP_REGNUM 63
#define LAST_VFP_REGNUM 94
#define IS_VFP_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
#define FIRST_PSEUDO_REGISTER 96
#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
#define SUBTARGET_FRAME_POINTER_REQUIRED 0
#endif
#define FRAME_POINTER_REQUIRED \
(current_function_has_nonlocal_label \
|| SUBTARGET_FRAME_POINTER_REQUIRED \
|| current_function_calls_builtin_ret_addr \
|| current_function_calls_builtin_frame_addr \
|| ! flag_omit_frame_pointer \
|| (TARGET_THUMB && ! leaf_function_p ()) \
|| (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()) \
|| (TARGET_ARM && regs_ever_live [LR_REGNUM]))
#define HARD_REGNO_NREGS(REGNO, MODE) \
((TARGET_ARM \
&& REGNO >= FIRST_FPA_REGNUM \
&& REGNO != FRAME_POINTER_REGNUM \
&& REGNO != ARG_POINTER_REGNUM) \
&& !IS_VFP_REGNUM (REGNO) \
? 1 : ARM_NUM_REGS (MODE))
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
arm_hard_regno_mode_ok ((REGNO), (MODE))
#define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
#define VALID_IWMMXT_REG_MODE(MODE) \
(arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
#define REG_ALLOC_ORDER \
{ \
3, 2, 1, 0, 12, 14, 4, 5, \
6, 7, 8, 10, 9, 11, 13, 15, \
16, 17, 18, 19, 20, 21, 22, 23, \
27, 28, 29, 30, 31, 32, 33, 34, \
35, 36, 37, 38, 39, 40, 41, 42, \
43, 44, 45, 46, 47, 48, 49, 50, \
51, 52, 53, 54, 55, 56, 57, 58, \
59, 60, 61, 62, \
24, 25, 26, \
78, 77, 76, 75, 74, 73, 72, 71, \
70, 69, 68, 67, 66, 65, 64, 63, \
79, 80, 81, 82, 83, 84, 85, 86, \
87, 88, 89, 90, 91, 92, 93, 94, \
95 \
}
#define DIMODE_REG_ALLOC_ORDER \
{ \
2, 3, 1, 0, 12, 14, 4, 5, \
6, 7, 8, 10, 9, 11, 13, 15, \
16, 17, 18, 19, 20, 21, 22, 23, \
27, 28, 29, 30, 31, 32, 33, 34, \
35, 36, 37, 38, 39, 40, 41, 42, \
43, 44, 45, 46, 47, 48, 49, 50, \
51, 52, 53, 54, 55, 56, 57, 58, \
59, 60, 61, 62, \
24, 25, 26, \
78, 77, 76, 75, 74, 73, 72, 71, \
70, 69, 68, 67, 66, 65, 64, 63, \
79, 80, 81, 82, 83, 84, 85, 86, \
87, 88, 89, 90, 91, 92, 93, 94, \
95 \
}
#define HARD_REGNO_RENAME_OK(SRC, DST) \
(! IS_INTERRUPT (cfun->machine->func_type) || \
regs_ever_live[DST])
enum reg_class
{
NO_REGS,
FPA_REGS,
CIRRUS_REGS,
VFP_REGS,
IWMMXT_GR_REGS,
IWMMXT_REGS,
LO_REGS,
STACK_REG,
BASE_REGS,
HI_REGS,
CC_REG,
VFPCC_REG,
GENERAL_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"FPA_REGS", \
"CIRRUS_REGS", \
"VFP_REGS", \
"IWMMXT_GR_REGS", \
"IWMMXT_REGS", \
"LO_REGS", \
"STACK_REG", \
"BASE_REGS", \
"HI_REGS", \
"CC_REG", \
"VFPCC_REG", \
"GENERAL_REGS", \
"ALL_REGS", \
}
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00FF0000, 0x00000000, 0x00000000 }, \
{ 0xF8000000, 0x000007FF, 0x00000000 }, \
{ 0x00000000, 0x80000000, 0x7FFFFFFF }, \
{ 0x00000000, 0x00007800, 0x00000000 }, \
{ 0x00000000, 0x7FFF8000, 0x00000000 }, \
{ 0x000000FF, 0x00000000, 0x00000000 }, \
{ 0x00002000, 0x00000000, 0x00000000 }, \
{ 0x000020FF, 0x00000000, 0x00000000 }, \
{ 0x0000FF00, 0x00000000, 0x00000000 }, \
{ 0x01000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x80000000 }, \
{ 0x0200FFFF, 0x00000000, 0x00000000 }, \
{ 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } \
}
#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
|| reg_classes_intersect_p (VFP_REGS, (CLASS)) \
: 0)
#define CLASS_LIKELY_SPILLED_P(CLASS) \
((TARGET_THUMB && (CLASS) == LO_REGS) \
|| (CLASS) == CC_REG)
#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
#define MODE_BASE_REG_CLASS(MODE) \
(TARGET_ARM ? GENERAL_REGS : \
(((MODE) == SImode) ? BASE_REGS : LO_REGS))
#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
#define SMALL_REGISTER_CLASSES TARGET_THUMB
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
(TARGET_ARM ? (CLASS) : \
((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
? ((true_regnum (X) == -1 ? LO_REGS \
: (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
: NO_REGS)) \
: NO_REGS)
#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
? ((true_regnum (X) == -1 ? LO_REGS \
: (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
: NO_REGS)) \
: NO_REGS)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
\
((TARGET_VFP && TARGET_HARD_FLOAT \
&& (CLASS) == VFP_REGS) \
? coproc_secondary_reload_class (MODE, X, FALSE) \
: (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
? coproc_secondary_reload_class (MODE, X, TRUE) \
: TARGET_ARM \
? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
? GENERAL_REGS : NO_REGS) \
: THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
\
((TARGET_VFP && TARGET_HARD_FLOAT \
&& (CLASS) == VFP_REGS) \
? coproc_secondary_reload_class (MODE, X, FALSE) : \
(TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
coproc_secondary_reload_class (MODE, X, TRUE) : \
\
(TARGET_MAVERICK && TARGET_HARD_FLOAT \
&& (CLASS) == CIRRUS_REGS \
&& (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
? GENERAL_REGS : \
(TARGET_ARM ? \
(((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
&& CONSTANT_P (X)) \
? GENERAL_REGS : \
(((MODE) == HImode && ! arm_arch4 \
&& (GET_CODE (X) == MEM \
|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
&& true_regnum (X) == -1))) \
? GENERAL_REGS : NO_REGS) \
: THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
do \
{ \
if (GET_CODE (X) == PLUS \
&& GET_CODE (XEXP (X, 0)) == REG \
&& REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
&& REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
&& GET_CODE (XEXP (X, 1)) == CONST_INT) \
{ \
HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
HOST_WIDE_INT low, high; \
\
if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
low = ((val & 0xf) ^ 0x8) - 0x8; \
else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
\
low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
else if (MODE == SImode \
|| (MODE == SFmode && TARGET_SOFT_FLOAT) \
|| ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
\
low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
\
low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
&& TARGET_HARD_FLOAT && TARGET_FPA) \
\
low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
else \
break; \
\
high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
^ (unsigned HOST_WIDE_INT) 0x80000000) \
- (unsigned HOST_WIDE_INT) 0x80000000); \
\
if (low == 0 || high == 0 || (high + low != val)) \
break; \
\
\
X = gen_rtx_PLUS (GET_MODE (X), \
gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
GEN_INT (high)), \
GEN_INT (low)); \
push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
VOIDmode, 0, 0, OPNUM, TYPE); \
goto WIN; \
} \
} \
while (0)
#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
do { \
rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
if (new_x) \
{ \
X = new_x; \
goto WIN; \
} \
} while (0)
#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
if (TARGET_ARM) \
ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
else \
THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
#define CLASS_MAX_NREGS(CLASS, MODE) \
(((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
(TARGET_ARM ? \
((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
(FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
(FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
(FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
(FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
(FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
(FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
(FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
(FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
2) \
: \
((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
#define STACK_GROWS_DOWNWARD 1
#define FRAME_GROWS_DOWNWARD 1
#define CALLER_INTERWORKING_SLOT_SIZE \
(TARGET_CALLER_INTERWORKING \
&& current_function_outgoing_args_size != 0 \
? UNITS_PER_WORD : 0)
#define STARTING_FRAME_OFFSET 0
#define ACCUMULATE_OUTGOING_ARGS 1
#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
#define LIBCALL_VALUE(MODE) \
(TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
&& GET_MODE_CLASS (MODE) == MODE_FLOAT \
? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
: TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
&& GET_MODE_CLASS (MODE) == MODE_FLOAT \
? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
: TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
: gen_rtx_REG (MODE, ARG_REGISTER (1)))
#define FUNCTION_VALUE(VALTYPE, FUNC) \
arm_function_value (VALTYPE, FUNC);
#define FUNCTION_VALUE_REGNO_P(REGNO) \
((REGNO) == ARG_REGISTER (1) \
|| (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
&& TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
|| ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
|| (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
&& TARGET_HARD_FLOAT_ABI && TARGET_FPA))
#define APPLY_RESULT_SIZE arm_apply_result_size()
#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
#define DEFAULT_PCC_STRUCT_RETURN 0
#define CALL_NORMAL 0x00000000
#define CALL_LONG 0x00000001
#define CALL_SHORT 0x00000002
#define ARM_FT_UNKNOWN 0
#define ARM_FT_NORMAL 1
#define ARM_FT_INTERWORKED 2
#define ARM_FT_ISR 4
#define ARM_FT_FIQ 5
#define ARM_FT_EXCEPTION 6
#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
#define ARM_FT_INTERRUPT (1 << 2)
#define ARM_FT_NAKED (1 << 3)
#define ARM_FT_VOLATILE (1 << 4)
#define ARM_FT_NESTED (1 << 5)
#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
#define IS_NAKED(t) (t & ARM_FT_NAKED)
#define IS_NESTED(t) (t & ARM_FT_NESTED)
typedef struct arm_stack_offsets GTY(())
{
int saved_args;
int frame;
int saved_regs;
int soft_frame;
int locals_base;
int outgoing_args;
}
arm_stack_offsets;
typedef struct machine_function GTY(())
{
rtx eh_epilogue_sp_ofs;
int far_jump_used;
int arg_pointer_live;
int lr_save_eliminated;
arm_stack_offsets stack_offsets;
unsigned long func_type;
int uses_anonymous_args;
int sibcall_blocked;
rtx pic_reg;
rtx call_via[14];
}
machine_function;
extern GTY(()) rtx thumb_call_via_label[14];
typedef struct
{
int nregs;
int iwmmxt_nregs;
int named_count;
int nargs;
int call_cookie;
int can_split;
} CUMULATIVE_ARGS;
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
#define FUNCTION_ARG_PADDING(MODE, TYPE) \
(arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
(arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
#define PAD_VARARGS_DOWN \
((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
(CUM).nargs += 1; \
if (arm_vector_mode_supported_p (MODE) \
&& (CUM).named_count > (CUM).nargs) \
(CUM).iwmmxt_nregs += 1; \
else \
(CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
? DOUBLEWORD_ALIGNMENT \
: PARM_BOUNDARY )
#define FUNCTION_ARG_REGNO_P(REGNO) \
(IN_RANGE ((REGNO), 0, 3) \
|| (TARGET_IWMMXT_ABI \
&& IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
#ifndef ARM_MCOUNT_NAME
#define ARM_MCOUNT_NAME "*mcount"
#endif
#ifndef ARM_FUNCTION_PROFILER
#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
{ \
char temp[20]; \
rtx sym; \
\
asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
IP_REGNUM, LR_REGNUM); \
assemble_name (STREAM, ARM_MCOUNT_NAME); \
fputc ('\n', STREAM); \
ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
assemble_aligned_integer (UNITS_PER_WORD, sym); \
}
#endif
#ifdef THUMB_FUNCTION_PROFILER
#define FUNCTION_PROFILER(STREAM, LABELNO) \
if (TARGET_ARM) \
ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
else \
THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
#else
#define FUNCTION_PROFILER(STREAM, LABELNO) \
ARM_FUNCTION_PROFILER (STREAM, LABELNO)
#endif
#define EXIT_IGNORE_STACK 1
#define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
#define USE_RETURN_INSN(ISCOND) \
(TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
{ ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM },\
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
#define CAN_ELIMINATE(FROM, TO) \
(((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
\
((TO) == STACK_POINTER_REGNUM \
&& !current_function_sp_is_unchanging) ? 0 : \
\
\
\
1)
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
if (TARGET_ARM) \
(OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
else \
(OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
#define DEBUGGER_ARG_OFFSET(value, addr) arm_debugger_arg_offset (value, addr)
#define INIT_EXPANDERS arm_init_expanders ()
#define ARM_TRAMPOLINE_TEMPLATE(FILE) \
{ \
asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
STATIC_CHAIN_REGNUM, PC_REGNUM); \
asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
PC_REGNUM, PC_REGNUM); \
assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
}
#define DOT_WORD ".word"
#define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
{ \
fprintf (FILE, "\t.code 32\n"); \
fprintf (FILE, ".Ltrampoline_start:\n"); \
asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
STATIC_CHAIN_REGNUM, PC_REGNUM); \
asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
IP_REGNUM, PC_REGNUM); \
asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
IP_REGNUM, IP_REGNUM); \
asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
\
fprintf (FILE, "\t" DOT_WORD "\t0\n"); \
fprintf (FILE, "\t" DOT_WORD "\t0\n"); \
\
fprintf (FILE, "\t.code 16\n"); \
}
#define TRAMPOLINE_TEMPLATE(FILE) \
if (TARGET_ARM) \
ARM_TRAMPOLINE_TEMPLATE (FILE) \
else \
THUMB_TRAMPOLINE_TEMPLATE (FILE)
#define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
#define TRAMPOLINE_ALIGNMENT 32
#ifndef INITIALIZE_TRAMPOLINE
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
emit_move_insn (gen_rtx_MEM (SImode, \
plus_constant (TRAMP, \
TARGET_ARM ? 8 : 16)), \
CXT); \
emit_move_insn (gen_rtx_MEM (SImode, \
plus_constant (TRAMP, \
TARGET_ARM ? 12 : 20)), \
FNADDR); \
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
0, VOIDmode, 2, TRAMP, Pmode, \
plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
}
#endif
#define HAVE_POST_INCREMENT 1
#define HAVE_PRE_INCREMENT TARGET_ARM
#define HAVE_POST_DECREMENT TARGET_ARM
#define HAVE_PRE_DECREMENT TARGET_ARM
#define HAVE_PRE_MODIFY_DISP TARGET_ARM
#define HAVE_POST_MODIFY_DISP TARGET_ARM
#define HAVE_PRE_MODIFY_REG TARGET_ARM
#define HAVE_POST_MODIFY_REG TARGET_ARM
#define TEST_REGNO(R, TEST, VALUE) \
((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
(TEST_REGNO (REGNO, <, PC_REGNUM) \
|| TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
|| TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
#define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
(TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
|| (GET_MODE_SIZE (MODE) >= 4 \
&& TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
(TARGET_THUMB \
? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
: ARM_REGNO_OK_FOR_BASE_P (REGNO))
#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
REGNO_OK_FOR_INDEX_P (X)
#define REGNO_OK_FOR_INDEX_P(REGNO) \
REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
#define MAX_REGS_PER_ADDRESS 2
#ifdef AOF_ASSEMBLER
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
#else
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == SYMBOL_REF \
&& (CONSTANT_POOL_ADDRESS_P (X) \
|| (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
#endif
#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
#define THUMB_LEGITIMATE_CONSTANT_P(X) \
( GET_CODE (X) == CONST_INT \
|| GET_CODE (X) == CONST_DOUBLE \
|| CONSTANT_ADDRESS_P (X) \
|| flag_pic)
#define LEGITIMATE_CONSTANT_P(X) \
(!arm_tls_referenced_p (X) \
&& (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) \
: THUMB_LEGITIMATE_CONSTANT_P (X)))
#define SYMBOL_SHORT_CALL ((SYMBOL_FLAG_MACH_DEP) << 3)
#define SYMBOL_LONG_CALL ((SYMBOL_FLAG_MACH_DEP) << 4)
#define SHORT_CALL_FLAG_CHAR '^'
#define LONG_CALL_FLAG_CHAR '#'
#define SYMBOL_SHORT_CALL_ATTR_P(SYMBOL) \
(SYMBOL_REF_FLAGS (SYMBOL) & SYMBOL_SHORT_CALL)
#define SYMBOL_LONG_CALL_ATTR_P(SYMBOL) \
(SYMBOL_REF_FLAGS (SYMBOL) & SYMBOL_LONG_CALL)
#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
#define SUBTARGET_NAME_ENCODING_LENGTHS
#endif
#define ARM_NAME_ENCODING_LENGTHS \
case '*': return 1; \
SUBTARGET_NAME_ENCODING_LENGTHS
#undef ASM_OUTPUT_LABELREF
#define ASM_OUTPUT_LABELREF(FILE, NAME) \
arm_asm_output_labelref (FILE, NAME)
#ifndef ARM_EABI_CTORS_SECTION_OP
#define ARM_EABI_CTORS_SECTION_OP \
"\t.section\t.init_array,\"aw\",%init_array"
#endif
#ifndef ARM_EABI_DTORS_SECTION_OP
#define ARM_EABI_DTORS_SECTION_OP \
"\t.section\t.fini_array,\"aw\",%fini_array"
#endif
#define ARM_CTORS_SECTION_OP \
"\t.section\t.ctors,\"aw\",%progbits"
#define ARM_DTORS_SECTION_OP \
"\t.section\t.dtors,\"aw\",%progbits"
#undef CTORS_SECTION_ASM_OP
#undef DTORS_SECTION_ASM_OP
#ifndef IN_LIBGCC2
# define CTORS_SECTION_ASM_OP \
(TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
# define DTORS_SECTION_ASM_OP \
(TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
#else
# ifdef __ARM_EABI__
# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
# define CTOR_LIST_END
# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
# define DTOR_LIST_END
# else
# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
# endif
#endif
#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
#endif
#define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
arm_encode_call_attribute (DECL, SYMBOL_SHORT_CALL)
#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
#ifdef TARGET_UNWIND_INFO
#define ARM_EABI_UNWIND_TABLES \
((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
#else
#define ARM_EABI_UNWIND_TABLES 0
#endif
#ifndef REG_OK_STRICT
#define ARM_REG_OK_FOR_BASE_P(X) \
(REGNO (X) <= LAST_ARM_REGNUM \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER \
|| REGNO (X) == FRAME_POINTER_REGNUM \
|| REGNO (X) == ARG_POINTER_REGNUM)
#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
(REGNO (X) <= LAST_LO_REGNUM \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER \
|| (GET_MODE_SIZE (MODE) >= 4 \
&& (REGNO (X) == STACK_POINTER_REGNUM \
|| (X) == hard_frame_pointer_rtx \
|| (X) == arg_pointer_rtx)))
#define REG_STRICT_P 0
#else
#define ARM_REG_OK_FOR_BASE_P(X) \
ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
#define REG_STRICT_P 1
#endif
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
(TARGET_THUMB \
? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
: ARM_REG_OK_FOR_BASE_P (X))
#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
#define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
#define REG_OK_FOR_INDEX_P(X) \
(TARGET_THUMB \
? THUMB_REG_OK_FOR_INDEX_P (X) \
: ARM_REG_OK_FOR_INDEX_P (X))
#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
REG_OK_FOR_INDEX_P (X)
#define ARM_BASE_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
#define ARM_INDEX_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
{ \
if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
goto WIN; \
}
#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
{ \
if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
goto WIN; \
}
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
if (TARGET_ARM) \
ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
else \
THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
do { \
X = arm_legitimize_address (X, OLDX, MODE); \
} while (0)
#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
do { \
X = thumb_legitimize_address (X, OLDX, MODE); \
} while (0)
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
do { \
if (TARGET_ARM) \
ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
else \
THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
\
if (memory_address_p (MODE, X)) \
goto WIN; \
} while (0)
#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
{ \
if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
|| GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
goto LABEL; \
}
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
if (TARGET_ARM) \
ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
#define CASE_VECTOR_MODE Pmode
#define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB)
#define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
(TARGET_ARM ? SImode \
: (MIN_OFFSET) >= -256 && (MAX_OFFSET) <= 254 \
? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
: (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 510 \
? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
: (MIN_OFFSET) >= -65536 && (MAX_OFFSET) <= 65534 \
? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, HImode) \
: SImode)
#define ASM_OUTPUT_ADDR_DIFF_VEC(LABEL, BODY) \
do { \
int idx, size = GET_MODE_SIZE (GET_MODE (BODY)); \
int pack = (TARGET_THUMB) ? 2 : 4; \
\
\
int base_label_no = CODE_LABEL_NUMBER (LABEL); \
int vlen = XVECLEN (BODY, 1); \
const char* directive; \
if (GET_MODE (BODY) == QImode) \
directive = ".byte"; \
else if (GET_MODE (BODY) == HImode) \
directive = ".short"; \
else \
{ \
pack = 1; \
directive = ".long"; \
} \
\
targetm.asm_out.internal_label (file, "L", base_label_no); \
\
if (TARGET_THUMB) \
asm_fprintf (file, "\t%s\t%d @ size\n", directive, vlen - 1); \
for (idx = 0; idx < vlen; idx++) \
{ \
rtx target_label = XEXP (XVECEXP (BODY, 1, idx), 0); \
\
if (GET_MODE (BODY) != SImode) \
{ \
\
gcc_assert (!TARGET_ARM); \
\
asm_fprintf (file, "\t%s\t(L%d-L%d)/%d\n", \
directive, \
CODE_LABEL_NUMBER (target_label), base_label_no, pack); \
} \
\
else if (!TARGET_THUMB) \
asm_fprintf (file, "\tb\tL%d\n", \
CODE_LABEL_NUMBER (target_label)); \
else \
\
asm_fprintf (file, "\t%s\tL%d-L%d\n", \
directive, \
CODE_LABEL_NUMBER (target_label), base_label_no); \
} \
\
vlen = (vlen + 1) * size; \
while (vlen % pack != 0) \
{ \
asm_fprintf (file, "\t%s\t0 @ pad\n", directive); \
vlen += size; \
} \
} while (0)
#define ASM_OUTPUT_ADDR_VEC(LABEL, BODY) \
do \
{ \
int vlen = XVECLEN (BODY, 0); \
int idx; \
if (GET_CODE (BODY) != ADDR_VEC) \
gcc_unreachable (); \
for (idx = 0; idx < vlen; idx++) \
{ \
ASM_OUTPUT_ADDR_VEC_ELT \
(file, CODE_LABEL_NUMBER (XEXP \
(XVECEXP (BODY, 0, idx), 0))); \
} \
} \
while (0)
#ifndef DEFAULT_SIGNED_CHAR
#define DEFAULT_SIGNED_CHAR 0
#endif
#define MOVE_MAX 4
#undef MOVE_RATIO
#define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
#define WORD_REGISTER_OPERATIONS
#define LOAD_EXTEND_OP(MODE) \
(TARGET_THUMB ? ZERO_EXTEND : \
((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
: ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
#define SLOW_BYTE_ACCESS 0
#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define NO_FUNCTION_CSE 1
#define COMBINE_TRY_RETAIN 1
#define Pmode SImode
#define FUNCTION_MODE Pmode
#define IFCVT_MODIFY_MULTIPLE_TESTS(CE_INFO, BB, TRUE_EXPR, FALSE_EXPR) \
arm_ifcvt_modify_multiple_tests (CE_INFO, BB, &TRUE_EXPR, &FALSE_EXPR)
#define ARM_FRAME_RTX(X) \
( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
|| (X) == arg_pointer_rtx)
#define MEMORY_MOVE_COST(M, CLASS, IN) \
(TARGET_ARM ? 10 : \
((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
* (CLASS == LO_REGS ? 1 : 2)))
#define BRANCH_COST \
(TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
extern unsigned arm_pic_register;
#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
#define LEGITIMATE_PIC_OPERAND_P(X) \
(!(symbol_mentioned_p (X) \
|| label_mentioned_p (X) \
|| (GET_CODE (X) == SYMBOL_REF \
&& CONSTANT_POOL_ADDRESS_P (X) \
&& (symbol_mentioned_p (get_pool_constant (X)) \
|| label_mentioned_p (get_pool_constant (X))))) \
|| tls_mentioned_p (X))
#define LEGITIMATE_DYNAMIC_NO_PIC_OPERAND_P(X) \
(! non_local_symbol_mentioned_p (X))
#define LEGITIMATE_INDIRECT_OPERAND_P(X) \
((! flag_pic || LEGITIMATE_PIC_OPERAND_P(X)) \
&& (! MACHO_DYNAMIC_NO_PIC_P \
|| LEGITIMATE_DYNAMIC_NO_PIC_OPERAND_P(X)))
extern int making_const_table;
#define REGISTER_TARGET_PRAGMAS() do { \
c_register_pragma (0, "long_calls", arm_pr_long_calls); \
c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
} while (0)
#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
#define REVERSIBLE_CC_MODE(MODE) 1
#define REVERSE_CONDITION(CODE,MODE) \
(((MODE) == CCFPmode || (MODE) == CCFPEmode) \
? reverse_condition_maybe_unordered (code) \
: reverse_condition (code))
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
do \
{ \
if (GET_CODE (OP1) == CONST_INT \
&& ! (const_ok_for_arm (INTVAL (OP1)) \
|| (const_ok_for_arm (- INTVAL (OP1))))) \
{ \
rtx const_op = OP1; \
CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
&const_op); \
OP1 = const_op; \
} \
} \
while (0)
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
#undef ASM_APP_OFF
#define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
do \
{ \
if (TARGET_ARM) \
asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
STACK_POINTER_REGNUM, REGNO); \
else \
asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
} while (0)
#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
do \
{ \
if (TARGET_ARM) \
asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
STACK_POINTER_REGNUM, REGNO); \
else \
asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
} while (0)
#undef ASM_OUTPUT_CASE_LABEL
#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
do \
{ \
if (TARGET_THUMB) \
ASM_OUTPUT_ALIGN (FILE, 2); \
(*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
} \
while (0)
#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
do \
{ \
if (TARGET_THUMB) \
{ \
if (is_called_in_ARM_mode (DECL) \
|| current_function_is_thunk) \
fprintf (STREAM, "\t.code 32\n") ; \
else \
\
{ \
fputs ("\t.code 16\n", STREAM); \
fputs ("\t.thumb_func ", STREAM); \
if (TARGET_MACHO) \
assemble_name (STREAM, (char *) NAME); \
putc ('\n', STREAM); \
} \
\
} \
if (TARGET_POKE_FUNCTION_NAME) \
arm_poke_function_name (STREAM, (char *) NAME); \
} \
while (0)
#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
do \
{ \
const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
\
if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
{ \
fprintf (FILE, "\t.thumb_set "); \
assemble_name (FILE, LABEL1); \
fprintf (FILE, ","); \
assemble_name (FILE, LABEL2); \
fprintf (FILE, "\n"); \
} \
else \
ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
} \
while (0)
#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
if ((LOG) != 0) \
{ \
if ((MAX_SKIP) == 0) \
fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
else \
fprintf ((FILE), "\t.p2align %d,,%d\n", \
(int) (LOG), (int) (MAX_SKIP)); \
}
#endif
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
if (TARGET_ARM && optimize) \
arm_final_prescan_insn (INSN); \
else if (TARGET_THUMB) \
thumb_final_prescan_insn (INSN)
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
(CODE == '@' || CODE == '|' \
\
|| CODE == '.' \
|| (TARGET_ARM && (CODE == '?')) \
|| (TARGET_THUMB && (CODE == '_')))
#define PRINT_OPERAND(STREAM, X, CODE) \
arm_print_operand (STREAM, X, CODE)
#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
(HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
: ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
? ((~ (unsigned HOST_WIDE_INT) 0) \
& ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
: 0))))
#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
{ \
int is_minus = GET_CODE (X) == MINUS; \
\
if (GET_CODE (X) == REG) \
asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
else if (GET_CODE (X) == PLUS || is_minus) \
{ \
rtx base = XEXP (X, 0); \
rtx index = XEXP (X, 1); \
HOST_WIDE_INT offset = 0; \
if (GET_CODE (base) != REG) \
{ \
\
\
rtx temp = base; \
base = index; \
index = temp; \
} \
switch (GET_CODE (index)) \
{ \
case CONST_INT: \
offset = INTVAL (index); \
if (is_minus) \
offset = -offset; \
asm_fprintf (STREAM, "[%r, #%wd]", \
REGNO (base), offset); \
break; \
\
case REG: \
asm_fprintf (STREAM, "[%r, %s%r]", \
REGNO (base), is_minus ? "-" : "", \
REGNO (index)); \
break; \
\
case MULT: \
case ASHIFTRT: \
case LSHIFTRT: \
case ASHIFT: \
case ROTATERT: \
{ \
asm_fprintf (STREAM, "[%r, %s%r", \
REGNO (base), is_minus ? "-" : "", \
REGNO (XEXP (index, 0))); \
arm_print_operand (STREAM, index, 'S'); \
fputs ("]", STREAM); \
break; \
} \
\
default: \
gcc_unreachable (); \
} \
} \
else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
|| GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
{ \
extern enum machine_mode output_memory_reference_mode; \
\
gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
\
if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
asm_fprintf (STREAM, "[%r, #%s%d]!", \
REGNO (XEXP (X, 0)), \
GET_CODE (X) == PRE_DEC ? "-" : "", \
GET_MODE_SIZE (output_memory_reference_mode)); \
else \
asm_fprintf (STREAM, "[%r], #%s%d", \
REGNO (XEXP (X, 0)), \
GET_CODE (X) == POST_DEC ? "-" : "", \
GET_MODE_SIZE (output_memory_reference_mode)); \
} \
else if (GET_CODE (X) == PRE_MODIFY) \
{ \
asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
asm_fprintf (STREAM, "#%wd]!", \
INTVAL (XEXP (XEXP (X, 1), 1))); \
else \
asm_fprintf (STREAM, "%r]!", \
REGNO (XEXP (XEXP (X, 1), 1))); \
} \
else if (GET_CODE (X) == POST_MODIFY) \
{ \
asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
asm_fprintf (STREAM, "#%wd", \
INTVAL (XEXP (XEXP (X, 1), 1))); \
else \
asm_fprintf (STREAM, "%r", \
REGNO (XEXP (XEXP (X, 1), 1))); \
} \
else output_addr_const (STREAM, X); \
}
#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
{ \
if (GET_CODE (X) == REG) \
asm_fprintf (STREAM, "[%r]", REGNO (X)); \
else if (GET_CODE (X) == POST_INC) \
asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
else if (GET_CODE (X) == PLUS) \
{ \
gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
asm_fprintf (STREAM, "[%r, #%wd]", \
REGNO (XEXP (X, 0)), \
INTVAL (XEXP (X, 1))); \
else \
asm_fprintf (STREAM, "[%r, %r]", \
REGNO (XEXP (X, 0)), \
REGNO (XEXP (X, 1))); \
} \
else \
output_addr_const (STREAM, X); \
}
#define PRINT_OPERAND_ADDRESS(STREAM, X) \
if (TARGET_ARM) \
ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
else \
THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
#define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
if (arm_output_addr_const_extra (file, x) == FALSE) \
goto fail
#define RETURN_ADDR_RTX(COUNT, FRAME) \
arm_return_addr (COUNT, FRAME)
#define RETURN_ADDR_MASK26 (0x03fffffc)
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
#define MASK_RETURN_ADDR \
\
((arm_arch4 || TARGET_THUMB) \
? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
: arm_gen_return_addr_mask ())
#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
optimization_options ((LEVEL), (SIZE))
#define TIE_PSEUDOS 1
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
arm_adjust_insn_length ((INSN), &(LENGTH))
#define DEBUGGER_AUTO_OFFSET(X) arm_local_debug_offset (X)
#define ALLOW_ELIMINATION_TO_SP
#define LABEL_ALIGN(LABEL) arm_label_align(LABEL)
#define TARGET_EXTRA_CASES (TARGET_THUMB ? 1 : 0)
#define TARGET_EXACT_SIZE_CALCULATIONS
#define TARGET_UNEXPANDED_PROLOGUE_SIZE \
(TARGET_THUMB ? count_thumb_unexpanded_prologue () : 0)
#define TARGET_ALIGN_ADDR_DIFF_VEC_LABEL
#if TARGET_MACHO
#define LOCAL_ALIGNMENT(TYPE, BASIC_ALIGN) \
(TARGET_THUMB ? (MAX (BASIC_ALIGN, 4 * BITS_PER_UNIT)) : BASIC_ALIGN)
#endif
#define ARG_POINTER_CFA_OFFSET(FNDECL) \
((FIRST_PARM_OFFSET (FNDECL)) \
+ (DECL_STRUCT_FUNCTION (FNDECL))->pretend_args_size)
enum arm_builtins
{
ARM_BUILTIN_GETWCX,
ARM_BUILTIN_SETWCX,
ARM_BUILTIN_WZERO,
ARM_BUILTIN_WAVG2BR,
ARM_BUILTIN_WAVG2HR,
ARM_BUILTIN_WAVG2B,
ARM_BUILTIN_WAVG2H,
ARM_BUILTIN_WACCB,
ARM_BUILTIN_WACCH,
ARM_BUILTIN_WACCW,
ARM_BUILTIN_WMACS,
ARM_BUILTIN_WMACSZ,
ARM_BUILTIN_WMACU,
ARM_BUILTIN_WMACUZ,
ARM_BUILTIN_WSADB,
ARM_BUILTIN_WSADBZ,
ARM_BUILTIN_WSADH,
ARM_BUILTIN_WSADHZ,
ARM_BUILTIN_WALIGN,
ARM_BUILTIN_TMIA,
ARM_BUILTIN_TMIAPH,
ARM_BUILTIN_TMIABB,
ARM_BUILTIN_TMIABT,
ARM_BUILTIN_TMIATB,
ARM_BUILTIN_TMIATT,
ARM_BUILTIN_TMOVMSKB,
ARM_BUILTIN_TMOVMSKH,
ARM_BUILTIN_TMOVMSKW,
ARM_BUILTIN_TBCSTB,
ARM_BUILTIN_TBCSTH,
ARM_BUILTIN_TBCSTW,
ARM_BUILTIN_WMADDS,
ARM_BUILTIN_WMADDU,
ARM_BUILTIN_WPACKHSS,
ARM_BUILTIN_WPACKWSS,
ARM_BUILTIN_WPACKDSS,
ARM_BUILTIN_WPACKHUS,
ARM_BUILTIN_WPACKWUS,
ARM_BUILTIN_WPACKDUS,
ARM_BUILTIN_WADDB,
ARM_BUILTIN_WADDH,
ARM_BUILTIN_WADDW,
ARM_BUILTIN_WADDSSB,
ARM_BUILTIN_WADDSSH,
ARM_BUILTIN_WADDSSW,
ARM_BUILTIN_WADDUSB,
ARM_BUILTIN_WADDUSH,
ARM_BUILTIN_WADDUSW,
ARM_BUILTIN_WSUBB,
ARM_BUILTIN_WSUBH,
ARM_BUILTIN_WSUBW,
ARM_BUILTIN_WSUBSSB,
ARM_BUILTIN_WSUBSSH,
ARM_BUILTIN_WSUBSSW,
ARM_BUILTIN_WSUBUSB,
ARM_BUILTIN_WSUBUSH,
ARM_BUILTIN_WSUBUSW,
ARM_BUILTIN_WAND,
ARM_BUILTIN_WANDN,
ARM_BUILTIN_WOR,
ARM_BUILTIN_WXOR,
ARM_BUILTIN_WCMPEQB,
ARM_BUILTIN_WCMPEQH,
ARM_BUILTIN_WCMPEQW,
ARM_BUILTIN_WCMPGTUB,
ARM_BUILTIN_WCMPGTUH,
ARM_BUILTIN_WCMPGTUW,
ARM_BUILTIN_WCMPGTSB,
ARM_BUILTIN_WCMPGTSH,
ARM_BUILTIN_WCMPGTSW,
ARM_BUILTIN_TEXTRMSB,
ARM_BUILTIN_TEXTRMSH,
ARM_BUILTIN_TEXTRMSW,
ARM_BUILTIN_TEXTRMUB,
ARM_BUILTIN_TEXTRMUH,
ARM_BUILTIN_TEXTRMUW,
ARM_BUILTIN_TINSRB,
ARM_BUILTIN_TINSRH,
ARM_BUILTIN_TINSRW,
ARM_BUILTIN_WMAXSW,
ARM_BUILTIN_WMAXSH,
ARM_BUILTIN_WMAXSB,
ARM_BUILTIN_WMAXUW,
ARM_BUILTIN_WMAXUH,
ARM_BUILTIN_WMAXUB,
ARM_BUILTIN_WMINSW,
ARM_BUILTIN_WMINSH,
ARM_BUILTIN_WMINSB,
ARM_BUILTIN_WMINUW,
ARM_BUILTIN_WMINUH,
ARM_BUILTIN_WMINUB,
ARM_BUILTIN_WMULUM,
ARM_BUILTIN_WMULSM,
ARM_BUILTIN_WMULUL,
ARM_BUILTIN_PSADBH,
ARM_BUILTIN_WSHUFH,
ARM_BUILTIN_WSLLH,
ARM_BUILTIN_WSLLW,
ARM_BUILTIN_WSLLD,
ARM_BUILTIN_WSRAH,
ARM_BUILTIN_WSRAW,
ARM_BUILTIN_WSRAD,
ARM_BUILTIN_WSRLH,
ARM_BUILTIN_WSRLW,
ARM_BUILTIN_WSRLD,
ARM_BUILTIN_WRORH,
ARM_BUILTIN_WRORW,
ARM_BUILTIN_WRORD,
ARM_BUILTIN_WSLLHI,
ARM_BUILTIN_WSLLWI,
ARM_BUILTIN_WSLLDI,
ARM_BUILTIN_WSRAHI,
ARM_BUILTIN_WSRAWI,
ARM_BUILTIN_WSRADI,
ARM_BUILTIN_WSRLHI,
ARM_BUILTIN_WSRLWI,
ARM_BUILTIN_WSRLDI,
ARM_BUILTIN_WRORHI,
ARM_BUILTIN_WRORWI,
ARM_BUILTIN_WRORDI,
ARM_BUILTIN_WUNPCKIHB,
ARM_BUILTIN_WUNPCKIHH,
ARM_BUILTIN_WUNPCKIHW,
ARM_BUILTIN_WUNPCKILB,
ARM_BUILTIN_WUNPCKILH,
ARM_BUILTIN_WUNPCKILW,
ARM_BUILTIN_WUNPCKEHSB,
ARM_BUILTIN_WUNPCKEHSH,
ARM_BUILTIN_WUNPCKEHSW,
ARM_BUILTIN_WUNPCKEHUB,
ARM_BUILTIN_WUNPCKEHUH,
ARM_BUILTIN_WUNPCKEHUW,
ARM_BUILTIN_WUNPCKELSB,
ARM_BUILTIN_WUNPCKELSH,
ARM_BUILTIN_WUNPCKELSW,
ARM_BUILTIN_WUNPCKELUB,
ARM_BUILTIN_WUNPCKELUH,
ARM_BUILTIN_WUNPCKELUW,
ARM_BUILTIN_THREAD_POINTER,
ARM_BUILTIN_MAX
};
#endif