#define C4x 1
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
extern int flag_inline_trees; \
if (!TARGET_SMALL) \
builtin_define ("_BIGMODEL"); \
if (!TARGET_MEMPARM) \
builtin_define ("_REGPARM"); \
if (flag_inline_functions) \
builtin_define ("_INLINE"); \
if (TARGET_C3X) \
{ \
builtin_define ("_TMS320C3x"); \
builtin_define ("_C3x"); \
if (TARGET_C30) \
{ \
builtin_define ("_TMS320C30"); \
builtin_define ("_C30"); \
} \
else if (TARGET_C31) \
{ \
builtin_define ("_TMS320C31"); \
builtin_define ("_C31"); \
} \
else if (TARGET_C32) \
{ \
builtin_define ("_TMS320C32"); \
builtin_define ("_C32"); \
} \
else if (TARGET_C33) \
{ \
builtin_define ("_TMS320C33"); \
builtin_define ("_C33"); \
} \
} \
else \
{ \
builtin_define ("_TMS320C4x"); \
builtin_define ("_C4x"); \
if (TARGET_C40) \
{ \
builtin_define ("_TMS320C40"); \
builtin_define ("_C40"); \
} \
else if (TARGET_C44) \
{ \
builtin_define ("_TMS320C44"); \
builtin_define ("_C44"); \
} \
} \
} \
while (0)
#define ASM_SPEC "\
%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
%{!m30:%{!m31:%{!m32:%{!m33:%{!m40:%{!m44:-m40}}}}}}}}}}}} \
%{mcpu=30} \
%{mcpu=31} \
%{mcpu=32} \
%{mcpu=33} \
%{mcpu=40} \
%{mcpu=44} \
%{m30} \
%{m31} \
%{m32} \
%{m33} \
%{m40} \
%{m44} \
%{mmemparm} %{mregparm} %{!mmemparm:%{!mregparm:-mregparm}} \
%{mbig} %{msmall} %{!msmall:%{!mbig:-mbig}}"
#define LINK_SPEC "\
%{m30:--architecture c3x} \
%{m31:--architecture c3x} \
%{m32:--architecture c3x} \
%{m33:--architecture c3x} \
%{mcpu=30:--architecture c3x} \
%{mcpu=31:--architecture c3x} \
%{mcpu=32:--architecture c3x} \
%{mcpu=33:--architecture c3x}"
#define ENDFILE_SPEC ""
#define SMALL_MEMORY_FLAG 0x0000001
#define MPYI_FLAG 0x0000002
#define FAST_FIX_FLAG 0x0000004
#define RPTS_FLAG 0x0000008
#define C3X_FLAG 0x0000010
#define TI_FLAG 0x0000020
#define PARANOID_FLAG 0x0000040
#define MEMPARM_FLAG 0x0000080
#define DEVEL_FLAG 0x0000100
#define RPTB_FLAG 0x0000200
#define BK_FLAG 0x0000400
#define DB_FLAG 0x0000800
#define DEBUG_FLAG 0x0001000
#define HOIST_FLAG 0x0002000
#define LOOP_UNSIGNED_FLAG 0x0004000
#define FORCE_FLAG 0x0008000
#define PRESERVE_FLOAT_FLAG 0x0010000
#define PARALLEL_INSN_FLAG 0x0020000
#define PARALLEL_MPY_FLAG 0x0040000
#define ALIASES_FLAG 0x0080000
#define C30_FLAG 0x0100000
#define C31_FLAG 0x0200000
#define C32_FLAG 0x0400000
#define C33_FLAG 0x0800000
#define C40_FLAG 0x1000000
#define C44_FLAG 0x2000000
#define TARGET_SWITCHES \
{ { "small", SMALL_MEMORY_FLAG, \
N_("Small memory model") }, \
{ "big", -SMALL_MEMORY_FLAG, \
N_("Big memory model") }, \
{ "mpyi", MPYI_FLAG, \
N_("Use MPYI instruction for C3x") }, \
{ "no-mpyi", -MPYI_FLAG, \
N_("Do not use MPYI instruction for C3x") }, \
{ "fast-fix", FAST_FIX_FLAG, \
N_("Use fast but approximate float to integer conversion") }, \
{ "no-fast-fix", -FAST_FIX_FLAG, \
N_("Use slow but accurate float to integer conversion") }, \
{ "rpts", RPTS_FLAG, \
N_("Enable use of RTPS instruction") }, \
{ "no-rpts", -RPTS_FLAG, \
N_("Disable use of RTPS instruction") }, \
{ "rptb", RPTB_FLAG, \
N_("Enable use of RTPB instruction") }, \
{ "no-rptb", -RPTB_FLAG, \
N_("Disable use of RTPB instruction") }, \
{ "30", C30_FLAG, \
N_("Generate code for C30 CPU")}, \
{ "31", C31_FLAG, \
N_("Generate code for C31 CPU")}, \
{ "32", C32_FLAG, \
N_("Generate code for C32 CPU")}, \
{ "33", C33_FLAG, \
N_("Generate code for C33 CPU")}, \
{ "40", C40_FLAG, \
N_("Generate code for C40 CPU")}, \
{ "44", C44_FLAG, \
N_("Generate code for C44 CPU")}, \
{ "ti", TI_FLAG, \
N_("Emit code compatible with TI tools")}, \
{ "no-ti", -TI_FLAG, \
N_("Emit code to use GAS extensions")}, \
{ "paranoid", PARANOID_FLAG, \
N_("Save DP across ISR in small memory model") }, \
{ "no-paranoid", -PARANOID_FLAG, \
N_("Don't save DP across ISR in small memory model") }, \
{ "isr-dp-reload", PARANOID_FLAG, \
N_("Save DP across ISR in small memory model") }, \
{ "no-isr-dp-reload", -PARANOID_FLAG, \
N_("Don't save DP across ISR in small memory model") }, \
{ "memparm", MEMPARM_FLAG, \
N_("Pass arguments on the stack") }, \
{ "regparm", -MEMPARM_FLAG, \
N_("Pass arguments in registers") }, \
{ "devel", DEVEL_FLAG, \
N_("Enable new features under development") }, \
{ "no-devel", -DEVEL_FLAG, \
N_("Disable new features under development") }, \
{ "bk", BK_FLAG, \
N_("Use the BK register as a general purpose register") }, \
{ "no-bk", -BK_FLAG, \
N_("Do not allocate BK register") }, \
{ "db", DB_FLAG, \
N_("Enable use of DB instruction") }, \
{ "no-db", -DB_FLAG, \
N_("Disable use of DB instruction") }, \
{ "debug", DEBUG_FLAG, \
N_("Enable debugging") }, \
{ "no-debug", -DEBUG_FLAG, \
N_("Disable debugging") }, \
{ "hoist", HOIST_FLAG, \
N_("Force constants into registers to improve hoisting") }, \
{ "no-hoist", -HOIST_FLAG, \
N_("Don't force constants into registers") }, \
{ "force", FORCE_FLAG, \
N_("Force RTL generation to emit valid 3 operand insns") }, \
{ "no-force", -FORCE_FLAG, \
N_("Allow RTL generation to emit invalid 3 operand insns") }, \
{ "loop-unsigned", LOOP_UNSIGNED_FLAG, \
N_("Allow unsigned iteration counts for RPTB/DB") }, \
{ "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
N_("Disallow unsigned iteration counts for RPTB/DB") }, \
{ "preserve-float", PRESERVE_FLOAT_FLAG, \
N_("Preserve all 40 bits of FP reg across call") }, \
{ "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
N_("Only preserve 32 bits of FP reg across call") }, \
{ "parallel-insns", PARALLEL_INSN_FLAG, \
N_("Enable parallel instructions") }, \
{ "no-parallel-insns", -PARALLEL_INSN_FLAG, \
N_("Disable parallel instructions") }, \
{ "parallel-mpy", PARALLEL_MPY_FLAG, \
N_("Enable MPY||ADD and MPY||SUB instructions") }, \
{ "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
N_("Disable MPY||ADD and MPY||SUB instructions") }, \
{ "aliases", ALIASES_FLAG, \
N_("Assume that pointers may be aliased") }, \
{ "no-aliases", -ALIASES_FLAG, \
N_("Assume that pointers not aliased") }, \
{ "", TARGET_DEFAULT, ""} }
#define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_INSN_FLAG \
| PARALLEL_MPY_FLAG | RPTB_FLAG
extern int target_flags;
#define TARGET_INLINE (! optimize_size)
#define TARGET_SMALL_REG_CLASS 0
#define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
#define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
#define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
#define TARGET_RPTS (target_flags & RPTS_FLAG)
#define TARGET_TI (target_flags & TI_FLAG)
#define TARGET_PARANOID (target_flags & PARANOID_FLAG)
#define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
#define TARGET_DEVEL (target_flags & DEVEL_FLAG)
#define TARGET_RPTB (target_flags & RPTB_FLAG \
&& optimize >= 2)
#define TARGET_BK (target_flags & BK_FLAG)
#define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
#define TARGET_DEBUG (target_flags & DEBUG_FLAG)
#define TARGET_HOIST (target_flags & HOIST_FLAG)
#define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
#define TARGET_FORCE (target_flags & FORCE_FLAG)
#define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
#define TARGET_PARALLEL ((target_flags & PARALLEL_INSN_FLAG) \
&& optimize >= 2)
#define TARGET_PARALLEL_MPY (TARGET_PARALLEL \
&& (target_flags & PARALLEL_MPY_FLAG))
#define TARGET_ALIASES (target_flags & ALIASES_FLAG)
#define TARGET_C3X (target_flags & C3X_FLAG)
#define TARGET_C30 (target_flags & C30_FLAG)
#define TARGET_C31 (target_flags & C31_FLAG)
#define TARGET_C32 (target_flags & C32_FLAG)
#define TARGET_C33 (target_flags & C33_FLAG)
#define TARGET_C40 (target_flags & C40_FLAG)
#define TARGET_C44 (target_flags & C44_FLAG)
#define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
#define TARGET_EXPOSE_LDP 0
#define TARGET_LOAD_DIRECT_MEMS 0
#define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
#define TARGET_OPTIONS \
{ {"rpts=", &c4x_rpts_cycles_string, \
N_("Specify maximum number of iterations for RPTS"), 0}, \
{"cpu=", &c4x_cpu_version_string, \
N_("Select CPU to generate code for"), 0} }
#define OVERRIDE_OPTIONS c4x_override_options ()
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)
#define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN 0
#define WORDS_BIG_ENDIAN 0
#define FLOAT_WORDS_BIG_ENDIAN 1
#define BITS_PER_UNIT 32
#define UNITS_PER_WORD 1
#define PARM_BOUNDARY 32
#define STACK_BOUNDARY 32
#define FUNCTION_BOUNDARY 32
#define BIGGEST_ALIGNMENT 32
#define EMPTY_FIELD_BOUNDARY 32
#define STRICT_ALIGNMENT 0
#define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
#define MAX_FIXED_MODE_SIZE 64
#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
(TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE && (MODE) == VOIDmode)
#define BITS_PER_HIGH 16
#define BITS_PER_LO_SUM 16
#define R0_REGNO 0
#define R1_REGNO 1
#define R2_REGNO 2
#define R3_REGNO 3
#define R4_REGNO 4
#define R5_REGNO 5
#define R6_REGNO 6
#define R7_REGNO 7
#define AR0_REGNO 8
#define AR1_REGNO 9
#define AR2_REGNO 10
#define AR3_REGNO 11
#define AR4_REGNO 12
#define AR5_REGNO 13
#define AR6_REGNO 14
#define AR7_REGNO 15
#define DP_REGNO 16
#define IR0_REGNO 17
#define IR1_REGNO 18
#define BK_REGNO 19
#define SP_REGNO 20
#define ST_REGNO 21
#define DIE_REGNO 22
#define IE_REGNO 22
#define IIE_REGNO 23
#define IF_REGNO 23
#define IIF_REGNO 24
#define IOF_REGNO 24
#define RS_REGNO 25
#define RE_REGNO 26
#define RC_REGNO 27
#define R8_REGNO 28
#define R9_REGNO 29
#define R10_REGNO 30
#define R11_REGNO 31
#define FIRST_PSEUDO_REGISTER 32
#define IS_R0R1_REGNO(r) \
((unsigned int)((r) - R0_REGNO) <= (R1_REGNO - R0_REGNO))
#define IS_R2R3_REGNO(r) \
((unsigned int)((r) - R2_REGNO) <= (R3_REGNO - R2_REGNO))
#define IS_EXT_LOW_REGNO(r) \
((unsigned int)((r) - R0_REGNO) <= (R7_REGNO - R0_REGNO))
#define IS_EXT_HIGH_REGNO(r) \
(! TARGET_C3X \
&& ((unsigned int) ((r) - R8_REGNO) <= (R11_REGNO - R8_REGNO)))
#define IS_AUX_REGNO(r) \
((unsigned int)((r) - AR0_REGNO) <= (AR7_REGNO - AR0_REGNO))
#define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
#define IS_DP_REGNO(r) ((r) == DP_REGNO)
#define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
#define IS_SP_REGNO(r) ((r) == SP_REGNO)
#define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
#define IS_ST_REGNO(r) ((r) == ST_REGNO)
#define IS_RC_REGNO(r) ((r) == RC_REGNO)
#define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
#define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
#define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
#define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
|| IS_REPEAT_REGNO(r) \
|| IS_SP_REGNO(r) \
|| IS_BK_REGNO(r))
#define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
#define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
#define IS_INT_CALL_SAVED_REGNO(r) (((r) == R4_REGNO) || ((r) == R5_REGNO) \
|| ((r) == R8_REGNO))
#define IS_FLOAT_CALL_SAVED_REGNO(r) (((r) == R6_REGNO) || ((r) == R7_REGNO))
#define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
#define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
|| IS_PSEUDO_REGNO(r))
#define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
#define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
#define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
#define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
#define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
#define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
#define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
#define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
#define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
#define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
#define FIXED_REGISTERS \
{ \
\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
}
#define CALL_USED_REGISTERS \
{ \
\
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
}
#define CONDITIONAL_REGISTER_USAGE \
{ \
if (! TARGET_BK) \
{ \
fixed_regs[BK_REGNO] = 1; \
call_used_regs[BK_REGNO] = 1; \
c4x_regclass_map[BK_REGNO] = NO_REGS; \
} \
if (TARGET_C3X) \
{ \
int i; \
\
reg_names[DIE_REGNO] = "ie"; \
reg_names[IF_REGNO] = "if"; \
reg_names[IOF_REGNO] = "iof"; \
\
for (i = R8_REGNO; i <= R11_REGNO; i++) \
{ \
fixed_regs[i] = call_used_regs[i] = 1; \
c4x_regclass_map[i] = NO_REGS; \
} \
} \
if (TARGET_PRESERVE_FLOAT) \
{ \
c4x_caller_save_map[R6_REGNO] = HFmode; \
c4x_caller_save_map[R7_REGNO] = HFmode; \
} \
}
#define REG_ALLOC_ORDER \
{R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
R9_REGNO, R10_REGNO, R11_REGNO, \
RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
IR0_REGNO, IR1_REGNO, \
SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
c4x_hard_regno_rename_ok((REGNO1), (REGNO2))
#define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS)
#define HARD_REGNO_NREGS(REGNO, MODE) \
(((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : \
((MODE) == HFmode) ? 1 : \
((MODE) == HCmode) ? 2 : \
((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
((IS_FLOAT_CALL_SAVED_REGNO (REGNO) && ! ((MODE) == QFmode)) \
|| (IS_INT_CALL_SAVED_REGNO (REGNO) \
&& ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) (c4x_caller_save_map[REGNO])
#define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
#define MODES_TIEABLE_P(MODE1, MODE2) 0
enum reg_class
{
NO_REGS,
R0R1_REGS,
R2R3_REGS,
EXT_LOW_REGS,
EXT_REGS,
ADDR_REGS,
INDEX_REGS,
BK_REG,
SP_REG,
RC_REG,
COUNTER_REGS,
INT_REGS,
GENERAL_REGS,
DP_REG,
ST_REG,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"R0R1_REGS", \
"R2R3_REGS", \
"EXT_LOW_REGS", \
"EXT_REGS", \
"ADDR_REGS", \
"INDEX_REGS", \
"BK_REG", \
"SP_REG", \
"RC_REG", \
"COUNTER_REGS", \
"INT_REGS", \
"GENERAL_REGS", \
"DP_REG", \
"ST_REG", \
"ALL_REGS" \
}
#define REG_CLASS_CONTENTS \
{ \
{0x00000000}, \
{0x00000003}, \
{0x0000000c}, \
{0x000000ff}, \
{0xf00000ff}, \
{0x0000ff00}, \
{0x00060000}, \
{0x00080000}, \
{0x00100000}, \
{0x08000000}, \
{0x0800ff00}, \
{0x0e1eff00}, \
{0xfe1effff}, \
{0x00010000}, \
{0x00200000}, \
{0xffffffff}, \
}
#define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
#define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
#define BASE_REG_CLASS ADDR_REGS
#define INDEX_REG_CLASS INDEX_REGS
#define REG_CLASS_FROM_LETTER(CC) \
( ((CC) == 'a') ? ADDR_REGS \
: ((CC) == 'b') ? SP_REG \
: ((CC) == 'c') ? INT_REGS \
: ((CC) == 'd') ? EXT_REGS \
: ((CC) == 'f') ? EXT_REGS \
: ((CC) == 'h') ? EXT_REGS \
: ((CC) == 'k') ? BK_REG \
: ((CC) == 'q') ? EXT_LOW_REGS \
: ((CC) == 't') ? R0R1_REGS \
: ((CC) == 'u') ? R2R3_REGS \
: ((CC) == 'v') ? RC_REG \
: ((CC) == 'x') ? INDEX_REGS \
: ((CC) == 'y') ? ST_REG \
: ((CC) == 'z') ? DP_REG \
: NO_REGS )
#define REGNO_OK_FOR_BASE_P(REGNO) \
(IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
#define REGNO_OK_FOR_INDEX_P(REGNO) \
(IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
(GET_CODE (X) == PLUS \
&& GET_MODE (X) == Pmode \
&& GET_CODE (XEXP ((X), 0)) == REG \
&& GET_MODE (XEXP ((X), 0)) == Pmode \
&& REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM \
&& GET_CODE (XEXP ((X), 1)) == CONST_INT \
? ADDR_REGS : (CLASS))
#define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0
#define CLASS_MAX_NREGS(CLASS, MODE) \
(((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
#define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16))
#define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0))
#define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128))
#define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0))
#define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768))
#define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0))
#define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL))
#define IS_HIGH_CONST(VAL) \
(! TARGET_C3X && (((VAL) & 0xffff) == 0))
#define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1))
#define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255))
#define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
&& IS_DISP1_CONST (VAL + 1))
#define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
&& IS_DISP8_CONST (VAL + 1))
#define CONST_OK_FOR_LETTER_P(VAL, C) \
( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
: ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
: ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
: ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
: ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
: ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
: ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
: 0 )
#define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \
: ((C) == 'H') ? (c4x_H_constant (OP)) \
: 0 )
#define EXTRA_CONSTRAINT(OP, C) \
( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
: ((C) == 'R') ? (c4x_R_constraint (OP)) \
: ((C) == 'S') ? (c4x_S_constraint (OP)) \
: ((C) == 'T') ? (c4x_T_constraint (OP)) \
: ((C) == 'U') ? (c4x_U_constraint (OP)) \
: 0 )
#define SMALL_CONST(VAL, insn) \
( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
? IS_INT16_CONST (VAL) \
: ( (get_attr_data (insn) == DATA_NOT_UINT16) \
? IS_NOT_UINT16_CONST (VAL) \
: ( (get_attr_data (insn) == DATA_HIGH_16) \
? IS_HIGH_CONST (VAL) \
: IS_UINT16_CONST (VAL) \
) \
) \
)
#define C4X_ARG0 -2
#define C4X_LOC0 1
#define STARTING_FRAME_OFFSET C4X_LOC0
#define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
#define ARGS_GROW_DOWNWARD
#define STACK_POINTER_OFFSET 1
#define STACK_POINTER_REGNUM SP_REGNO
#define FRAME_POINTER_REGNUM AR3_REGNO
#define ARG_POINTER_REGNUM AR3_REGNO
#define STATIC_CHAIN_REGNUM AR0_REGNO
#define FRAME_POINTER_REQUIRED 0
#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
{ \
int regno; \
int offset = 0; \
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
if (regs_ever_live[regno] && ! call_used_regs[regno]) \
offset += TARGET_PRESERVE_FLOAT \
&& IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
(DEPTH) = -(offset + get_frame_size ()); \
}
#define ELIMINABLE_REGS \
{{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
#define CAN_ELIMINATE(FROM, TO) \
(! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
|| ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
{ \
int regno; \
int offset = 0; \
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
if (regs_ever_live[regno] && ! call_used_regs[regno]) \
offset += TARGET_PRESERVE_FLOAT \
&& IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
(OFFSET) = -(offset + get_frame_size ()); \
}
#define PUSH_ARGS 1
#define PUSH_ROUNDING(BYTES) (BYTES)
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
typedef struct c4x_args
{
int floats;
int ints;
int maxfloats;
int maxints;
int init;
int var;
int prototype;
int args;
}
CUMULATIVE_ARGS;
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
(c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
(c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
(c4x_function_arg(&CUM, MODE, TYPE, NAMED))
#define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
#define FUNCTION_ARG_REGNO_P(REGNO) \
( ( ((REGNO) == AR2_REGNO) \
|| ((REGNO) == R2_REGNO) \
|| ((REGNO) == R3_REGNO) \
|| ((REGNO) == RC_REGNO) \
|| ((REGNO) == RS_REGNO) \
|| ((REGNO) == RE_REGNO)) \
? 1 \
: 0)
#define FUNCTION_VALUE(VALTYPE, FUNC) \
gen_rtx_REG (TYPE_MODE(VALTYPE), R0_REGNO)
#define LIBCALL_VALUE(MODE) \
gen_rtx_REG (MODE, R0_REGNO)
#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
#define DEFAULT_PCC_STRUCT_RETURN 0
#define FUNCTION_PROFILER(FILE, LABELNO) \
if (! TARGET_C3X) \
{ \
fprintf (FILE, "\tpush\tar2\n"); \
fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
fprintf (FILE, "\tcall\tmcount\n"); \
fprintf (FILE, "\tpop\tar2\n"); \
} \
else \
{ \
fprintf (FILE, "\tpush\tar2\n"); \
fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
fprintf (FILE, "\tlsh\t16,ar2\n"); \
fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
fprintf (FILE, "\tcall\tmcount\n"); \
fprintf (FILE, "\tpop\tar2\n"); \
}
#define SELECT_CC_MODE(OP,X,Y) \
((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
|| GET_CODE (X) == NEG || GET_CODE (X) == MULT \
|| GET_MODE (X) == ABS \
|| GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
|| GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
|| GET_MODE (Y) == ABS) \
? CC_NOOVmode : CCmode)
#define HAVE_POST_INCREMENT 1
#define HAVE_PRE_INCREMENT 1
#define HAVE_POST_DECREMENT 1
#define HAVE_PRE_DECREMENT 1
#define HAVE_PRE_MODIFY_REG 1
#define HAVE_POST_MODIFY_REG 1
#define HAVE_PRE_MODIFY_DISP 1
#define HAVE_POST_MODIFY_DISP 1
#define PACK_INSNS 2
#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
#define MAX_REGS_PER_ADDRESS 2
#ifndef REG_OK_STRICT
#define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
#define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ \
if (c4x_legitimate_address_p (MODE, X, 0)) \
goto ADDR; \
}
#else
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ \
if (c4x_legitimate_address_p (MODE, X, 1)) \
goto ADDR; \
}
#endif
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
{ \
rtx new; \
\
new = c4x_legitimize_address (X, MODE); \
if (new != NULL_RTX) \
{ \
(X) = new; \
goto WIN; \
} \
}
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
{ \
if (MODE != HImode \
&& MODE != HFmode \
&& GET_MODE (X) != HImode \
&& GET_MODE (X) != HFmode \
&& (GET_CODE (X) == CONST \
|| GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == LABEL_REF)) \
{ \
if (! TARGET_SMALL) \
{ \
int i; \
(X) = gen_rtx_LO_SUM (GET_MODE (X), \
gen_rtx_HIGH (GET_MODE (X), X), X); \
i = push_reload (XEXP (X, 0), NULL_RTX, \
&XEXP (X, 0), NULL, \
DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
OPNUM, TYPE); \
\
rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
rld[i].nocombine = 1; \
} \
else \
{ \
\
(X) = gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, DP_REGNO), (X)); \
} \
goto WIN; \
} \
else if (MODE != HImode \
&& MODE != HFmode \
&& GET_MODE (X) != HImode \
&& GET_MODE (X) != HFmode \
&& GET_CODE (X) == LO_SUM \
&& GET_CODE (XEXP (X,0)) == HIGH \
&& (GET_CODE (XEXP (XEXP (X,0),0)) == CONST \
|| GET_CODE (XEXP (XEXP (X,0),0)) == SYMBOL_REF \
|| GET_CODE (XEXP (XEXP (X,0),0)) == LABEL_REF)) \
{ \
if (! TARGET_SMALL) \
{ \
int i = push_reload (XEXP (X, 0), NULL_RTX, \
&XEXP (X, 0), NULL, \
DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
OPNUM, TYPE); \
\
rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
rld[i].nocombine = 1; \
} \
goto WIN; \
} \
}
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
if (GET_CODE (ADDR) == PRE_DEC \
|| GET_CODE (ADDR) == POST_DEC \
|| GET_CODE (ADDR) == PRE_INC \
|| GET_CODE (ADDR) == POST_INC \
|| GET_CODE (ADDR) == POST_MODIFY \
|| GET_CODE (ADDR) == PRE_MODIFY) \
goto LABEL
#define LEGITIMATE_CONSTANT_P(X) \
((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
|| (GET_CODE (X) == CONST_INT) \
|| (GET_CODE (X) == SYMBOL_REF) \
|| (GET_CODE (X) == LABEL_REF) \
|| (GET_CODE (X) == CONST) \
|| (GET_CODE (X) == HIGH && ! TARGET_C3X) \
|| (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
#define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
if (REG_P (OP1) && ! REG_P (OP0)) \
{ \
rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
CODE = swap_condition (CODE); \
}
#define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
#define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
#define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
#define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
|| INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
#define REGISTER_MOVE_COST(MODE, FROM, TO) 2
#define MEMORY_MOVE_COST(M,C,I) 4
#define BRANCH_COST 8
#define WORD_REGISTER_OPERATIONS
#define TEXT_SECTION_ASM_OP "\t.text"
#define DATA_SECTION_ASM_OP "\t.data"
#define READONLY_DATA_SECTION_ASM_OP "\t.sect\t\".const\""
#if 0
#define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
#endif
#define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
#undef EXTRA_SECTIONS
#define EXTRA_SECTIONS in_init, in_fini
#undef EXTRA_SECTION_FUNCTIONS
#define EXTRA_SECTION_FUNCTIONS \
INIT_SECTION_FUNCTION \
FINI_SECTION_FUNCTION
#define INIT_SECTION_FUNCTION \
extern void init_section (void); \
void \
init_section (void) \
{ \
if (in_section != in_init) \
{ \
fprintf (asm_out_file, ";\t.init\n"); \
in_section = in_init; \
} \
}
#define FINI_SECTION_FUNCTION \
void \
fini_section () \
{ \
if (in_section != in_fini) \
{ \
fprintf (asm_out_file, "%s\n", FINI_SECTION_ASM_OP); \
in_section = in_fini; \
} \
}
#define TARGET_ASM_NAMED_SECTION c4x_asm_named_section
#define ASM_COMMENT_START ";"
#define ASM_APP_ON ""
#define ASM_APP_OFF ""
#define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
#define NO_DOT_IN_LABEL
#define GLOBAL_ASM_OP "\t.global\t"
#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
c4x_external_ref (NAME)
#define USER_LABEL_PREFIX "_"
#define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
sprintf (BUFFER, "*%s%lu", PREFIX, (unsigned long)(NUM))
#define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
do { \
assemble_name (STREAM, NAME); \
fprintf (STREAM, "\t.set\t%s\n", VALUE); \
} while (0)
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
fprintf (FILE, "\t.long\tL%d\n", VALUE);
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
#undef SIZE_TYPE
#define SIZE_TYPE "unsigned int"
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "int"
#undef WCHAR_TYPE
#define WCHAR_TYPE "long int"
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE 32
#define INT_TYPE_SIZE 32
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 32
#define LONG_DOUBLE_TYPE_SIZE 64
#define ASM_OUTPUT_IDENT(FILE, NAME) \
fprintf (FILE, "\t.ident \"%s\"\n", NAME);
#undef ASM_OUTPUT_LOCAL
#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
( fputs ("\t.bss\t", FILE), \
assemble_name (FILE, (NAME)), \
fprintf (FILE, ",%u\n", (int)(ROUNDED)))
#undef ASM_OUTPUT_COMMON
#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
( fputs ("\t.globl\t", FILE), \
assemble_name (FILE, (NAME)), \
fputs ("\n\t.bss\t", FILE), \
assemble_name (FILE, (NAME)), \
fprintf (FILE, ",%u\n", (int)(ROUNDED)))
#undef ASM_OUTPUT_BSS
#define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
( fputs ("\t.globl\t", FILE), \
assemble_name (FILE, (NAME)), \
fputs ("\n\t.bss\t", FILE), \
assemble_name (FILE, (NAME)), \
fprintf (FILE, ",%u\n", (int)(SIZE)))
#define OBJECT_FORMAT_COFF
#define REAL_NM_FILE_NAME "c4x-nm"
#define REGISTER_NAMES \
{ \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
"dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
"iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
}
#define FLOAT_REGISTER_NAMES \
{ \
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
"ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
"dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
"iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
}
#define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
#define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
#define REGISTER_TARGET_PRAGMAS() do { \
c_register_pragma (0, "CODE_SECTION", c4x_pr_CODE_SECTION); \
c_register_pragma (0, "DATA_SECTION", c4x_pr_DATA_SECTION); \
c_register_pragma (0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \
c_register_pragma (0, "FUNC_EXT_CALLED", c4x_pr_ignored); \
c_register_pragma (0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \
c_register_pragma (0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \
c_register_pragma (0, "FUNC_NEVER_RETURNS", c4x_pr_FUNC_NEVER_RETURNS); \
c_register_pragma (0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \
c_register_pragma (0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \
c_register_pragma (0, "INTERRUPT", c4x_pr_INTERRUPT); \
} while (0)
#define ASM_OUTPUT_SKIP(FILE, SIZE) \
{ int c = SIZE; \
for (; c > 0; --c) \
fprintf (FILE,"\t.word\t0\n"); \
}
#define ASM_NO_SKIP_IN_TEXT 1
#define ASM_OUTPUT_ALIGN(FILE, LOG) \
if ((LOG) != 0) \
fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
#define SDB_DELIM "\n"
#define SDB_DEBUGGING_INFO 1
#define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM)
#define PUT_SDB_DEF(A) \
do { fprintf (asm_out_file, "\t.sdef\t"); \
ASM_OUTPUT_LABELREF (asm_out_file, A); \
fprintf (asm_out_file, SDB_DELIM); } while (0)
#define PUT_SDB_PLAIN_DEF(A) \
fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
#define PUT_SDB_BLOCK_START(LINE) \
fprintf (asm_out_file, \
"\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
#define PUT_SDB_BLOCK_END(LINE) \
fprintf (asm_out_file, \
"\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
#define PUT_SDB_FUNCTION_START(LINE) \
fprintf (asm_out_file, \
"\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
#define PUT_SDB_FUNCTION_END(LINE) \
fprintf (asm_out_file, \
"\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
SDB_DELIM, SDB_DELIM, SDB_DELIM, \
(LINE), SDB_DELIM)
#define PUT_SDB_EPILOGUE_END(NAME) \
do { fprintf (asm_out_file, "\t.sdef\t"); \
ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
fprintf (asm_out_file, \
"%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
#define DEFAULT_SIGNED_CHAR 1
#define FUNCTION_MODE QImode
#define SLOW_BYTE_ACCESS 0
#define Pmode QImode
#define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
#define TRAMPOLINE_TEMPLATE(FILE) \
{ \
if (TARGET_C3X) \
{ \
fprintf (FILE, "\tldiu\t0,ar1\n"); \
fprintf (FILE, "\tlsh\t16,ar1\n"); \
fprintf (FILE, "\tor\t0,ar1\n"); \
fprintf (FILE, "\tldiu\t0,ar0\n"); \
fprintf (FILE, "\tbud\tar1\n"); \
fprintf (FILE, "\tlsh\t16,ar0\n"); \
fprintf (FILE, "\tor\t0,ar0\n"); \
fprintf (FILE, "\tor\t1000h,st\n"); \
} \
else \
{ \
fprintf (FILE, "\tlaj\t$+4\n"); \
fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
fprintf (FILE, "\tbud\tar1\n"); \
fprintf (FILE, "\tnop\n"); \
fprintf (FILE, "\tnop\n"); \
fprintf (FILE, "\tor\t1000h,st\n"); \
fprintf (FILE, "\t.word\t0\n"); \
fprintf (FILE, "\t.word\t0\n"); \
} \
}
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
if (TARGET_C3X) \
{ \
rtx tmp1, tmp2; \
tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
size_int (16), 0, 1); \
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
GEN_INT (0x5069), size_int (16), 0, 1); \
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
emit_move_insn (gen_rtx_MEM (QImode, \
plus_constant (TRAMP, 0)), tmp1); \
tmp1 = expand_and (QImode, FNADDR, GEN_INT (0xffff), 0); \
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
GEN_INT (0x1069), size_int (16), 0, 1); \
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
emit_move_insn (gen_rtx_MEM (QImode, \
plus_constant (TRAMP, 2)), tmp1); \
tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
size_int (16), 0, 1); \
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
GEN_INT (0x5068), size_int (16), 0, 1); \
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
emit_move_insn (gen_rtx_MEM (QImode, \
plus_constant (TRAMP, 3)), tmp1); \
tmp1 = expand_and (QImode, CXT, GEN_INT (0xffff), 0); \
tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
GEN_INT (0x1068), size_int (16), 0, 1); \
emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
emit_move_insn (gen_rtx_MEM (QImode, \
plus_constant (TRAMP, 6)), tmp1); \
} \
else \
{ \
emit_move_insn (gen_rtx_MEM (QImode, \
plus_constant (TRAMP, 8)), FNADDR); \
emit_move_insn (gen_rtx_MEM (QImode, \
plus_constant (TRAMP, 9)), CXT); \
} \
}
#define CASE_VECTOR_MODE Pmode
#define MOVE_MAX 1
#define MOVE_RATIO 3
#define BSS_SECTION_ASM_OP "\t.bss"
#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define DBR_OUTPUT_SEQEND(FILE) \
if (final_sequence != NULL_RTX) \
{ \
int count; \
rtx insn = XVECEXP (final_sequence, 0, 0); \
int laj = GET_CODE (insn) == CALL_INSN \
|| (GET_CODE (insn) == INSN \
&& GET_CODE (PATTERN (insn)) == TRAP_IF);\
\
count = dbr_sequence_length(); \
while (count < (laj ? 2 : 3)) \
{ \
fputs("\tnop\n", FILE); \
count++; \
} \
if (laj) \
fputs("\tpush\tr11\n", FILE); \
}
#define NO_FUNCTION_CSE
#define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
#define PREDICATE_CODES \
{"fp_zero_operand", {CONST_DOUBLE}}, \
{"const_operand", {CONST_INT, CONST_DOUBLE}}, \
{"stik_const_operand", {CONST_INT}}, \
{"not_const_operand", {CONST_INT}}, \
{"reg_operand", {REG, SUBREG}}, \
{"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
{"r0r1_reg_operand", {REG, SUBREG}}, \
{"r2r3_reg_operand", {REG, SUBREG}}, \
{"ext_low_reg_operand", {REG, SUBREG}}, \
{"ext_reg_operand", {REG, SUBREG}}, \
{"std_reg_operand", {REG, SUBREG}}, \
{"std_or_reg_operand", {REG, SUBREG}}, \
{"addr_reg_operand", {REG, SUBREG}}, \
{"index_reg_operand", {REG, SUBREG}}, \
{"dp_reg_operand", {REG}}, \
{"sp_reg_operand", {REG}}, \
{"st_reg_operand", {REG}}, \
{"rc_reg_operand", {REG}}, \
{"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \
{"dst_operand", {SUBREG, REG, MEM}}, \
{"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
{"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
{"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
{"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
{"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
{"nonimmediate_lsrc_operand", {SUBREG, REG, MEM}}, \
{"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
{"par_ind_operand", {MEM}}, \
{"parallel_operand", {SUBREG, REG, MEM}}, \
{"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
{"mem_operand", {MEM}},
enum c4x_builtins
{
C4X_BUILTIN_FIX,
C4X_BUILTIN_FIX_ANSI,
C4X_BUILTIN_MPYI,
C4X_BUILTIN_TOIEEE,
C4X_BUILTIN_FRIEEE,
C4X_BUILTIN_RCPF
};
#undef HAVE_GAS_HIDDEN