struct processor_costs {
const int add;
const int lea;
const int shift_var;
const int shift_const;
const int mult_init[5];
const int mult_bit;
const int divide[5];
int movsx;
int movzx;
const int large_insn;
const int move_ratio;
const int movzbl_load;
const int int_load[3];
const int int_store[3];
const int fp_move;
const int fp_load[3];
const int fp_store[3];
const int mmx_move;
const int mmx_load[2];
const int mmx_store[2];
const int sse_move;
const int sse_load[3];
const int sse_store[3];
const int mmxsse_to_integer;
const int prefetch_block;
const int simultaneous_prefetches;
const int branch_cost;
const int fadd;
const int fmul;
const int fdiv;
const int fabs;
const int fchs;
const int fsqrt;
};
extern const struct processor_costs *ix86_cost;
extern int target_flags;
#ifndef TARGET_CPU_DEFAULT
#ifdef TARGET_64BIT_DEFAULT
#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_k8
#else
#define TARGET_CPU_DEFAULT 0
#endif
#endif
#ifndef TARGET_FPMATH_DEFAULT
#define TARGET_FPMATH_DEFAULT \
(TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
#endif
#define MASK_80387 0x00000001
#define MASK_RTD 0x00000002
#define MASK_ALIGN_DOUBLE 0x00000004
#define MASK_SVR3_SHLIB 0x00000008
#define MASK_IEEE_FP 0x00000010
#define MASK_FLOAT_RETURNS 0x00000020
#define MASK_NO_FANCY_MATH_387 0x00000040
#define MASK_OMIT_LEAF_FRAME_POINTER 0x080
#define MASK_STACK_PROBE 0x00000100
#define MASK_NO_ALIGN_STROPS 0x00000200
#define MASK_INLINE_ALL_STROPS 0x00000400
#define MASK_NO_PUSH_ARGS 0x00000800
#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000
#define MASK_MMX 0x00002000
#define MASK_SSE 0x00004000
#define MASK_SSE2 0x00008000
#define MASK_SSE3 0x00010000
#define MASK_3DNOW 0x00020000
#define MASK_3DNOW_A 0x00040000
#define MASK_128BIT_LONG_DOUBLE 0x00080000
#define MASK_64BIT 0x00100000
#define MASK_MS_BITFIELD_LAYOUT 0x00200000
#define MASK_TLS_DIRECT_SEG_REFS 0x00400000
#define MASK_SSEREGPARM 0x01000000
#define TARGET_SSEREGPARM (target_flags & MASK_SSEREGPARM)
#define MACHOPIC_NL_SYMBOL_PTR_SECTION ".section __IMPORT,__pointers,non_lazy_symbol_pointers"
#define MASK_NO_RED_ZONE 0x04000000
#define TARGET_80387 (target_flags & MASK_80387)
#define TARGET_RTD (target_flags & MASK_RTD)
#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
#define TARGET_ACCUMULATE_OUTGOING_ARGS \
(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
#define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
#define TARGET_USE_FANCY_MATH_387 (! TARGET_NO_FANCY_MATH_387)
#define TARGET_OMIT_LEAF_FRAME_POINTER \
(target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
#define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
#define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
#ifdef IN_LIBGCC2
#ifdef __x86_64__
#define TARGET_64BIT 1
#else
#define TARGET_64BIT 0
#endif
#else
#ifdef TARGET_BI_ARCH
#define TARGET_64BIT (target_flags & MASK_64BIT)
#else
#if TARGET_64BIT_DEFAULT
#define TARGET_64BIT 1
#else
#define TARGET_64BIT 0
#endif
#endif
#endif
#define HAS_LONG_COND_BRANCH 1
#define HAS_LONG_UNCOND_BRANCH 1
#define TARGET_TLS_DIRECT_SEG_REFS (target_flags & MASK_TLS_DIRECT_SEG_REFS)
#define TARGET_386 (ix86_tune == PROCESSOR_I386)
#define TARGET_486 (ix86_tune == PROCESSOR_I486)
#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
#define TARGET_K6 (ix86_tune == PROCESSOR_K6)
#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
#define TUNEMASK (1 << ix86_tune)
extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
extern const int x86_use_bit_test, x86_cmove, x86_fisttp, x86_deep_branch;
extern const int x86_branch_hints, x86_unroll_strlen;
extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
extern const int x86_use_cltd, x86_read_modify_write;
extern const int x86_read_modify, x86_split_long_moves;
extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
extern const int x86_epilogue_using_move, x86_decompose_lea;
extern const int x86_arch_always_fancy_math_387, x86_shift1;
extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
extern const int x86_use_ffreep;
extern const int x86_inter_unit_moves, x86_schedule;
extern const int x86_use_bt;
extern int x86_prefetch_sse;
#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
#define TARGET_FISTTP (((x86_fisttp & (1 << ix86_arch)) || TARGET_SSE3) \
&& TARGET_80387)
#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
#define TARGET_MOVX (x86_movx & TUNEMASK)
#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
#define TARGET_USE_LOOP (x86_use_loop & TUNEMASK)
#define TARGET_USE_FIOP (x86_use_fiop & TUNEMASK)
#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
#define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
#define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
#define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
#define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
#define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
#define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
#define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
(x86_sse_partial_reg_dependency & TUNEMASK)
#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & TUNEMASK)
#define TARGET_PREFETCH_SSE (x86_prefetch_sse)
#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
#define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
#define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
#define TARGET_USE_BT (x86_use_bt & TUNEMASK)
#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
#define ASSEMBLER_DIALECT (ix86_asm_dialect)
#define TARGET_SSE ((target_flags & MASK_SSE) != 0)
#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
#define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0)
#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
&& (ix86_fpmath & FPMATH_387))
#define TARGET_MMX ((target_flags & MASK_MMX) != 0)
#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
#define TARGET_USE_MS_BITFIELD_LAYOUT (target_flags & MASK_MS_BITFIELD_LAYOUT)
#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
#define TARGET_SWITCHES \
{ { "80387", MASK_80387, N_("Use hardware fp") }, \
{ "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
{ "hard-float", MASK_80387, N_("Use hardware fp") }, \
{ "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
{ "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
{ "386", 0, "" }, \
{ "486", 0, "" }, \
{ "pentium", 0, "" }, \
{ "pentiumpro", 0, "" }, \
{ "intel-syntax", 0, "" }, \
{ "no-intel-syntax", 0, "" }, \
{ "rtd", MASK_RTD, \
N_("Alternate calling convention") }, \
{ "no-rtd", -MASK_RTD, \
N_("Use normal calling convention") }, \
{ "align-double", MASK_ALIGN_DOUBLE, \
N_("Align some doubles on dword boundary") }, \
{ "no-align-double", -MASK_ALIGN_DOUBLE, \
N_("Align doubles on word boundary") }, \
{ "svr3-shlib", MASK_SVR3_SHLIB, \
N_("Uninitialized locals in .bss") }, \
{ "no-svr3-shlib", -MASK_SVR3_SHLIB, \
N_("Uninitialized locals in .data") }, \
{ "ieee-fp", MASK_IEEE_FP, \
N_("Use IEEE math for fp comparisons") }, \
{ "no-ieee-fp", -MASK_IEEE_FP, \
N_("Do not use IEEE math for fp comparisons") }, \
{ "fp-ret-in-387", MASK_FLOAT_RETURNS, \
N_("Return values of functions in FPU registers") }, \
{ "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
N_("Do not return values of functions in FPU registers")}, \
{ "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
N_("Do not generate sin, cos, sqrt for FPU") }, \
{ "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
N_("Generate sin, cos, sqrt for FPU")}, \
{ "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
N_("Omit the frame pointer in leaf functions") }, \
{ "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
{ "stack-arg-probe", MASK_STACK_PROBE, \
N_("Enable stack probing") }, \
{ "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
{ "windows", 0, 0 }, \
{ "dll", 0, 0 }, \
{ "align-stringops", -MASK_NO_ALIGN_STROPS, \
N_("Align destination of the string operations") }, \
{ "no-align-stringops", MASK_NO_ALIGN_STROPS, \
N_("Do not align destination of the string operations") }, \
{ "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
N_("Inline all known string operations") }, \
{ "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
N_("Do not inline all known string operations") }, \
{ "push-args", -MASK_NO_PUSH_ARGS, \
N_("Use push instructions to save outgoing arguments") }, \
{ "no-push-args", MASK_NO_PUSH_ARGS, \
N_("Do not use push instructions to save outgoing arguments") }, \
{ "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
N_("Use push instructions to save outgoing arguments") }, \
{ "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
N_("Do not use push instructions to save outgoing arguments") }, \
{ "mmx", MASK_MMX, \
N_("Support MMX built-in functions") }, \
{ "no-mmx", -(MASK_MMX|MASK_3DNOW|MASK_3DNOW_A), \
N_("Do not support MMX built-in functions") }, \
{ "3dnow", MASK_3DNOW, \
N_("Support 3DNow! built-in functions") }, \
{ "no-3dnow", -(MASK_3DNOW|MASK_3DNOW_A), \
N_("Do not support 3DNow! built-in functions") }, \
{ "sse", MASK_SSE, \
N_("Support MMX and SSE built-in functions and code generation") }, \
{ "no-sse", -(MASK_SSE|MASK_SSE2|MASK_SSE3), \
N_("Do not support MMX and SSE built-in functions and code generation") },\
{ "sse2", MASK_SSE2, \
N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
{ "no-sse2", -(MASK_SSE2|MASK_SSE3), \
N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
{ "sse3", MASK_SSE3, \
N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
{ "no-sse3", -MASK_SSE3, \
N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
{ "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
N_("sizeof(long double) is 16") }, \
{ "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
N_("sizeof(long double) is 12") }, \
{ "64", MASK_64BIT, \
N_("Generate 64bit x86-64 code") }, \
{ "32", -MASK_64BIT, \
N_("Generate 32bit i386 code") }, \
{ "ms-bitfields", MASK_MS_BITFIELD_LAYOUT, \
N_("Use native (MS) bitfield layout") }, \
{ "no-ms-bitfields", -MASK_MS_BITFIELD_LAYOUT, \
N_("Use gcc default bitfield layout") }, \
{ "red-zone", -MASK_NO_RED_ZONE, \
N_("Use red-zone in the x86-64 code") }, \
{ "no-red-zone", MASK_NO_RED_ZONE, \
N_("Do not use red-zone in the x86-64 code") }, \
{ "tls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS, \
N_("Use direct references against %gs when accessing tls data") }, \
{ "no-tls-direct-seg-refs", -MASK_TLS_DIRECT_SEG_REFS, \
N_("Do not use direct references against %gs when accessing tls data") }, \
SUBTARGET_SWITCHES \
{ "", \
TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT \
| TARGET_TLS_DIRECT_SEG_REFS_DEFAULT, 0 }}
#ifndef TARGET_64BIT_DEFAULT
#define TARGET_64BIT_DEFAULT 0
#endif
#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
#endif
#define TARGET_DEFAULT 0
#define TARGET_MACHO 0
#define TARGET_96_ROUND_53_LONG_DOUBLE 0
#define TARGET_OPTIONS \
{ { "tune=", &ix86_tune_string, \
N_("Schedule code for given CPU"), 0}, \
{ "fpmath=", &ix86_fpmath_string, \
N_("Generate floating point mathematics using given instruction set"), 0},\
{ "arch=", &ix86_arch_string, \
N_("Generate code for given CPU"), 0}, \
{ "regparm=", &ix86_regparm_string, \
N_("Number of registers used to pass integer arguments"), 0},\
{ "align-loops=", &ix86_align_loops_string, \
N_("Loop code aligned to this power of 2"), 0}, \
{ "align-jumps=", &ix86_align_jumps_string, \
N_("Jump targets are aligned to this power of 2"), 0}, \
{ "align-functions=", &ix86_align_funcs_string, \
N_("Function starts are aligned to this power of 2"), 0}, \
{ "preferred-stack-boundary=", \
&ix86_preferred_stack_boundary_string, \
N_("Attempt to keep stack aligned to this power of 2"), 0}, \
{ "branch-cost=", &ix86_branch_cost_string, \
N_("Branches are this expensive (1-5, arbitrary units)"), 0},\
{ "cmodel=", &ix86_cmodel_string, \
N_("Use given x86-64 code model"), 0}, \
{ "debug-arg", &ix86_debug_arg_string, \
"" , 0}, \
{ "debug-addr", &ix86_debug_addr_string, \
"" , 0}, \
{ "asm=", &ix86_asm_string, \
N_("Use given assembler dialect"), 0}, \
{ "tls-dialect=", &ix86_tls_dialect_string, \
N_("Use given thread-local storage dialect"), 0}, \
SUBTARGET_OPTIONS \
}
#define OVERRIDE_OPTIONS override_options ()
#define SUBTARGET_SWITCHES
#define SUBTARGET_OPTIONS
#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
optimization_options ((LEVEL), (SIZE))
#define OPTION_DEFAULT_SPECS \
{"arch", "%{!march=*:-march=%(VALUE)}"}, \
{"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
{"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }
#ifndef CC1_CPU_SPEC
#define CC1_CPU_SPEC "\
%{!mtune*: \
%{m386:mtune=i386 \
%n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
%{m486:-mtune=i486 \
%n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
%{mpentium:-mtune=pentium \
%n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
%{mpentiumpro:-mtune=pentiumpro \
%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
%{mcpu=*:-mtune=%* \
%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
%<mcpu=* \
%{mintel-syntax:-masm=intel \
%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
%{mno-intel-syntax:-masm=att \
%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
#endif
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
size_t arch_len = strlen (ix86_arch_string); \
size_t tune_len = strlen (ix86_tune_string); \
int last_arch_char = ix86_arch_string[arch_len - 1]; \
int last_tune_char = ix86_tune_string[tune_len - 1]; \
\
if (TARGET_64BIT) \
{ \
builtin_assert ("cpu=x86_64"); \
builtin_assert ("machine=x86_64"); \
builtin_define ("__amd64"); \
builtin_define ("__amd64__"); \
builtin_define ("__x86_64"); \
builtin_define ("__x86_64__"); \
} \
else \
{ \
builtin_assert ("cpu=i386"); \
builtin_assert ("machine=i386"); \
builtin_define_std ("i386"); \
} \
\
\
if (TARGET_386) \
builtin_define ("__tune_i386__"); \
else if (TARGET_486) \
builtin_define ("__tune_i486__"); \
else if (TARGET_PENTIUM) \
{ \
builtin_define ("__tune_i586__"); \
builtin_define ("__tune_pentium__"); \
if (last_tune_char == 'x') \
builtin_define ("__tune_pentium_mmx__"); \
} \
else if (TARGET_PENTIUMPRO) \
{ \
builtin_define ("__tune_i686__"); \
builtin_define ("__tune_pentiumpro__"); \
switch (last_tune_char) \
{ \
case '3': \
builtin_define ("__tune_pentium3__"); \
\
case '2': \
builtin_define ("__tune_pentium2__"); \
break; \
} \
} \
else if (TARGET_K6) \
{ \
builtin_define ("__tune_k6__"); \
if (last_tune_char == '2') \
builtin_define ("__tune_k6_2__"); \
else if (last_tune_char == '3') \
builtin_define ("__tune_k6_3__"); \
} \
else if (TARGET_ATHLON) \
{ \
builtin_define ("__tune_athlon__"); \
\
if (last_tune_char != 'n') \
builtin_define ("__tune_athlon_sse__"); \
} \
else if (TARGET_K8) \
builtin_define ("__tune_k8__"); \
else if (TARGET_PENTIUM4) \
builtin_define ("__tune_pentium4__"); \
else if (TARGET_NOCONA) \
builtin_define ("__tune_nocona__"); \
\
if (TARGET_MMX) \
builtin_define ("__MMX__"); \
if (TARGET_3DNOW) \
builtin_define ("__3dNOW__"); \
if (TARGET_3DNOW_A) \
builtin_define ("__3dNOW_A__"); \
if (TARGET_SSE) \
builtin_define ("__SSE__"); \
if (TARGET_SSE2) \
builtin_define ("__SSE2__"); \
if (TARGET_SSE3) \
builtin_define ("__SSE3__"); \
if (TARGET_SSE_MATH && TARGET_SSE) \
builtin_define ("__SSE_MATH__"); \
if (TARGET_SSE_MATH && TARGET_SSE2) \
builtin_define ("__SSE2_MATH__"); \
\
\
if (ix86_arch == PROCESSOR_I486) \
{ \
builtin_define ("__i486"); \
builtin_define ("__i486__"); \
} \
else if (ix86_arch == PROCESSOR_PENTIUM) \
{ \
builtin_define ("__i586"); \
builtin_define ("__i586__"); \
builtin_define ("__pentium"); \
builtin_define ("__pentium__"); \
if (last_arch_char == 'x') \
builtin_define ("__pentium_mmx__"); \
} \
else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
{ \
builtin_define ("__i686"); \
builtin_define ("__i686__"); \
builtin_define ("__pentiumpro"); \
builtin_define ("__pentiumpro__"); \
} \
else if (ix86_arch == PROCESSOR_K6) \
{ \
\
builtin_define ("__k6"); \
builtin_define ("__k6__"); \
if (last_arch_char == '2') \
builtin_define ("__k6_2__"); \
else if (last_arch_char == '3') \
builtin_define ("__k6_3__"); \
} \
else if (ix86_arch == PROCESSOR_ATHLON) \
{ \
builtin_define ("__athlon"); \
builtin_define ("__athlon__"); \
\
if (last_arch_char != 'n') \
builtin_define ("__athlon_sse__"); \
} \
else if (ix86_arch == PROCESSOR_K8) \
{ \
builtin_define ("__k8"); \
builtin_define ("__k8__"); \
} \
else if (ix86_arch == PROCESSOR_PENTIUM4) \
{ \
builtin_define ("__pentium4"); \
builtin_define ("__pentium4__"); \
} \
else if (ix86_arch == PROCESSOR_NOCONA) \
{ \
builtin_define ("__nocona"); \
builtin_define ("__nocona__"); \
} \
} \
while (0)
#define TARGET_CPU_DEFAULT_i386 0
#define TARGET_CPU_DEFAULT_i486 1
#define TARGET_CPU_DEFAULT_pentium 2
#define TARGET_CPU_DEFAULT_pentium_mmx 3
#define TARGET_CPU_DEFAULT_pentiumpro 4
#define TARGET_CPU_DEFAULT_pentium2 5
#define TARGET_CPU_DEFAULT_pentium3 6
#define TARGET_CPU_DEFAULT_pentium4 7
#define TARGET_CPU_DEFAULT_k6 8
#define TARGET_CPU_DEFAULT_k6_2 9
#define TARGET_CPU_DEFAULT_k6_3 10
#define TARGET_CPU_DEFAULT_athlon 11
#define TARGET_CPU_DEFAULT_athlon_sse 12
#define TARGET_CPU_DEFAULT_k8 13
#define TARGET_CPU_DEFAULT_pentium_m 14
#define TARGET_CPU_DEFAULT_prescott 15
#define TARGET_CPU_DEFAULT_nocona 16
#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
"pentiumpro", "pentium2", "pentium3", \
"pentium4", "k6", "k6-2", "k6-3",\
"athlon", "athlon-4", "k8", \
"pentium-m", "prescott", "nocona"}
#ifndef CC1_SPEC
#define CC1_SPEC "%(cc1_cpu) "
#endif
#ifndef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#endif
#define EXTRA_SPECS \
{ "cc1_cpu", CC1_CPU_SPEC }, \
SUBTARGET_EXTRA_SPECS
#define LONG_DOUBLE_TYPE_SIZE 80
#define TARGET_FLT_EVAL_METHOD \
(TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
#define SHORT_TYPE_SIZE 16
#define INT_TYPE_SIZE 32
#define FLOAT_TYPE_SIZE 32
#define LONG_TYPE_SIZE BITS_PER_WORD
#define DOUBLE_TYPE_SIZE 64
#define LONG_LONG_TYPE_SIZE 64
#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
#define MAX_BITS_PER_WORD 64
#else
#define MAX_BITS_PER_WORD 32
#endif
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN 0
#define WORDS_BIG_ENDIAN 0
#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
#ifdef IN_LIBGCC2
#define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
#else
#define MIN_UNITS_PER_WORD 4
#endif
#define PARM_BOUNDARY BITS_PER_WORD
#define STACK_BOUNDARY ((ix86_preferred_stack_boundary >= 128) ? 128 : \
(ix86_preferred_stack_boundary == 64) ? 64 : 32)
#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
(ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
#define FUNCTION_BOUNDARY 8
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
#define BIGGEST_ALIGNMENT 128
#define ALIGN_MODE_128(MODE) \
((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE))
#ifdef IN_TARGET_LIBS
#ifdef __x86_64__
#define BIGGEST_FIELD_ALIGNMENT 128
#else
#define BIGGEST_FIELD_ALIGNMENT 32
#endif
#else
#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED, FIRST_FIELD_P) \
x86_field_alignment (FIELD, COMPUTED)
#endif
#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
#define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
ix86_function_arg_boundary ((MODE), (TYPE))
#define STRICT_ALIGNMENT 0
#define PCC_BITFIELD_TYPE_MATTERS 1
#define STACK_REGS
#define IS_STACK_MODE(MODE) \
((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode) \
#define FIRST_PSEUDO_REGISTER 53
#define DWARF_FRAME_REGISTERS 17
#define FIXED_REGISTERS \
\
{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
\
1, 1, 1, 1, 1, \
\
0, 0, 0, 0, 0, 0, 0, 0, \
\
0, 0, 0, 0, 0, 0, 0, 0, \
\
2, 2, 2, 2, 2, 2, 2, 2, \
\
2, 2, 2, 2, 2, 2, 2, 2}
#define CALL_USED_REGISTERS \
\
{ 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 2, 2, 2, 2, \
\
1, 1, 1, 1, 1, 1, 1, 1} \
#define REG_ALLOC_ORDER \
{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52 }
#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
#define CONDITIONAL_REGISTER_USAGE \
do { \
int i; \
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
{ \
if (fixed_regs[i] > 1) \
fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
if (call_used_regs[i] > 1) \
call_used_regs[i] = (call_used_regs[i] \
== (TARGET_64BIT ? 3 : 2)); \
} \
if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
{ \
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
} \
if (! TARGET_MMX) \
{ \
int i; \
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
} \
if (! TARGET_SSE) \
{ \
int i; \
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
} \
if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
{ \
int i; \
HARD_REG_SET x; \
COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
if (TEST_HARD_REG_BIT (x, i)) \
fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
} \
if (! TARGET_64BIT) \
{ \
int i; \
for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
reg_names[i] = ""; \
for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
reg_names[i] = ""; \
} \
} while (0)
#define HARD_REGNO_NREGS(REGNO, MODE) \
(FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
: ((MODE) == XFmode \
? (TARGET_64BIT ? 2 : 3) \
: (MODE) == XCmode \
? (TARGET_64BIT ? 4 : 6) \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
#define VALID_SSE2_REG_MODE(MODE) \
((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
|| (MODE) == V2DImode || (MODE) == DFmode)
#define VALID_SSE_REG_MODE(MODE) \
((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
|| (MODE) == SFmode || (MODE) == TFmode)
#define VALID_MMX_REG_MODE_3DNOW(MODE) \
((MODE) == V2SFmode || (MODE) == SFmode)
#define VALID_MMX_REG_MODE(MODE) \
((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
|| (MODE) == V2SImode || (MODE) == SImode)
#define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : 0)
#define VALID_FP_MODE_P(MODE) \
((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
|| (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
#define VALID_INT_MODE_P(MODE) \
((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
|| (MODE) == DImode \
|| (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
|| (MODE) == CDImode \
|| (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
|| (MODE) == TFmode || (MODE) == TCmode)))
#define SSE_REG_MODE_P(MODE) \
((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
|| (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
|| (MODE) == V4SFmode || (MODE) == V4SImode)
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
ix86_hard_regno_mode_ok ((REGNO), (MODE))
#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
#define AVOID_CCMODE_COPIES
#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
(CC_REGNO_P (REGNO) ? VOIDmode \
: (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
: (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
: (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
: (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
: (MODE))
#define STACK_POINTER_REGNUM 7
#define HARD_FRAME_POINTER_REGNUM 6
#define FRAME_POINTER_REGNUM 20
#define FIRST_FLOAT_REG 8
#define FIRST_STACK_REG FIRST_FLOAT_REG
#define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
#define LAST_SSE_REG (FIRST_SSE_REG + 7)
#define FIRST_MMX_REG (LAST_SSE_REG + 1)
#define LAST_MMX_REG (FIRST_MMX_REG + 7)
#define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
#define SUBTARGET_FRAME_POINTER_REQUIRED 0
#endif
#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
#define ARG_POINTER_REGNUM 16
#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
#define REAL_PIC_OFFSET_TABLE_REGNUM 3
#define PIC_OFFSET_TABLE_REGNUM \
(TARGET_64BIT || !flag_pic ? INVALID_REGNUM \
: reload_completed ? REGNO (pic_offset_table_rtx) \
: REAL_PIC_OFFSET_TABLE_REGNUM)
#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
#define RETURN_IN_MEMORY(TYPE) \
ix86_return_in_memory (TYPE)
#define MS_AGGREGATE_RETURN 0
#define KEEP_AGGREGATE_RETURN_POINTER 0
enum reg_class
{
NO_REGS,
AREG, DREG, CREG, BREG, SIREG, DIREG,
AD_REGS,
Q_REGS,
NON_Q_REGS,
INDEX_REGS,
LEGACY_REGS,
GENERAL_REGS,
FP_TOP_REG, FP_SECOND_REG,
FLOAT_REGS,
SSE_REGS,
MMX_REGS,
FP_TOP_SSE_REGS,
FP_SECOND_SSE_REGS,
FLOAT_SSE_REGS,
FLOAT_INT_REGS,
INT_SSE_REGS,
FLOAT_INT_SSE_REGS,
ALL_REGS, LIM_REG_CLASSES
};
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
#define INTEGER_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), GENERAL_REGS)
#define FLOAT_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), FLOAT_REGS)
#define SSE_CLASS_P(CLASS) \
((CLASS) == SSE_REGS)
#define MMX_CLASS_P(CLASS) \
((CLASS) == MMX_REGS)
#define MAYBE_INTEGER_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), GENERAL_REGS)
#define MAYBE_FLOAT_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), FLOAT_REGS)
#define MAYBE_SSE_CLASS_P(CLASS) \
reg_classes_intersect_p (SSE_REGS, (CLASS))
#define MAYBE_MMX_CLASS_P(CLASS) \
reg_classes_intersect_p (MMX_REGS, (CLASS))
#define Q_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), Q_REGS)
#define REG_CLASS_NAMES \
{ "NO_REGS", \
"AREG", "DREG", "CREG", "BREG", \
"SIREG", "DIREG", \
"AD_REGS", \
"Q_REGS", "NON_Q_REGS", \
"INDEX_REGS", \
"LEGACY_REGS", \
"GENERAL_REGS", \
"FP_TOP_REG", "FP_SECOND_REG", \
"FLOAT_REGS", \
"SSE_REGS", \
"MMX_REGS", \
"FP_TOP_SSE_REGS", \
"FP_SECOND_SSE_REGS", \
"FLOAT_SSE_REGS", \
"FLOAT_INT_REGS", \
"INT_SSE_REGS", \
"FLOAT_INT_SSE_REGS", \
"ALL_REGS" }
#define REG_CLASS_CONTENTS \
{ { 0x00, 0x0 }, \
{ 0x01, 0x0 }, { 0x02, 0x0 }, \
{ 0x04, 0x0 }, { 0x08, 0x0 }, \
{ 0x10, 0x0 }, { 0x20, 0x0 }, \
{ 0x03, 0x0 }, \
{ 0x0f, 0x0 }, \
{ 0x1100f0, 0x1fe0 }, \
{ 0x7f, 0x1fe0 }, \
{ 0x1100ff, 0x0 }, \
{ 0x1100ff, 0x1fe0 }, \
{ 0x100, 0x0 }, { 0x0200, 0x0 },\
{ 0xff00, 0x0 }, \
{ 0x1fe00000,0x1fe000 }, \
{ 0xe0000000, 0x1f }, \
{ 0x1fe00100,0x1fe000 }, \
{ 0x1fe00200,0x1fe000 }, \
{ 0x1fe0ff00,0x1fe000 }, \
{ 0x1ffff, 0x1fe0 }, \
{ 0x1fe100ff,0x1fffe0 }, \
{ 0x1fe1ffff,0x1fffe0 }, \
{ 0xffffffff,0x1fffff } \
}
#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
#define SMALL_REGISTER_CLASSES 1
#define QI_REG_P(X) \
(REG_P (X) && REGNO (X) < 4)
#define GENERAL_REGNO_P(N) \
((N) < 8 || REX_INT_REGNO_P (N))
#define GENERAL_REG_P(X) \
(REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
#define NON_QI_REG_P(X) \
(REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
#define SSE_REGNO_P(N) \
(((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
|| ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
#define REX_SSE_REGNO_P(N) \
((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
#define SSE_REGNO(N) \
((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
#define SSE_FLOAT_MODE_P(MODE) \
((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
#define STACK_REG_P(XOP) \
(REG_P (XOP) && \
REGNO (XOP) >= FIRST_STACK_REG && \
REGNO (XOP) <= LAST_STACK_REG)
#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
#define INDEX_REG_CLASS INDEX_REGS
#define BASE_REG_CLASS GENERAL_REGS
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'r' ? GENERAL_REGS : \
(C) == 'R' ? LEGACY_REGS : \
(C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
(C) == 'Q' ? Q_REGS : \
(C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
? FLOAT_REGS \
: NO_REGS) : \
(C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
? FP_TOP_REG \
: NO_REGS) : \
(C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
? FP_SECOND_REG \
: NO_REGS) : \
(C) == 'a' ? AREG : \
(C) == 'b' ? BREG : \
(C) == 'c' ? CREG : \
(C) == 'd' ? DREG : \
(C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
(C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
(C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
(C) == 'A' ? AD_REGS : \
(C) == 'D' ? DIREG : \
(C) == 'S' ? SIREG : \
(C) == 'l' ? INDEX_REGS : \
NO_REGS)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
: (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
: (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
: (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
: (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
: (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
: 0)
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'G' ? standard_80387_constant_p (VALUE) \
: 0)
#define EXTRA_CONSTRAINT(VALUE, D) \
((D) == 'e' ? x86_64_immediate_operand (VALUE, VOIDmode) \
: (D) == 'Z' ? x86_64_zext_immediate_operand (VALUE, VOIDmode) \
: (D) == 'C' ? standard_sse_constant_p (VALUE) \
: 0)
#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
((MODE) == QImode && !TARGET_64BIT \
&& ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
|| (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
? Q_REGS : (CLASS))
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
ix86_preferred_reload_class ((X), (CLASS))
#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
ix86_preferred_output_reload_class ((X), (CLASS))
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
(((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
|| (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
? Q_REGS : NO_REGS)
#define CLASS_MAX_NREGS(CLASS, MODE) \
(!MAYBE_INTEGER_CLASS_P (CLASS) \
? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
: (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
+ UNITS_PER_WORD - 1) / UNITS_PER_WORD))
#define CLASS_LIKELY_SPILLED_P(CLASS) \
(((CLASS) == AREG) \
|| ((CLASS) == DREG) \
|| ((CLASS) == CREG) \
|| ((CLASS) == BREG) \
|| ((CLASS) == AD_REGS) \
|| ((CLASS) == SIREG) \
|| ((CLASS) == DIREG) \
|| ((CLASS) == FP_TOP_REG) \
|| ((CLASS) == FP_SECOND_REG))
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
ix86_cannot_change_mode_class (FROM, TO, CLASS)
#define STACK_GROWS_DOWNWARD
#define FRAME_GROWS_DOWNWARD
#define STARTING_FRAME_OFFSET 0
#define PUSH_ROUNDING(BYTES) \
(TARGET_64BIT \
? (((BYTES) + 7) & (-8)) \
: (((BYTES) + 1) & (-2)))
#define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
#define PUSH_ARGS_REVERSED 1
#define FIRST_PARM_OFFSET(FNDECL) 0
#define REG_PARM_STACK_SPACE(FNDECL) 0
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
#define FUNCTION_VALUE(VALTYPE, FUNC) \
ix86_function_value (VALTYPE, FUNC, 0)
#define FUNCTION_VALUE_REGNO_P(N) \
ix86_function_value_regno_p (N)
#define LIBCALL_VALUE(MODE) \
ix86_libcall_value (MODE)
#define APPLY_RESULT_SIZE (8+108)
#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
typedef struct ix86_args {
int words;
int nregs;
int regno;
int fastcall;
int sse_words;
int sse_nregs;
int warn_sse;
int warn_mmx;
int sse_regno;
int mmx_words;
int mmx_nregs;
int mmx_regno;
int maybe_vaarg;
int float_in_sse;
} CUMULATIVE_ARGS;
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
function_arg (&(CUM), (MODE), (TYPE), (NAMED))
#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
ix86_va_start (VALIST, NEXTARG)
#define TARGET_ASM_FILE_END ix86_file_end
#define NEED_INDICATE_EXEC_STACK 0
#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
#define MCOUNT_NAME "_mcount"
#define PROFILE_COUNT_REGISTER "edx"
#define EXIT_IGNORE_STACK 1
#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
#define CAN_ELIMINATE(FROM, TO) \
((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
#define REGNO_OK_FOR_INDEX_P(REGNO) \
((REGNO) < STACK_POINTER_REGNUM \
|| (REGNO >= FIRST_REX_INT_REG \
&& (REGNO) <= LAST_REX_INT_REG) \
|| ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
&& (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
|| (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
#define REGNO_OK_FOR_BASE_P(REGNO) \
((REGNO) <= STACK_POINTER_REGNUM \
|| (REGNO) == ARG_POINTER_REGNUM \
|| (REGNO) == FRAME_POINTER_REGNUM \
|| (REGNO >= FIRST_REX_INT_REG \
&& (REGNO) <= LAST_REX_INT_REG) \
|| ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
&& (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
|| (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
#define REGNO_OK_FOR_SIREG_P(REGNO) \
((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
#define REGNO_OK_FOR_DIREG_P(REGNO) \
((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
(REGNO (X) < STACK_POINTER_REGNUM \
|| (REGNO (X) >= FIRST_REX_INT_REG \
&& REGNO (X) <= LAST_REX_INT_REG) \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER)
#define REG_OK_FOR_BASE_NONSTRICT_P(X) \
(REGNO (X) <= STACK_POINTER_REGNUM \
|| REGNO (X) == ARG_POINTER_REGNUM \
|| REGNO (X) == FRAME_POINTER_REGNUM \
|| (REGNO (X) >= FIRST_REX_INT_REG \
&& REGNO (X) <= LAST_REX_INT_REG) \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER)
#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
#ifndef REG_OK_STRICT
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
#else
#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
#endif
#define MAX_REGS_PER_ADDRESS 2
#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
#ifdef REG_OK_STRICT
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
do { \
if (legitimate_address_p ((MODE), (X), 1)) \
goto ADDR; \
} while (0)
#else
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
do { \
if (legitimate_address_p ((MODE), (X), 0)) \
goto ADDR; \
} while (0)
#endif
#define FIND_BASE_TERM(X) ix86_find_base_term (X)
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
do { \
(X) = legitimize_address ((X), (OLDX), (MODE)); \
if (memory_address_p ((MODE), (X))) \
goto WIN; \
} while (0)
#define REWRITE_ADDRESS(X) rewrite_address (X)
#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
#define SYMBOLIC_CONST(X) \
(GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == LABEL_REF \
|| (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
do { \
if (GET_CODE (ADDR) == POST_INC \
|| GET_CODE (ADDR) == POST_DEC) \
goto LABEL; \
} while (0)
#define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
#define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_MACHO ? 4 : (TARGET_SSE ? 3 : 0)))
#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
#define DEFAULT_SIGNED_CHAR 1
#define PREFETCH_BLOCK ix86_cost->prefetch_block
#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
#define MOVE_MAX 16
#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
#define CLEAR_RATIO (optimize_size ? 2 \
: ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
do { \
if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
|| ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
(MODE) = SImode; \
} while (0)
#define Pmode (TARGET_64BIT ? DImode : SImode)
#define FUNCTION_MODE QImode
#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
#define MEMORY_MOVE_COST(MODE, CLASS, IN) \
ix86_memory_move_cost ((MODE), (CLASS), (IN))
#define BRANCH_COST ix86_branch_cost
#define SLOW_BYTE_ACCESS 0
#define SLOW_SHORT_ACCESS 0
#define NO_FUNCTION_CSE
#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
#define REVERSIBLE_CC_MODE(MODE) 1
#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
#define HI_REGISTER_NAMES \
{"ax","dx","cx","bx","si","di","bp","sp", \
"st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
"argp", "flags", "fpsr", "dirflag", "frame", \
"xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
"xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
#define REGISTER_NAMES HI_REGISTER_NAMES
#define ADDITIONAL_REGISTER_NAMES \
{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
{ "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
{ "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
{ "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
{ "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
{ "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
#define QI_REGISTER_NAMES \
{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
#define QI_HIGH_REGISTER_NAMES \
{"ah", "dh", "ch", "bh", }
#define DBX_REGISTER_NUMBER(N) \
(TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
#define INCOMING_RETURN_ADDR_RTX \
gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
#define RETURN_ADDR_RTX(COUNT, FRAME) \
((COUNT) == 0 \
? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
: gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
#define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
(flag_pic \
? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
: DW_EH_PE_absptr)
#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
do { \
if (TARGET_64BIT) \
asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
else \
asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
} while (0)
#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
do { \
if (TARGET_64BIT) \
asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
else \
asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
} while (0)
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
ix86_output_addr_vec_elt ((FILE), (VALUE))
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
#define JUMP_TABLES_IN_TEXT_SECTION \
(!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
#ifdef HAVE_AS_TLS
#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
i386_output_dwarf_dtprel (FILE, SIZE, X)
#endif
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm (SECTION_OP "\n\t" \
"call " USER_LABEL_PREFIX #FUNC "\n" \
TEXT_SECTION_ASM_OP);
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
#define PRINT_OPERAND(FILE, X, CODE) \
print_operand ((FILE), (X), (CODE))
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
print_operand_address ((FILE), (ADDR))
#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
do { \
if (! output_addr_const_extra (FILE, (X))) \
goto FAIL; \
} while (0);
#define ASM_OPERAND_LETTER '#'
#define RET return ""
#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
enum processor_type
{
PROCESSOR_I386,
PROCESSOR_I486,
PROCESSOR_PENTIUM,
PROCESSOR_PENTIUMPRO,
PROCESSOR_K6,
PROCESSOR_ATHLON,
PROCESSOR_PENTIUM4,
PROCESSOR_K8,
PROCESSOR_NOCONA,
PROCESSOR_max
};
extern enum processor_type ix86_tune;
extern const char *ix86_tune_string;
extern enum processor_type ix86_arch;
extern const char *ix86_arch_string;
enum fpmath_unit
{
FPMATH_387 = 1,
FPMATH_SSE = 2
};
extern enum fpmath_unit ix86_fpmath;
extern const char *ix86_fpmath_string;
enum tls_dialect
{
TLS_DIALECT_GNU,
TLS_DIALECT_SUN
};
extern enum tls_dialect ix86_tls_dialect;
extern const char *ix86_tls_dialect_string;
enum cmodel {
CM_32,
CM_SMALL,
CM_KERNEL,
CM_MEDIUM,
CM_LARGE,
CM_SMALL_PIC
};
extern enum cmodel ix86_cmodel;
extern const char *ix86_cmodel_string;
#define RED_ZONE_SIZE 128
#define RED_ZONE_RESERVE 8
enum asm_dialect {
ASM_ATT,
ASM_INTEL
};
extern const char *ix86_asm_string;
extern enum asm_dialect ix86_asm_dialect;
extern int ix86_regparm;
extern const char *ix86_regparm_string;
extern void ix86_darwin_handle_regparmandstackparm (tree fndecl);
extern void ix86_darwin_redirect_calls(void);
extern unsigned int ix86_preferred_stack_boundary;
extern const char *ix86_preferred_stack_boundary_string;
extern int ix86_branch_cost;
extern const char *ix86_branch_cost_string;
extern const char *ix86_debug_arg_string;
extern const char *ix86_debug_addr_string;
extern const char *ix86_align_loops_string;
extern const char *ix86_align_jumps_string;
extern const char *ix86_align_funcs_string;
extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
extern rtx ix86_compare_op0;
extern rtx ix86_compare_op1;
#define OPTIMIZE_MODE_SWITCHING(ENTITY) ix86_optimize_mode_switching
#define NUM_MODES_FOR_MODE_SWITCHING { I387_CW_ANY }
#define MODE_NEEDED(ENTITY, I) \
(GET_CODE (I) == CALL_INSN \
|| (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
|| GET_CODE (PATTERN (I)) == ASM_INPUT))\
? I387_CW_UNINITIALIZED \
: recog_memoized (I) < 0 \
? I387_CW_ANY \
: get_attr_i387_cw (I))
#define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
assign_386_stack_local (HImode, 2), \
MODE), 0 \
: 0)
#define HARD_REGNO_RENAME_OK(SRC, TARGET) \
((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
#define DLL_IMPORT_EXPORT_PREFIX '#'
#define FASTCALL_PREFIX '@'
struct machine_function GTY(())
{
struct stack_local_entry *stack_locals;
const char *some_ld_name;
int save_varrargs_registers;
int accesses_prev_frame;
int optimize_mode_switching;
int use_fast_prologue_epilogue;
int use_fast_prologue_epilogue_nregs;
};
#define ix86_stack_locals (cfun->machine->stack_locals)
#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
#define X86_FILE_START_VERSION_DIRECTIVE false
#define X86_FILE_START_FLTUSED false
#undef TARGET_CW_EXTRA_INFO
#define TARGET_CW_EXTRA_INFO \
char mod[3]; \
bool as_immediate; \
bool as_offset;
#define TARGET_CW_REORDER_ARG(OPCODE, NEWARGNUM, NUM_ARGS, ARGNUM) \
do { \
\
if (cw_x86_needs_swapping (opcode)) \
NEWARGNUM = NUM_ARGS - ARGNUM + 1; \
} while (0)
#define CW_SYNTH_CONSTRAINTS(R, ARGNUM, NUM_ARGS, DB) \
do { \
\
if (R \
&& ARGNUM == 2 \
&& NUM_ARGS == 2 \
&& R < &DB[sizeof(DB) / sizeof (DB[0]) - 1] \
&& strcmp (R[1].opcode, R->opcode) == 0 \
&& R[1].argnum == 3) \
{ \
tree t; \
size_t len = strlen (r->constraint) + strlen (r[1].constraint) + 1; \
char *p = alloca (len); \
\
sprintf(p, "%s%s", r->constraint, r[1].constraint); \
t = build_string (len, p); \
return TREE_STRING_POINTER (t); \
} \
} while (0)
#define TARGET_CW_PRINT_OP(BUF, ARG, ARGNUM, USES, MUST_BE_REG, MUST_NOT_BE_REG, E) \
cw_print_op (BUF, ARG, ARGNUM, USES, MUST_BE_REG, MUST_NOT_BE_REG, E)
extern tree x86_canonicalize_operands (const char **, tree, void *);
#define CW_CANONICALIZE_OPERANDS(OPCODE, NEW_OPCODE, IARGS, E) \
do { \
NEW_OPCODE = OPCODE; \
IARGS = x86_canonicalize_operands (&NEW_OPCODE, IARGS, E); \
} while (0)
#define CW_SEE_OPCODE(YYCHAR, T) \
\
((YYCHAR == TYPESPEC \
&& C_RID_CODE (T) == RID_INT) \
? IDENTIFIER : YYCHAR)
#define CW_IS_PREFIX(ID) \
do { \
const char *myname = IDENTIFIER_POINTER (ID); \
if (strcasecmp (myname, "lock") == 0 \
|| strcasecmp (myname, "rep") == 0 \
|| strcasecmp (myname, "repe") == 0 \
|| strcasecmp (myname, "repz") == 0 \
|| strcasecmp (myname, "repne") == 0 \
|| strcasecmp (myname, "repnz") == 0) \
return true; \
} while (0)
#define CW_PRINT_PREFIX(BUF, PREFIX_LIST) x86_cw_print_prefix(BUF, PREFIX_LIST)
#define CW_IMMED_PREFIX(E, BUF) \
do { \
if (! E->as_immediate) \
sprintf (BUF + strlen (BUF), "$"); \
} while (0)
#define CW_OFFSET_PREFIX(E, BUF) \
do { \
if (E->as_offset) \
sprintf (BUF + strlen (BUF), "$"); \
} while (0)
#define CW_HIDE_REG(R) FP_REGNO_P (R)
#define CW_SEE_IMMEDIATE(E) \
E->as_immediate = true
#define CW_SEE_NO_IMMEDIATE(E) \
E->as_immediate = false
#undef TARGET_CW_OP_CONSTRAINT
#define TARGET_CW_OP_CONSTRAINT \
{ "adc", 1, "+rm,r" }, \
{ "adc", 2, "ir,m" }, \
{ "add", 1, "+rm,r" }, \
{ "add", 2, "ir,m" }, \
{ "addsd", 1, "+x"}, \
{ "addsd", 2, "m"}, \
{ "addss", 1, "+x"}, \
{ "addss", 2, "m"}, \
{ "addsubpd", 1, "+x"}, \
{ "addsubpd", 2, "m"}, \
{ "addsubps", 1, "+x"}, \
{ "addsubps", 2, "m"}, \
{ "and", 1, "+rm,r"}, \
{ "and", 2, "ir,m"}, \
{ "andnpd", 1, "+x"}, \
{ "andnpd", 2, "m"}, \
{ "andnps", 1, "+x"}, \
{ "andnps", 2, "m"}, \
{ "andpd", 1, "+x"}, \
{ "andpd", 2, "m"}, \
{ "andps", 1, "+x"}, \
{ "andps", 2, "m"}, \
{ "arpl", 1, "+" rm16}, \
{ "arpl", 2, r16}, \
{ "bound", 1, U("r")}, \
{ "bound", 2, U("m")}, \
{ "bsf", 1, "=r"}, \
{ "bsf", 2, "rm"}, \
{ "bsr", 1, "=r"}, \
{ "bsr", 2, "rm"}, \
{ "bt", 1, "rm"}, \
{ "bt", 2, "ri"}, \
{ "btc", 1, "rm"}, \
{ "btc", 2, "ri"}, \
{ "btr", 1, "rm"}, \
{ "btr", 2, "ri"}, \
{ "bts", 1, "rm"}, \
{ "bts", 2, "ri"}, \
{ "call", 1, "rsm"}, \
{ "clflush", 1, "=m"}, \
{ "cmova", 2, "rm"}, \
{ "cmovae", 2, "rm"}, \
{ "cmovb", 2, "rm"}, \
{ "cmovbe", 2, "rm"}, \
{ "cmovc", 2, "rm"}, \
{ "cmove", 2, "rm"}, \
{ "cmovg", 2, "rm"}, \
{ "cmovge", 2, "rm"}, \
{ "cmovl", 2, "rm"}, \
{ "cmovle", 2, "rm"}, \
{ "cmovna", 2, "rm"}, \
{ "cmovnae", 2, "rm"}, \
{ "cmovnb", 2, "rm"}, \
{ "cmovnbe", 2, "rm"}, \
{ "cmovnc", 2, "rm"}, \
{ "cmovne", 2, "rm"}, \
{ "cmovng", 2, "rm"}, \
{ "cmovnge", 2, "rm"}, \
{ "cmovnl", 2, "rm"}, \
{ "cmovnle", 2, "rm"}, \
{ "cmovno", 2, "rm"}, \
{ "cmovnp", 2, "rm"}, \
{ "cmovns", 2, "rm"}, \
{ "cmovnz", 2, "rm"}, \
{ "cmovo", 2, "rm"}, \
{ "cmovp", 2, "rm"}, \
{ "cmovpe", 2, U("rm")}, \
{ "cmovpo", 2, U("rm")}, \
{ "cmovs", 2, "rm"}, \
{ "cmovz", 2, U("rm")}, \
{ "cmp", 1, "rm,r"}, \
{ "cmp", 2, "ir,m"}, \
{ "cmppd", 1, "=x"}, \
{ "cmppd", 2, "xm"}, \
{ "cmppd", 3, "i"}, \
{ "cmpps", 1, "=x"}, \
{ "cmpps", 2, "xm"}, \
{ "cmpps", 3, "i"}, \
{ "cmpsd", 1, "=x"}, \
{ "cmpsd", 2, "xm"}, \
{ "cmpsd", 3, "i"}, \
{ "cmpss", 1, "=x"}, \
{ "cmpss", 2, "xm"}, \
{ "cmpss", 3, "i"}, \
{ "cmpxchg", 1, "+mr"}, \
{ "cmpxchg", 2, "r"}, \
{ "comisd", 1, "x"}, \
{ "comisd", 2, "m"}, \
{ "comiss", 1, "x"}, \
{ "comiss", 2, "m"}, \
{ "cvtdq2pd", 1, "=x"}, \
{ "cvtdq2pd", 2, "m"}, \
{ "cvtdq2ps", 1, "=x"}, \
{ "cvtdq2ps", 2, "m"}, \
{ "cvtpd2pi", 1, "=y"}, \
{ "cvtpd2pi", 2, "m"}, \
{ "cvtpd2ps", 1, "=x"}, \
{ "cvtpd2ps", 2, "m"}, \
{ "cvtpi2pd", 1, "=x"}, \
{ "cvtpi2pd", 2, "m"}, \
{ "cvtpi2ps", 1, "=x"}, \
{ "cvtpi2ps", 2, "m"}, \
{ "cvtps2dq", 1, "=x"}, \
{ "cvtps2dq", 2, "m"}, \
{ "cvtps2pd", 1, "=x"}, \
{ "cvtps2pd", 2, "m"}, \
{ "cvtps2pi", 1, "=y"}, \
{ "cvtps2pi", 2, "m"}, \
{ "cvtsd2si", 1, "=r"}, \
{ "cvtsd2si", 2, "xm"}, \
{ "cvtsd2ss", 1, "=x"}, \
{ "cvtsd2ss", 2, "m"}, \
{ "cvtsi2sd", 1, "=x"}, \
{ "cvtsi2sd", 2, "m"}, \
{ "cvtsi2ss", 1, "=x"}, \
{ "cvtsi2ss", 2, "m"}, \
{ "cvtss2sd", 1, "=x"}, \
{ "cvtss2sd", 2, "m"}, \
{ "cvtss2si", 1, "=r"}, \
{ "cvtss2si", 2, "xm"}, \
{ "cvttpd2dq", 1, "=x"}, \
{ "cvttpd2dq", 2, "m"}, \
{ "cvttpd2pi", 1, "=y"}, \
{ "cvttpd2pi", 2, "m"}, \
{ "cvttps2dq", 1, "=x"}, \
{ "cvttps2dq", 2, "m"}, \
{ "cvttps2pi", 1, "=y"}, \
{ "cvttps2pi", 2, "m"}, \
{ "cvttsd2si", 1, "=r"}, \
{ "cvttsd2si", 2, "xm"}, \
{ "cvttss2si", 1, "=r"}, \
{ "cvttss2si", 2, "xm"}, \
{ "dec", 1, "+" rm8rm16rm32}, \
{ "div", 1, rm8rm16rm32}, \
{ "divpd", 1, "+x"}, \
{ "divpd", 2, "m"}, \
{ "divps", 1, "+x"}, \
{ "divps", 2, "m"}, \
{ "divsd", 1, "+x"}, \
{ "divsd", 2, "m"}, \
{ "divss", 1, "+x"}, \
{ "divss", 2, "m"}, \
{ "enter", 1, "i"}, \
{ "enter", 2, "i"}, \
{ "fadd", 1, "+t,f,@"}, \
{ "fadd", 2, "f,t," m32fpm64fp},\
{ "faddp", 1, "+f"}, \
{ "faddp", 2, "t"}, \
{ "fbld", 1, "m"}, \
{ "fbstp", 1, "m"}, \
{ "fcmovb", 1, "=t"}, \
{ "fcmovb", 2, "f"}, \
{ "fcmovbe", 1, "=t"}, \
{ "fcmovbe", 2, "f"}, \
{ "fcmove", 1, "=t"}, \
{ "fcmove", 2, "f"}, \
{ "fcmovnb", 1, "=t"}, \
{ "fcmovnb", 2, "f"}, \
{ "fcmovnbe", 1, "=t"}, \
{ "fcmovnbe", 2, "f"}, \
{ "fcmovne", 1, "=t"}, \
{ "fcmovne", 2, "f"}, \
{ "fcmovnu", 1, "=t"}, \
{ "fcmovnu", 2, "f"}, \
{ "fcmovu", 1, "=t"}, \
{ "fcmovu", 2, "f"}, \
{ "fcom", 1, "f" m32fpm64fp}, \
{ "fcomi", 1, "t"}, \
{ "fcomi", 2, "f"}, \
{ "fcomip", 1, "t"}, \
{ "fcomip", 2, "f"}, \
{ "fcomp", 1, "f" m32fpm64fp},\
{ "fdiv", 1, "+t,f,@"}, \
{ "fdiv", 2, "f,t," m32fpm64fp},\
{ "fdivp", 1, "+f"}, \
{ "fdivp", 2, "t"}, \
{ "fdivr", 1, "+t,@"}, \
{ "fdivr", 2, "f,m"}, \
{ "fdivrp", 1, "+f"}, \
{ "fdivrp", 2, "t"}, \
{ "ffree", 1, "f"}, \
{ "fiadd", 1, m2m4}, \
{ "ficom", 1, m2m4}, \
{ "ficomp", 1, m2m4}, \
{ "fidiv", 1, m2m4}, \
{ "fidivl", 1, "m"}, \
{ "fidivr", 1, m2m4}, \
{ "fidivrl", 1, "m"}, \
{ "fild", 1, "m"}, \
{ "fildl", 1, "m"}, \
{ "fildll", 1, "m"}, \
{ "fimul", 1, m2m4}, \
{ "fist", 1, "=m"}, \
{ "fistp", 1, "=m"}, \
{ "fistpll", 1, "=m"}, \
{ "fisttp", 1, "=" m2m4}, \
{ "fisttpll", 1, "=m"}, \
{ "fisub", 1, m2m4}, \
{ "fisubr", 1, m2m4}, \
{ "fld", 1, "f" m32fpm64fpm80fp},\
{ "fldcw", 1, m16}, \
{ "fldenv", 1, "m"}, \
{ "fldt", 1, "m"}, \
{ "fmul", 1, "=f,t,@"}, \
{ "fmul", 2, "t,f," m2m4}, \
{ "fmulp", 1, "=f"}, \
{ "fmulp", 2, "t"}, \
{ "fnsave", 1, "=m"}, \
{ "fnstcw", 1, "m"}, \
{ "fnstenv", 1, "m"}, \
{ "fnstsw", 1, "ma"}, \
{ "frstor", 1, "m"}, \
{ "fsave", 1, "=m"}, \
{ "fst", 1, "=f" m32fpm64fp}, \
{ "fstcw", 1, "=m"}, \
{ "fstenv", 1, "=m"}, \
{ "fstp", 1, "=f" m32fpm64fpm80fp},\
{ "fstsw", 1, "=ma"}, \
{ "fsub", 1, "=f,t,@"}, \
{ "fsub", 2, "t,f," m32fpm64fp},\
{ "fsubr", 1, "=f,t," m32fpm64fp},\
{ "fsubr", 2, "t,f,@"}, \
{ "fucom", 1, "f"}, \
{ "fucomi", 1, "t"}, \
{ "fucomi", 2, "f"}, \
{ "fucomip", 1, "t"}, \
{ "fucomip", 2, "f"}, \
{ "fucomp", 1, "f"}, \
{ "fxch", 1, "+f" }, \
{ "fxrstor", 1, "m"}, \
{ "fxsave", 1, "=m"}, \
{ "haddpd", 1, "+x"}, \
{ "haddpd", 2, "xm"}, \
{ "haddps", 1, "+x"}, \
{ "haddps", 2, "xm"}, \
{ "hsubpd", 1, "+x"}, \
{ "hsubpd", 2, "xm"}, \
{ "hsubps", 1, "+x"}, \
{ "hsubps", 2, "xm"}, \
{ "idiv", 1, "r" m4}, \
{ "imul", 1, "+r"}, \
{ "imul", 2, "rm"}, \
{ "imul", 3, "i"}, \
{ "in", 1, "=a"}, \
{ "in", 2, "i"}, \
{ "inc", 1, "+r" m4}, \
{ "ins", 1, U("=m")}, \
{ "ins", 2, U("d")}, \
{ "int", 1, "i"}, \
{ "invlpg", 1, "m"}, \
{ "ja", 1, "s"}, \
{ "jae", 1, "s"}, \
{ "jb", 1, "s"}, \
{ "jbe", 1, "s"}, \
{ "jc", 1, "s"}, \
{ "jcxz", 1, rel8}, \
{ "je", 1, "s"}, \
{ "jecxz", 1, rel8}, \
{ "jg", 1, "s"}, \
{ "jge", 1, "s"}, \
{ "jl", 1, "s"}, \
{ "jle", 1, "s"}, \
{ "jmp", 1, "sm"}, \
{ "jna", 1, "s"}, \
{ "jnae", 1, "s"}, \
{ "jnb", 1, "s"}, \
{ "jnc", 1, "s"}, \
{ "jne", 1, "s"}, \
{ "jng", 1, "s"}, \
{ "jnge", 1, "s"}, \
{ "jnl", 1, "s"}, \
{ "jnle", 1, "s"}, \
{ "jno", 1, "s"}, \
{ "jnp", 1, "s"}, \
{ "jns", 1, "s"}, \
{ "jnz", 1, "s"}, \
{ "jo", 1, "s"}, \
{ "jp", 1, "s"}, \
{ "jpe", 1, "s"}, \
{ "jpo", 1, "s"}, \
{ "js", 1, "s"}, \
{ "jz", 1, "s"}, \
{ "lar", 1, "=r"}, \
{ "lar", 2, "rm"}, \
{ "lddqu", 1, "=x"}, \
{ "lddqu", 2, "m"}, \
{ "ldmxcsr", 1, "m"}, \
{ "lds", 1, "=r"}, \
{ "lds", 2, m4}, \
{ "lea", 1, "=r"}, \
{ "lea", 2, "m"}, \
{ "les", 1, "=r"}, \
{ "les", 2, "m"}, \
{ "lfs", 1, "=r"}, \
{ "lfs", 2, "m"}, \
{ "lgdt", 1, "m"}, \
{ "lgs", 1, "=r"}, \
{ "lgs", 2, "m"}, \
{ "lidt", 1, "m"}, \
{ "lldt", 1, "rm"}, \
{ "lmsw", 1, "m"}, \
{ "lods", 1, U("m")}, \
{ "loop", 1, rel8}, \
{ "loope", 1, rel8}, \
{ "loopne", 1, rel8}, \
{ "loopnz", 1, rel8}, \
{ "loopz", 1, rel8}, \
{ "lsl", 1, "=" r16 "," r32}, \
{ "lsl", 2, rm16 "," rm32}, \
{ "lss", 1, "=r"}, \
{ "lss", 2, m4}, \
{ "ltr", 1, "rm"}, \
{ "maskmovdqu", 1, "x"}, \
{ "maskmovdqu", 2, "x"}, \
{ "maskmovq", 1, "y"}, \
{ "maskmovq", 2, "y"}, \
{ "maxpd", 1, "+x"}, \
{ "maxpd", 2, "xm"}, \
{ "maxps", 1, "+x"}, \
{ "maxps", 2, "xm"}, \
{ "maxsd", 1, "+x"}, \
{ "maxsd", 2, "xm"}, \
{ "maxss", 1, "+x"}, \
{ "maxss", 2, "xm"}, \
{ "minpd", 1, "+x"}, \
{ "minpd", 2, "xm"}, \
{ "minps", 1, "+x"}, \
{ "minps", 2, "xm"}, \
{ "minsd", 1, "+x"}, \
{ "minsd", 2, "xm"}, \
{ "minss", 1, "+x"}, \
{ "minss", 2, "xm"}, \
{ "mov", 1, "=rm" S("4") ",r"},\
{ "mov", 2, "ri,rmi"}, \
{ "movapd", 1, "=x,xm"}, \
{ "movapd", 2, "xm,x"}, \
{ "movaps", 1, "=x,xm"}, \
{ "movaps", 2, "xm,x"}, \
{ "movd", 1, "=rm,x,y,rm"}, \
{ "movd", 2, "x,rm,rm,y"}, \
{ "movddup", 1, "=x"}, \
{ "movddup", 2, "xm"}, \
{ "movdq2q", 1, "=y"}, \
{ "movdq2q", 2, "x"}, \
{ "movdqa", 1, "=x"}, \
{ "movdqa", 2, "xm"}, \
{ "movdqu", 1, "=x"}, \
{ "movdqu", 2, "xm"}, \
{ "movhlps", 1, "=x"}, \
{ "movhlps", 2, "x"}, \
{ "movhpd", 1, "=x,m"}, \
{ "movhpd", 2, "m,x"}, \
{ "movhps", 1, "=x,m"}, \
{ "movhps", 2, "m,x"}, \
{ "movlhps", 1, "=x"}, \
{ "movlhps", 2, "x"}, \
{ "movlpd", 1, "=x,m"}, \
{ "movlpd", 2, "m,x"}, \
{ "movlps", 1, "=x,m"}, \
{ "movlps", 2, "m,x"}, \
{ "movmskpd", 1, "=r"}, \
{ "movmskpd", 2, "x"}, \
{ "movmskps", 1, "=r"}, \
{ "movmskps", 2, "x"}, \
{ "movntdq", 1, "=m"}, \
{ "movntdq", 2, "x"}, \
{ "movnti", 1, "=m"}, \
{ "movnti", 2, "r"}, \
{ "movntpd", 1, "=m"}, \
{ "movntpd", 2, "x"}, \
{ "movntps", 1, "=m"}, \
{ "movntps", 2, "x"}, \
{ "movntq", 1, "=m"}, \
{ "movntq", 2, "y"}, \
{ "movq", 1, "=x,m,y,m"}, \
{ "movq", 2, "xm,x,ym,y"}, \
{ "movq2dq", 1, "=x"}, \
{ "movq2dq", 2, "y"}, \
{ "movs", 1, U("=m")}, \
{ "movs", 2, U("m")}, \
{ "movsd", 1, "=xm,x"}, \
{ "movsd", 2, "x,xm"}, \
{ "movshdup", 1, "=x"}, \
{ "movshdup", 2, "xm"}, \
{ "movsldup", 1, "=x"}, \
{ "movsldup", 2, "xm"}, \
{ "movss", 1, "=xm,x"}, \
{ "movss", 2, "x,xm"}, \
{ "movsx", 1, "=" r16 "," r32},\
{ "movsx", 2, rm8 "," rm8rm16},\
{ "movupd", 1, "=x,xm"}, \
{ "movupd", 2, "xm,x"}, \
{ "movups", 1, "=x,xm"}, \
{ "movups", 2, "xm,x"}, \
{ "movzx", 1, "=" r16 "," r32},\
{ "movzx", 2, rm8 "," rm8rm16},\
{ "mul", 1, rm8rm16rm32}, \
{ "mulpd", 1, "=x"}, \
{ "mulpd", 2, "xm"}, \
{ "mulps", 1, "=x"}, \
{ "mulps", 2, "xm"}, \
{ "mulsd", 1, "=x"}, \
{ "mulsd", 2, "xm"}, \
{ "mulss", 1, "=x"}, \
{ "mulss", 2, "xm"}, \
{ "neg", 1, "+" rm8rm16rm32}, \
{ "not", 1, "+" rm8rm16rm32}, \
{ "or", 1, "+" rm8 "," rm16 "," rm32 "," r8 "," r16 "," r32},\
{ "or", 2, r8 "i," r16 "i," r32 "i," m8 "," m16 "," m32},\
{ "orpd", 1, "+x"}, \
{ "orpd", 2, "xm"}, \
{ "orps", 1, "+x"}, \
{ "orps", 2, "xm"}, \
{ "out", 1, "id"}, \
{ "out", 2, a8 a16 a32}, \
{ "outs", 1, U("d")}, \
{ "outs", 2, U("m")}, \
{ "packssdw", 1, "+x,y"}, \
{ "packssdw", 2, "xm,ym"}, \
{ "packsswb", 1, "+x,y"}, \
{ "packsswb", 2, "xm,ym"}, \
{ "packuswb", 1, "+x,y"}, \
{ "packuswb", 2, "xm,ym"}, \
{ "paddb", 1, "+x,y"}, \
{ "paddb", 2, "xm,ym"}, \
{ "paddd", 1, "+x,y"}, \
{ "paddd", 2, "xm,ym"}, \
{ "paddq", 1, "+x,y"}, \
{ "paddq", 2, "x,,ym"}, \
{ "paddsb", 1, "+x,y"}, \
{ "paddsb", 2, "xm,ym"}, \
{ "paddsw", 1, "+x,y"}, \
{ "paddsw", 2, "xm,ym"}, \
{ "paddusb", 1, "+x,y"}, \
{ "paddusb", 2, "xm,ym"}, \
{ "paddusw", 1, "+x,y"}, \
{ "paddusw", 2, "xm,ym"}, \
{ "paddw", 1, "+x,y"}, \
{ "paddw", 2, "xm,ym"}, \
{ "pand", 1, "+x,y"}, \
{ "pand", 2, "xm,ym"}, \
{ "pandn", 1, "+x,y"}, \
{ "pandn", 2, "xm,ym"}, \
{ "pavgb", 1, "+x,y"}, \
{ "pavgb", 2, "xm,ym"}, \
{ "pavgw", 1, "+x,y"}, \
{ "pavgw", 2, "xm,ym"}, \
{ "pcmpeqb", 1, "+x,y"}, \
{ "pcmpeqb", 2, "xm,ym"}, \
{ "pcmpeqd", 1, "+x,y"}, \
{ "pcmpeqd", 2, "xm,ym"}, \
{ "pcmpeqw", 1, "+x,y"}, \
{ "pcmpeqw", 2, "xm,ym"}, \
{ "pcmpgtb", 1, "+x,y"}, \
{ "pcmpgtb", 2, "xm,ym"}, \
{ "pcmpgtd", 1, "+x,y"}, \
{ "pcmpgtd", 2, "xm,ym"}, \
{ "pcmpgtw", 1, "+x,y"}, \
{ "pcmpgtw", 2, "xm,ym"}, \
{ "pextrw", 1, "=q"}, \
{ "pextrw", 2, "xy"}, \
{ "pextrw", 3, "i"}, \
{ "pinsrw", 1, "=xy"}, \
{ "pinsrw", 2, "qm"}, \
{ "pinsrw", 3, "i"}, \
{ "pmaddwd", 1, "+x,y"}, \
{ "pmaddwd", 2, "xm,ym"}, \
{ "pmaxsw", 1, "+x,y"}, \
{ "pmaxsw", 2, "xm,ym"}, \
{ "pmaxub", 1, "+x,y"}, \
{ "pmaxub", 2, "xm,ym"}, \
{ "pminsw", 1, "+x,y"}, \
{ "pminsw", 2, "xm,ym"}, \
{ "pminub", 1, "+x,y"}, \
{ "pminub", 2, "xm,ym"}, \
{ "pmovmskb", 1, "+" r32r64}, \
{ "pmovmskb", 2, "xy"}, \
{ "pmulhuw", 1, "+x,y"}, \
{ "pmulhuw", 2, "xm,ym"}, \
{ "pmulhw", 1, "+x,y"}, \
{ "pmulhw", 2, "xm,ym"}, \
{ "pmullw", 1, "+x,y"}, \
{ "pmullw", 2, "xm,ym"}, \
{ "pmuludq", 1, "+x,y"}, \
{ "pmuludq", 2, "xm,ym"}, \
{ "pop", 1, "rm"}, \
{ "por", 1, "+x,y"}, \
{ "por", 2, "xm,ym"}, \
{ "prefetchnta", 1, "m"}, \
{ "prefetcht0", 1, "m"}, \
{ "prefetcht1", 1, "m"}, \
{ "prefetcht2", 1, "m"}, \
{ "psadbw", 1, "+x,y"}, \
{ "psadbw", 2, "xm,ym"}, \
{ "pshufd", 1, "=x"}, \
{ "pshufd", 2, "xm"}, \
{ "pshufd", 3, "i"}, \
{ "pshufhw", 1, "=x"}, \
{ "pshufhw", 2, "xm"}, \
{ "pshufhw", 3, "i"}, \
{ "pshuflw", 1, "=x"}, \
{ "pshuflw", 2, "xm"}, \
{ "pshuflw", 3, "i"}, \
{ "pshufw", 1, "=y"}, \
{ "pshufw", 2, "ym"}, \
{ "pshufw", 3, "i"}, \
{ "pslld", 1, "+x,y"}, \
{ "pslld", 2, "xmi,ymi"}, \
{ "pslldq", 1, "+x"}, \
{ "pslldq", 2, "i"}, \
{ "psllq", 1, "+x,y"}, \
{ "psllq", 2, "xmi,ymi"}, \
{ "psllw", 1, "+x,y"}, \
{ "psllw", 2, "xmi,ymi"}, \
{ "psrad", 1, "+x,y"}, \
{ "psrad", 2, "xmi,ymi"}, \
{ "psraw", 1, "+x,y"}, \
{ "psraw", 2, "xmi,ymi"}, \
{ "psrld", 1, "+x,y"}, \
{ "psrld", 2, "xmi,ymi"}, \
{ "psrldq", 1, "+x"}, \
{ "psrldq", 2, "i"}, \
{ "psrlq", 1, "+x,y"}, \
{ "psrlq", 2, "xmi,ymi"}, \
{ "psrlw", 1, "+x,y"}, \
{ "psrlw", 2, "xmi,ymi"}, \
{ "psubb", 1, "+x,y"}, \
{ "psubb", 2, "xm,ym"}, \
{ "psubd", 1, "+x,y"}, \
{ "psubd", 2, "xm,ym"}, \
{ "psubq", 1, "+x,y"}, \
{ "psubq", 2, "xm,ym"}, \
{ "psubsb", 1, "+x,y"}, \
{ "psubsb", 2, "xm,ym"}, \
{ "psubsw", 1, "+x,y"}, \
{ "psubsw", 2, "xm,ym"}, \
{ "psubusb", 1, "+x,y"}, \
{ "psubusb", 2, "xm,ym"}, \
{ "psubusw", 1, "+x,y"}, \
{ "psubusw", 2, "xm,ym"}, \
{ "psubw", 1, "+x,y"}, \
{ "psubw", 2, "xm,ym"}, \
{ "punpckhbw", 1, "+x,y"}, \
{ "punpckhbw", 2, "xm,ym"}, \
{ "punpckhdq", 1, "+x,y"}, \
{ "punpckhdq", 2, "xm,ym"}, \
{ "punpckhqdq", 1, "+x"}, \
{ "punpckhqdq", 2, "xm"}, \
{ "punpckhwd", 1, "+x,y"}, \
{ "punpckhwd", 2, "xm,ym"}, \
{ "punpcklbw", 1, "+x,y"}, \
{ "punpcklbw", 2, "xm,ym"}, \
{ "punpckldq", 1, "+x,y"}, \
{ "punpckldq", 2, "xm,ym"}, \
{ "punpcklqdq", 1, "+x"}, \
{ "punpcklqdq", 2, "xm"}, \
{ "punpcklwd", 1, "+x,y"}, \
{ "punpcklwd", 2, "xm,ym"}, \
{ "push", 1, "rmi"}, \
{ "pxor", 1, "+x,y"}, \
{ "pxor", 2, "xm,ym"}, \
{ "rcl", 1, "+" rm8rm16rm32}, \
{ "rcl", 2, "ic"}, \
{ "rcpps", 1, "+x"}, \
{ "rcpps", 2, "xm"}, \
{ "rcpss", 1, "+x"}, \
{ "rcpss", 2, "xm"}, \
{ "rcr", 1, "+" rm8rm16rm32}, \
{ "rcr", 2, "ic"}, \
{ "ret", 1, "i"}, \
{ "rol", 1, "+" rm8rm16rm32}, \
{ "rol", 2, "ic"}, \
{ "ror", 1, "+" rm8rm16rm32}, \
{ "ror", 2, "ic"}, \
{ "rsqrtps", 1, "=x"}, \
{ "rsqrtps", 2, "xm"}, \
{ "rsqrtss", 1, "=x"}, \
{ "rsqrtss", 2, "xm"}, \
{ "sal", 1, "+" rm8rm16rm32}, \
{ "sal", 2, "ic"}, \
{ "sar", 1, "+" rm8rm16rm32}, \
{ "sar", 2, "ic"}, \
{ "sbb", 1, "+" rm8 "," rm16 "," rm32 "," r8 "," r16 "," r32},\
{ "sbb", 2, ri8 "," ri16 "," ri32 "," m8 "," m16 "," m32},\
{ "scas", 1, U("m")}, \
{ "seta", 1, "=qm"}, \
{ "setae", 1, "=qm"}, \
{ "setb", 1, "=qm"}, \
{ "setbe", 1, "=qm"}, \
{ "setc", 1, "=qm"}, \
{ "sete", 1, "=qm"}, \
{ "setg", 1, "=qm"}, \
{ "setge", 1, "=qm"}, \
{ "setl", 1, "=qm"}, \
{ "setle", 1, "=qm"}, \
{ "setna", 1, "=qm"}, \
{ "setnae", 1, "=qm"}, \
{ "setnb", 1, "=qm"}, \
{ "setnbe", 1, "=qm"}, \
{ "setnc", 1, "=qm"}, \
{ "setne", 1, "=qm"}, \
{ "setng", 1, "=qm"}, \
{ "setnge", 1, "=qm"}, \
{ "setnl", 1, "=qm"}, \
{ "setnle", 1, "=qm"}, \
{ "setno", 1, "=qm"}, \
{ "setnp", 1, "=qm"}, \
{ "setns", 1, "=qm"}, \
{ "setnz", 1, "=qm"}, \
{ "seto", 1, "=qm"}, \
{ "setp", 1, "=qm"}, \
{ "setpe", 1, "=qm"}, \
{ "setpo", 1, "=qm"}, \
{ "sets", 1, "=qm"}, \
{ "setz", 1, "=qm"}, \
{ "sgdt", 1, "=m"}, \
{ "shl", 1, "+" rm8rm16rm32}, \
{ "shl", 2, "ic"}, \
{ "shld", 1, "+" rm16 "," rm16},\
{ "shld", 2, r16 "," r32}, \
{ "shld", 3, "ic"}, \
{ "shr", 1, "+" rm8rm16rm32}, \
{ "shr", 2, "ic"}, \
{ "shrd", 1, "+" rm16 "," rm32},\
{ "shrd", 2, r16 "," r32}, \
{ "shrd", 3, "ic"}, \
{ "shufpd", 1, "+x"}, \
{ "shufpd", 2, "xm"}, \
{ "shufpd", 3, "i"}, \
{ "shufps", 1, "+x"}, \
{ "shufps", 2, "xm"}, \
{ "shufps", 3, "i"}, \
{ "sidt", 1, "=m"}, \
{ "sldt", 1, "=q" S("2") "m"},\
{ "smsw", 1, "=q" S("2") "m"},\
{ "sqrtpd", 1, "=x"}, \
{ "sqrtpd", 2, "xm"}, \
{ "sqrtps", 1, "=x"}, \
{ "sqrtps", 2, "xm"}, \
{ "sqrtsd", 1, "=x"}, \
{ "sqrtsd", 2, "xm"}, \
{ "sqrtss", 1, "=x"}, \
{ "sqrtss", 2, "xm"}, \
{ "stmxcsr", 1, "m"}, \
{ "stos", 1, U("=m")}, \
{ "str", 1, "=q" S("2") "m"},\
{ "sub", 1, "=rm,r"}, \
{ "sub", 2, "ir,m"}, \
{ "subpd", 1, "+x"}, \
{ "subpd", 2, "xm"}, \
{ "subps", 1, "+x"}, \
{ "subps", 2, "xm"}, \
{ "subsd", 1, "+x"}, \
{ "subsd", 2, "xm"}, \
{ "subss", 1, "+x"}, \
{ "subss", 2, "xm"}, \
{ "test", 1, "+r," rm8rm16rm32},\
{ "test", 2, "r,i"}, \
{ "ucomisd", 1, "+x"}, \
{ "ucomisd", 2, "xm"}, \
{ "ucomiss", 1, "+x"}, \
{ "ucomiss", 2, "xm"}, \
{ "unpckhpd", 1, "+x"}, \
{ "unpckhpd", 2, "xm"}, \
{ "unpckhps", 1, "+x"}, \
{ "unpckhps", 2, "xm"}, \
{ "unpcklpd", 1, "+x"}, \
{ "unpcklpd", 2, "xm"}, \
{ "unpcklps", 1, "+x"}, \
{ "unpcklps", 2, "xm"}, \
{ "verr", 1, rm16}, \
{ "verw", 1, rm16}, \
{ "xadd", 1, "+" rm8 "," rm16 "," rm32},\
{ "xadd", 2, r8 "," r16 "," r32},\
{ "xchg", 1, "+rm,r"}, \
{ "xchg", 2, "&r,m"}, \
{ "xlat", 1, U("m")}, \
{ "xor", 1, "+rm,r"}, \
{ "xor", 2, "ri,m"}, \
{ "xorpd", 1, "+x"}, \
{ "xorpd", 2, "xm"}, \
{ "xorps", 1, "+x"}, \
{ "xorps", 2, "xm"},