(include "simplify.inc")
(define-arch
(name m32r) (comment "Renesas M32R")
(default-alignment aligned)
(insn-lsb0? #f)
(machs m32r m32rx m32r2)
(isas m32r)
)
(define-attr
(for insn)
(type enum)
(name PIPE)
(comment "parallel execution pipeline selection")
(values NONE O S OS O_OS)
)
(define-attr
(for insn)
(type enum)
(name PARALLEL)
(attrs META) (values NO YES)
(default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES)))
)
(define-isa
(name m32r)
(default-insn-bitsize 32)
(base-insn-bitsize 32)
(default-insn-word-bitsize 32)
(liw-insns 2)
(parallel-insns 2)
(decode-assist (0 1 2 3 8 9 10 11))
(insn-types (long 31 (eq-attr (current-insn) LENGTH 31) (0 1 2 7 8 9 10) )
(short
15
(eq-attr (current-insn) LENGTH 15) (0 1 2 7 8 9 10)
)
)
(frame long32 ((long)) "$0" (+ (1 1) (31 $0)) (sequence () (execute $0)) )
(frame serial2x16
((short)
(short))
"$0 -> $1"
(+ (1 0) (15 $0) (1 0) (15 $1))
(sequence ()
(execute $0)
(execute $1))
)
(frame parallel2x16
((short (eq-attr (current-insn) PIPE "O,BOTH"))
(short (eq-attr (current-insn) PIPE "S,BOTH")))
"$0 || $1"
(+ (1 0) (15 $0) (1 1) (15 $1))
(parallel ()
(execute $0)
(execute $1))
)
)
(define-cpu
(name m32rbf)
(comment "Renesas M32R base family")
(endian either)
(word-bitsize 32)
(parallel-insns 1)
)
(define-cpu
(name m32rxf)
(comment "Renesas M32Rx family")
(endian either)
(word-bitsize 32)
(file-transform "x")
)
(define-cpu
(name m32r2f)
(comment "Renesas M32R2 family")
(endian either)
(word-bitsize 32)
(file-transform "2")
)
(define-mach
(name m32r)
(comment "Generic M32R cpu")
(cpu m32rbf)
)
(define-mach
(name m32rx)
(comment "M32RX cpu")
(cpu m32rxf)
)
(define-mach
(name m32r2)
(comment "M32R2 cpu")
(cpu m32r2f)
)
(define-model
(name m32r/d) (comment "m32r/d") (attrs)
(mach m32r)
(pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))
(pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
(state
(h-gr UINT)
)
(unit u-exec "Execution Unit" ()
1 1 () ((sr INT -1) (dr INT -1)) ((dr INT -1)) () )
(unit u-cmp "Compare Unit" ()
1 1 () ((src1 INT -1) (src2 INT -1)) () () )
(unit u-mac "Multiply/Accumulate Unit" ()
1 1 () ((src1 INT -1) (src2 INT -1)) () () )
(unit u-cti "Branch Unit" ()
1 1 () ((sr INT -1)) ((pc)) () )
(unit u-load "Memory Load Unit" ()
1 1 () ((sr INT)
) ((dr INT)) () )
(unit u-store "Memory Store Unit" ()
1 1 () ((src1 INT) (src2 INT)) () () )
)
(define-model
(name test) (comment "test") (attrs)
(mach m32r)
(pipeline all "" () ((fetch) (decode) (execute) (writeback)))
(unit u-exec "Execution Unit" ()
1 1 () () () ())
)
(define-model
(name m32rx) (comment "m32rx") (attrs)
(mach m32rx)
(pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
(pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
(pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
(unit u-exec "Execution Unit" ()
1 1 () ((sr INT -1) (dr INT -1)) ((dr INT -1)) () )
(unit u-cmp "Compare Unit" ()
1 1 () ((src1 INT -1) (src2 INT -1)) () () )
(unit u-mac "Multiply/Accumulate Unit" ()
1 1 () ((src1 INT -1) (src2 INT -1)) () () )
(unit u-cti "Branch Unit" ()
1 1 () ((sr INT -1)) ((pc)) () )
(unit u-load "Memory Load Unit" ()
1 1 () ((sr INT)) ((dr INT)) () )
(unit u-store "Memory Store Unit" ()
1 1 () ((src1 INT) (src2 INT)) () () )
)
(define-model
(name m32r2) (comment "m32r2") (attrs)
(mach m32r2)
(pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
(pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
(pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
(unit u-exec "Execution Unit" ()
1 1 () ((sr INT -1) (dr INT -1)) ((dr INT -1)) () )
(unit u-cmp "Compare Unit" ()
1 1 () ((src1 INT -1) (src2 INT -1)) () () )
(unit u-mac "Multiply/Accumulate Unit" ()
1 1 () ((src1 INT -1) (src2 INT -1)) () () )
(unit u-cti "Branch Unit" ()
1 1 () ((sr INT -1)) ((pc)) () )
(unit u-load "Memory Load Unit" ()
1 1 () ((sr INT)) ((dr INT)) () )
(unit u-store "Memory Store Unit" ()
1 1 () ((src1 INT) (src2 INT)) () () )
)
(define-attr
(for ifield operand)
(type boolean)
(name RELOC)
(comment "there is a reloc associated with this field (experiment)")
)
(dnf f-op1 "op1" () 0 4)
(dnf f-op2 "op2" () 8 4)
(dnf f-cond "cond" () 4 4)
(dnf f-r1 "r1" () 4 4)
(dnf f-r2 "r2" () 12 4)
(df f-simm8 "simm8" () 8 8 INT #f #f)
(df f-simm16 "simm16" () 16 16 INT #f #f)
(dnf f-shift-op2 "shift op2" () 8 3)
(dnf f-uimm3 "uimm3" () 5 3)
(dnf f-uimm4 "uimm4" () 12 4)
(dnf f-uimm5 "uimm5" () 11 5)
(dnf f-uimm8 "uimm8" () 8 8)
(dnf f-uimm16 "uimm16" () 16 16)
(dnf f-uimm24 "uimm24" (ABS-ADDR RELOC) 8 24)
(dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16)
(df f-disp8 "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT
((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))
((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4)))))
(df f-disp16 "disp16" (PCREL-ADDR RELOC) 16 16 INT
((value pc) (sra WI (sub WI value pc) (const 2)))
((value pc) (add WI (sll WI value (const 2)) pc)))
(df f-disp24 "disp24" (PCREL-ADDR RELOC) 8 24 INT
((value pc) (sra WI (sub WI value pc) (const 2)))
((value pc) (add WI (sll WI value (const 2)) pc)))
(dnf f-op23 "op2.3" () 9 3)
(dnf f-op3 "op3" () 14 2)
(dnf f-acc "acc" () 8 1)
(dnf f-accs "accs" () 12 2)
(dnf f-accd "accd" () 4 2)
(dnf f-bits67 "bits67" () 6 2)
(dnf f-bit4 "bit4" () 4 1)
(dnf f-bit14 "bit14" () 14 1)
(define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")
(attrs)
(start 15) (length 1)
(encode (value pc) (sub WI value (const WI 1)))
(decode (value pc) (add WI value (const WI 1)))
)
(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
("0" "1" "2" "3" "4" "5" "6" "7"
"8" "9" "10" "11" "12" "13" "14" "15")
)
(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
("0" "1" "2" "3" "4" "5" "6" "7"
"8" "9" "10" "11" "12" "13" "14" "15")
)
(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
(dnh h-hi16 "high 16 bits" ()
(immediate (UINT 16))
() () ()
)
(dnh h-slo16 "signed low 16 bits" ()
(immediate (INT 16))
() () ()
)
(dnh h-ulo16 "unsigned low 16 bits" ()
(immediate (UINT 16))
() () ()
)
(define-keyword
(name gr-names)
(print-name h-gr)
(prefix "")
(values (fp 13) (lr 14) (sp 15)
(r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
(r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
)
(define-hardware
(name h-gr)
(comment "general registers")
(attrs PROFILE CACHE-ADDR)
(type register WI (16))
(indices extern-keyword gr-names)
)
(define-keyword
(name cr-names)
(print-name h-cr)
(prefix "")
(values (psw 0) (cbr 1) (spi 2) (spu 3)
(bpc 6) (bbpsw 8) (bbpc 14) (evb 5)
(cr0 0) (cr1 1) (cr2 2) (cr3 3)
(cr4 4) (cr5 5) (cr6 6) (cr7 7)
(cr8 8) (cr9 9) (cr10 10) (cr11 11)
(cr12 12) (cr13 13) (cr14 14) (cr15 15))
)
(define-hardware
(name h-cr)
(comment "control registers")
(type register UWI (16))
(indices extern-keyword cr-names)
(get (index) (c-call UWI "@cpu@_h_cr_get_handler" index))
(set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval))
)
(define-hardware
(name h-accum)
(comment "accumulator")
(type register DI)
(get () (c-call DI "@cpu@_h_accum_get_handler"))
(set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval))
)
(define-hardware
(name h-accums)
(comment "accumulators")
(attrs (MACH m32rx,m32r2))
(type register DI (2))
(indices keyword "" ((a0 0) (a1 1)))
(get (index) (c-call DI "@cpu@_h_accums_get_handler" index))
(set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval))
)
(dsh h-cond "condition bit" () (register BI))
(define-hardware
(name h-psw)
(comment "psw part of psw")
(type register UQI)
(get () (c-call UQI "@cpu@_h_psw_get_handler"))
(set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval))
)
(dsh h-bpsw "backup psw" () (register UQI))
(dsh h-bbpsw "backup bpsw" () (register UQI))
(dsh h-lock "lock" () (register BI))
(define-attr
(for operand)
(type boolean)
(name HASH-PREFIX)
(comment "immediates have an optional '#' prefix")
)
(dnop sr "source register" () h-gr f-r2)
(dnop dr "destination register" () h-gr f-r1)
(dnop src1 "source register 1" () h-gr f-r1)
(dnop src2 "source register 2" () h-gr f-r2)
(dnop scr "source control register" () h-cr f-r2)
(dnop dcr "destination control register" () h-cr f-r1)
(dnop simm8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-simm8)
(dnop simm16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-simm16)
(dnop uimm3 "3 bit unsigned number" (HASH-PREFIX) h-uint f-uimm3)
(dnop uimm4 "4 bit trap number" (HASH-PREFIX) h-uint f-uimm4)
(dnop uimm5 "5 bit shift count" (HASH-PREFIX) h-uint f-uimm5)
(dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8)
(dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16)
(dnop imm1 "1 bit immediate" ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1)
(dnop accd "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd)
(dnop accs "accumulator source register" ((MACH m32rx,m32r2)) h-accums f-accs)
(dnop acc "accumulator reg (d)" ((MACH m32rx,m32r2)) h-accums f-acc)
(define-operand (name hash) (comment "# prefix") (attrs)
(type h-sint) (index f-nil)
(handlers (parse "hash") (print "hash"))
)
(define-operand
(name hi16)
(comment "high 16 bit immediate, sign optional")
(attrs)
(type h-hi16)
(index f-hi16)
(handlers (parse "hi16"))
)
(define-operand
(name slo16)
(comment "16 bit signed immediate, for low()")
(attrs)
(type h-slo16)
(index f-simm16)
(handlers (parse "slo16"))
)
(define-operand
(name ulo16)
(comment "16 bit unsigned immediate, for low()")
(attrs)
(type h-ulo16)
(index f-uimm16)
(handlers (parse "ulo16"))
)
(dnop uimm24 "24 bit address" (HASH-PREFIX) h-addr f-uimm24)
(define-operand
(name disp8)
(comment "8 bit displacement")
(attrs RELAX)
(type h-iaddr)
(index f-disp8)
)
(dnop disp16 "16 bit displacement" () h-iaddr f-disp16)
(dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24)
(dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)
(dnop accum "accumulator" (SEM-ONLY) h-accum f-nil)
(define-attr
(for insn)
(type boolean)
(name FILL-SLOT)
(comment "fill right bin with `nop' if insn is in left bin")
)
(define-attr
(for insn)
(type boolean)
(name SPECIAL)
(comment "non-public m32rx insn")
)
(define-attr
(for insn)
(type boolean)
(name SPECIAL_M32R)
(comment "non-public m32r insn")
)
(define-attr
(for insn)
(type boolean)
(name SPECIAL_FLOAT)
(comment "floating point insn")
)
(define-attr
(for insn)
(type enum)
(name IDOC)
(comment "insn kind for documentation")
(attrs META)
(values
(MEM - () "Memory")
(ALU - () "ALU")
(BR - () "Branch")
(ACCUM - () "Accumulator")
(MAC - () "Multiply/Accumulate")
(MISC - () "Miscellaneous")
)
)
(define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm)
(begin
(dni mnemonic
(.str mnemonic " reg/reg")
((PIPE OS) (IDOC ALU))
(.str mnemonic " $dr,$sr")
(+ OP1_0 op2-op dr sr)
(set dr (sem-op dr sr))
()
)
(dni (.sym mnemonic "3")
(.str mnemonic " reg/" imm)
((IDOC ALU))
(.str mnemonic "3 $dr,$sr," imm-prefix "$" imm)
(+ OP1_8 op2-op dr sr imm)
(set dr (sem-op sr imm))
()
)
)
)
(bin-op add OP2_10 add "$hash" slo16)
(bin-op and OP2_12 and "" uimm16)
(bin-op or OP2_14 or "$hash" ulo16)
(bin-op xor OP2_13 xor "" uimm16)
(dni addi "addi"
((PIPE OS) (IDOC ALU))
"addi $dr,$simm8"
(+ OP1_4 dr simm8)
(set dr (add dr simm8))
((m32r/d (unit u-exec))
(m32rx (unit u-exec))
(m32r2 (unit u-exec)))
)
(dni addv "addv"
((PIPE OS) (IDOC ALU))
"addv $dr,$sr"
(+ OP1_0 OP2_8 dr sr)
(parallel ()
(set dr (add dr sr))
(set condbit (add-oflag dr sr (const 0))))
()
)
(dni addv3 "addv3"
((IDOC ALU))
"addv3 $dr,$sr,$simm16"
(+ OP1_8 OP2_8 dr sr simm16)
(parallel ()
(set dr (add sr simm16))
(set condbit (add-oflag sr simm16 (const 0))))
()
)
(dni addx "addx"
((PIPE OS) (IDOC ALU))
"addx $dr,$sr"
(+ OP1_0 OP2_9 dr sr)
(parallel ()
(set dr (addc dr sr condbit))
(set condbit (add-cflag dr sr condbit)))
()
)
(dni bc8 "bc with 8 bit displacement"
(COND-CTI (PIPE O) (IDOC BR))
"bc.s $disp8"
(+ OP1_7 (f-r1 12) disp8)
(if condbit (set pc disp8))
((m32r/d (unit u-cti))
(m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bc8r "relaxable bc8"
(COND-CTI RELAXABLE (PIPE O) (IDOC BR))
"bc $disp8"
(emit bc8 disp8)
)
(dni bc24 "bc with 24 bit displacement"
(COND-CTI (IDOC BR))
"bc.l $disp24"
(+ OP1_15 (f-r1 12) disp24)
(if condbit (set pc disp24))
((m32r/d (unit u-cti))
(m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bc24r "relaxable bc24"
(COND-CTI RELAXED (IDOC BR))
"bc $disp24"
(emit bc24 disp24)
)
(dni beq "beq"
(COND-CTI (IDOC BR))
"beq $src1,$src2,$disp16"
(+ OP1_11 OP2_0 src1 src2 disp16)
(if (eq src1 src2) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
(m32rx (unit u-cti) (unit u-cmp (cycles 0)))
(m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
)
(define-pmacro (cbranch sym comment op2-op comp-op)
(dni sym comment (COND-CTI (IDOC BR))
(.str sym " $src2,$disp16")
(+ OP1_11 op2-op (f-r1 0) src2 disp16)
(if (comp-op src2 (const WI 0)) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
(m32rx (unit u-cti) (unit u-cmp (cycles 0)))
(m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
)
)
(cbranch beqz "beqz" OP2_8 eq)
(cbranch bgez "bgez" OP2_11 ge)
(cbranch bgtz "bgtz" OP2_13 gt)
(cbranch blez "blez" OP2_12 le)
(cbranch bltz "bltz" OP2_10 lt)
(cbranch bnez "bnez" OP2_9 ne)
(dni bl8 "bl with 8 bit displacement"
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
"bl.s $disp8"
(+ OP1_7 (f-r1 14) disp8)
(sequence ()
(set (reg h-gr 14)
(add (and pc (const -4)) (const 4)))
(set pc disp8))
((m32r/d (unit u-cti))
(m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bl8r "relaxable bl8"
(UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
"bl $disp8"
(emit bl8 disp8)
)
(dni bl24 "bl with 24 bit displacement"
(UNCOND-CTI (IDOC BR))
"bl.l $disp24"
(+ OP1_15 (f-r1 14) disp24)
(sequence ()
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24))
((m32r/d (unit u-cti))
(m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bl24r "relaxable bl24"
(UNCOND-CTI RELAXED (IDOC BR))
"bl $disp24"
(emit bl24 disp24)
)
(dni bcl8 "bcl with 8 bit displacement"
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
"bcl.s $disp8"
(+ OP1_7 (f-r1 8) disp8)
(if condbit
(sequence ()
(set (reg h-gr 14)
(add (and pc (const -4))
(const 4)))
(set pc disp8)))
((m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bcl8r "relaxable bcl8"
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
"bcl $disp8"
(emit bcl8 disp8)
)
(dni bcl24 "bcl with 24 bit displacement"
(COND-CTI (MACH m32rx,m32r2) (IDOC BR))
"bcl.l $disp24"
(+ OP1_15 (f-r1 8) disp24)
(if condbit
(sequence ()
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24)))
((m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bcl24r "relaxable bcl24"
(COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
"bcl $disp24"
(emit bcl24 disp24)
)
(dni bnc8 "bnc with 8 bit displacement"
(COND-CTI (PIPE O) (IDOC BR))
"bnc.s $disp8"
(+ OP1_7 (f-r1 13) disp8)
(if (not condbit) (set pc disp8))
((m32r/d (unit u-cti))
(m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bnc8r "relaxable bnc8"
(COND-CTI RELAXABLE (PIPE O) (IDOC BR))
"bnc $disp8"
(emit bnc8 disp8)
)
(dni bnc24 "bnc with 24 bit displacement"
(COND-CTI (IDOC BR))
"bnc.l $disp24"
(+ OP1_15 (f-r1 13) disp24)
(if (not condbit) (set pc disp24))
((m32r/d (unit u-cti))
(m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bnc24r "relaxable bnc24"
(COND-CTI RELAXED (IDOC BR))
"bnc $disp24"
(emit bnc24 disp24)
)
(dni bne "bne"
(COND-CTI (IDOC BR))
"bne $src1,$src2,$disp16"
(+ OP1_11 OP2_1 src1 src2 disp16)
(if (ne src1 src2) (set pc disp16))
((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
(m32rx (unit u-cti) (unit u-cmp (cycles 0)))
(m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
)
(dni bra8 "bra with 8 bit displacement"
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
"bra.s $disp8"
(+ OP1_7 (f-r1 15) disp8)
(set pc disp8)
((m32r/d (unit u-cti))
(m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bra8r "relaxable bra8"
(UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
"bra $disp8"
(emit bra8 disp8)
)
(dni bra24 "bra with 24 displacement"
(UNCOND-CTI (IDOC BR))
"bra.l $disp24"
(+ OP1_15 (f-r1 15) disp24)
(set pc disp24)
((m32r/d (unit u-cti))
(m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bra24r "relaxable bra24"
(UNCOND-CTI RELAXED (IDOC BR))
"bra $disp24"
(emit bra24 disp24)
)
(dni bncl8 "bncl with 8 bit displacement"
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
"bncl.s $disp8"
(+ OP1_7 (f-r1 9) disp8)
(if (not condbit)
(sequence ()
(set (reg h-gr 14)
(add (and pc (const -4))
(const 4)))
(set pc disp8)))
((m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bncl8r "relaxable bncl8"
(COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
"bncl $disp8"
(emit bncl8 disp8)
)
(dni bncl24 "bncl with 24 bit displacement"
(COND-CTI (MACH m32rx,m32r2) (IDOC BR))
"bncl.l $disp24"
(+ OP1_15 (f-r1 9) disp24)
(if (not condbit)
(sequence ()
(set (reg h-gr 14) (add pc (const 4)))
(set pc disp24)))
((m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dnmi bncl24r "relaxable bncl24"
(COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
"bncl $disp24"
(emit bncl24 disp24)
)
(dni cmp "cmp"
((PIPE OS) (IDOC ALU))
"cmp $src1,$src2"
(+ OP1_0 OP2_4 src1 src2)
(set condbit (lt src1 src2))
((m32r/d (unit u-cmp))
(m32rx (unit u-cmp))
(m32r2 (unit u-cmp)))
)
(dni cmpi "cmpi"
((IDOC ALU))
"cmpi $src2,$simm16"
(+ OP1_8 (f-r1 0) OP2_4 src2 simm16)
(set condbit (lt src2 simm16))
((m32r/d (unit u-cmp))
(m32rx (unit u-cmp))
(m32r2 (unit u-cmp)))
)
(dni cmpu "cmpu"
((PIPE OS) (IDOC ALU))
"cmpu $src1,$src2"
(+ OP1_0 OP2_5 src1 src2)
(set condbit (ltu src1 src2))
((m32r/d (unit u-cmp))
(m32rx (unit u-cmp))
(m32r2 (unit u-cmp)))
)
(dni cmpui "cmpui"
((IDOC ALU))
"cmpui $src2,$simm16"
(+ OP1_8 (f-r1 0) OP2_5 src2 simm16)
(set condbit (ltu src2 simm16))
((m32r/d (unit u-cmp))
(m32rx (unit u-cmp))
(m32r2 (unit u-cmp)))
)
(dni cmpeq "cmpeq"
((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
"cmpeq $src1,$src2"
(+ OP1_0 OP2_6 src1 src2)
(set condbit (eq src1 src2))
((m32rx (unit u-cmp))
(m32r2 (unit u-cmp)))
)
(dni cmpz "cmpz"
((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
"cmpz $src2"
(+ OP1_0 OP2_7 (f-r1 0) src2)
(set condbit (eq src2 (const 0)))
((m32rx (unit u-cmp))
(m32r2 (unit u-cmp)))
)
(dni div "div"
((IDOC ALU))
"div $dr,$sr"
(+ OP1_9 OP2_0 dr sr (f-simm16 0))
(if (ne sr (const 0)) (set dr (div dr sr)))
((m32r/d (unit u-exec (cycles 37)))
(m32rx (unit u-exec (cycles 37)))
(m32r2 (unit u-exec (cycles 37))))
)
(dni divu "divu"
((IDOC ALU))
"divu $dr,$sr"
(+ OP1_9 OP2_1 dr sr (f-simm16 0))
(if (ne sr (const 0)) (set dr (udiv dr sr)))
((m32r/d (unit u-exec (cycles 37)))
(m32rx (unit u-exec (cycles 37)))
(m32r2 (unit u-exec (cycles 37))))
)
(dni rem "rem"
((IDOC ALU))
"rem $dr,$sr"
(+ OP1_9 OP2_2 dr sr (f-simm16 0))
(if (ne sr (const 0)) (set dr (mod dr sr)))
((m32r/d (unit u-exec (cycles 37)))
(m32rx (unit u-exec (cycles 37)))
(m32r2 (unit u-exec (cycles 37))))
)
(dni remu "remu"
((IDOC ALU))
"remu $dr,$sr"
(+ OP1_9 OP2_3 dr sr (f-simm16 0))
(if (ne sr (const 0)) (set dr (umod dr sr)))
((m32r/d (unit u-exec (cycles 37)))
(m32rx (unit u-exec (cycles 37)))
(m32r2 (unit u-exec (cycles 37))))
)
(dni remh "remh"
((MACH m32r2))
"remh $dr,$sr"
(+ OP1_9 OP2_2 dr sr (f-simm16 #x10))
(if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr)))
((m32r2 (unit u-exec (cycles 21))))
)
(dni remuh "remuh"
((MACH m32r2))
"remuh $dr,$sr"
(+ OP1_9 OP2_3 dr sr (f-simm16 #x10))
(if (ne sr (const 0)) (set dr (umod dr sr)))
((m32r2 (unit u-exec (cycles 21))))
)
(dni remb "remb"
((MACH m32r2))
"remb $dr,$sr"
(+ OP1_9 OP2_2 dr sr (f-simm16 #x18))
(if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr)))
((m32r2 (unit u-exec (cycles 21))))
)
(dni remub "remub"
((MACH m32r2))
"remub $dr,$sr"
(+ OP1_9 OP2_3 dr sr (f-simm16 #x18))
(if (ne sr (const 0)) (set dr (umod dr sr)))
((m32r2 (unit u-exec (cycles 21))))
)
(dni divuh "divuh"
((MACH m32r2))
"divuh $dr,$sr"
(+ OP1_9 OP2_1 dr sr (f-simm16 #x10))
(if (ne sr (const 0)) (set dr (udiv dr sr)))
((m32r2 (unit u-exec (cycles 21))))
)
(dni divb "divb"
((MACH m32r2))
"divb $dr,$sr"
(+ OP1_9 OP2_0 dr sr (f-simm16 #x18))
(if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr)))
((m32r2 (unit u-exec (cycles 21))))
)
(dni divub "divub"
((MACH m32r2))
"divub $dr,$sr"
(+ OP1_9 OP2_1 dr sr (f-simm16 #x18))
(if (ne sr (const 0)) (set dr (udiv dr sr)))
((m32r2 (unit u-exec (cycles 21))))
)
(dni divh "divh"
((MACH m32rx,m32r2) (IDOC ALU))
"divh $dr,$sr"
(+ OP1_9 OP2_0 dr sr (f-simm16 #x10))
(if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))
((m32rx (unit u-exec (cycles 21)))
(m32r2 (unit u-exec (cycles 21))))
)
(dni jc "jc"
(COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"jc $sr"
(+ OP1_1 (f-r1 12) OP2_12 sr)
(if condbit (set pc (and sr (const -4))))
((m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dni jnc "jnc"
(COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"jnc $sr"
(+ OP1_1 (f-r1 13) OP2_12 sr)
(if (not condbit) (set pc (and sr (const -4))))
((m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dni jl "jl"
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
"jl $sr"
(+ OP1_1 (f-r1 14) OP2_12 sr)
(parallel ()
(set (reg h-gr 14)
(add (and pc (const -4)) (const 4)))
(set pc (and sr (const -4))))
((m32r/d (unit u-cti))
(m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(dni jmp "jmp"
(UNCOND-CTI (PIPE O) (IDOC BR))
"jmp $sr"
(+ OP1_1 (f-r1 15) OP2_12 sr)
(set pc (and sr (const -4)))
((m32r/d (unit u-cti))
(m32rx (unit u-cti))
(m32r2 (unit u-cti)))
)
(define-pmacro (no-ext-expr mode expr) expr)
(define-pmacro (ext-expr mode expr) (ext mode expr))
(define-pmacro (zext-expr mode expr) (zext mode expr))
(define-pmacro (load-op suffix op2-op mode ext-op)
(begin
(dni (.sym ld suffix) (.str "ld" suffix)
((PIPE O) (IDOC MEM))
(.str "ld" suffix " $dr,@$sr")
(+ OP1_2 op2-op dr sr)
(set dr (ext-op WI (mem mode sr)))
((m32r/d (unit u-load))
(m32rx (unit u-load))
(m32r2 (unit u-load)))
)
(dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")
(NO-DIS (PIPE O) (IDOC MEM))
(.str "ld" suffix " $dr,@($sr)")
(emit (.sym ld suffix) dr sr))
(dni (.sym ld suffix -d) (.str "ld" suffix "-d")
((IDOC MEM))
(.str "ld" suffix " $dr,@($slo16,$sr)")
(+ OP1_10 op2-op dr sr slo16)
(set dr (ext-op WI (mem mode (add sr slo16))))
((m32r/d (unit u-load (cycles 2)))
(m32rx (unit u-load (cycles 2)))
(m32r2 (unit u-load (cycles 2))))
)
(dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")
(NO-DIS (IDOC MEM))
(.str "ld" suffix " $dr,@($sr,$slo16)")
(emit (.sym ld suffix -d) dr sr slo16))
)
)
(load-op "" OP2_12 WI no-ext-expr)
(load-op b OP2_8 QI ext-expr)
(load-op h OP2_10 HI ext-expr)
(load-op ub OP2_9 QI zext-expr)
(load-op uh OP2_11 HI zext-expr)
(dni ld-plus "ld+"
((PIPE O) (IDOC MEM))
"ld $dr,@$sr+"
(+ OP1_2 dr OP2_14 sr)
(parallel ()
(set dr (mem WI sr))
(set sr (add sr (const 4))))
((m32r/d (unit u-load (pred (const 1)))
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
(m32rx (unit u-load)
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
(m32r2 (unit u-load)
(unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
)
)
(dnmi pop "pop"
((PIPE O) (IDOC MEM))
"pop $dr"
(emit ld-plus dr (sr 15)) )
(dni ld24 "ld24"
((IDOC MEM))
"ld24 $dr,$uimm24"
(+ OP1_14 dr uimm24)
(set dr uimm24)
()
)
(dni ldi8 "ldi8"
((PIPE OS) (IDOC ALU))
"ldi8 $dr,$simm8"
(+ OP1_6 dr simm8)
(set dr simm8)
()
)
(dnmi ldi8a "ldi8 alias"
((PIPE OS) (IDOC ALU))
"ldi $dr,$simm8"
(emit ldi8 dr simm8)
)
(dni ldi16 "ldi16"
((IDOC ALU))
"ldi16 $dr,$hash$slo16"
(+ OP1_9 OP2_15 (f-r2 0) dr slo16)
(set dr slo16)
()
)
(dnmi ldi16a "ldi16 alias"
((IDOC ALU))
"ldi $dr,$hash$slo16"
(emit ldi16 dr slo16)
)
(dni lock "lock"
((PIPE O) (IDOC MISC))
"lock $dr,@$sr"
(+ OP1_2 OP2_13 dr sr)
(sequence ()
(set (reg h-lock) (const BI 1))
(set dr (mem WI sr)))
((m32r/d (unit u-load))
(m32rx (unit u-load))
(m32r2 (unit u-load)))
)
(dni machi "machi"
(
(MACH m32r) (PIPE S) (IDOC MAC)
)
"machi $src1,$src2"
(+ OP1_3 OP2_4 src1 src2)
(set accum
(sra DI
(sll DI
(add DI
accum
(mul DI
(ext DI (and WI src1 (const #xffff0000)))
(ext DI (trunc HI (sra WI src2 (const 16))))))
(const 8))
(const 8)))
((m32r/d (unit u-mac)))
)
(dni machi-a "machi-a"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"machi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 4) src2)
(set acc
(sra DI
(sll DI
(add DI
acc
(mul DI
(ext DI (and WI src1 (const #xffff0000)))
(ext DI (trunc HI (sra WI src2 (const 16))))))
(const 8))
(const 8)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni maclo "maclo"
((MACH m32r) (PIPE S) (IDOC MAC))
"maclo $src1,$src2"
(+ OP1_3 OP2_5 src1 src2)
(set accum
(sra DI
(sll DI
(add DI
accum
(mul DI
(ext DI (sll WI src1 (const 16)))
(ext DI (trunc HI src2))))
(const 8))
(const 8)))
((m32r/d (unit u-mac)))
)
(dni maclo-a "maclo-a"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"maclo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 5) src2)
(set acc
(sra DI
(sll DI
(add DI
acc
(mul DI
(ext DI (sll WI src1 (const 16)))
(ext DI (trunc HI src2))))
(const 8))
(const 8)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni macwhi "macwhi"
((MACH m32r) (PIPE S) (IDOC MAC))
"macwhi $src1,$src2"
(+ OP1_3 OP2_6 src1 src2)
(set accum
(sra DI
(sll DI
(add DI
accum
(mul DI
(ext DI src1)
(ext DI (trunc HI (sra WI src2 (const 16))))))
(const 8))
(const 8)))
((m32r/d (unit u-mac)))
)
(dni macwhi-a "macwhi-a"
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
"macwhi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 6) src2)
(set acc
(add acc
(mul (ext DI src1)
(ext DI (trunc HI (sra src2 (const 16)))))))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni macwlo "macwlo"
((MACH m32r) (PIPE S) (IDOC MAC))
"macwlo $src1,$src2"
(+ OP1_3 OP2_7 src1 src2)
(set accum
(sra DI
(sll DI
(add DI
accum
(mul DI
(ext DI src1)
(ext DI (trunc HI src2))))
(const 8))
(const 8)))
((m32r/d (unit u-mac)))
)
(dni macwlo-a "macwlo-a"
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
"macwlo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 7) src2)
(set acc
(add acc
(mul (ext DI src1)
(ext DI (trunc HI src2)))))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni mul "mul"
((PIPE S) (IDOC ALU))
"mul $dr,$sr"
(+ OP1_1 OP2_6 dr sr)
(set dr (mul dr sr))
((m32r/d (unit u-exec (cycles 4)))
(m32rx (unit u-exec (cycles 4)))
(m32r2 (unit u-exec (cycles 4))))
)
(dni mulhi "mulhi"
((MACH m32r) (PIPE S) (IDOC ACCUM))
"mulhi $src1,$src2"
(+ OP1_3 OP2_0 src1 src2)
(set accum
(sra DI
(sll DI
(mul DI
(ext DI (and WI src1 (const #xffff0000)))
(ext DI (trunc HI (sra WI src2 (const 16)))))
(const 16))
(const 16)))
((m32r/d (unit u-mac)))
)
(dni mulhi-a "mulhi-a"
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mulhi $src1,$src2,$acc"
(+ OP1_3 (f-op23 0) src1 acc src2)
(set acc
(sra DI
(sll DI
(mul DI
(ext DI (and WI src1 (const #xffff0000)))
(ext DI (trunc HI (sra WI src2 (const 16)))))
(const 16))
(const 16)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni mullo "mullo"
((MACH m32r) (PIPE S) (IDOC ACCUM))
"mullo $src1,$src2"
(+ OP1_3 OP2_1 src1 src2)
(set accum
(sra DI
(sll DI
(mul DI
(ext DI (sll WI src1 (const 16)))
(ext DI (trunc HI src2)))
(const 16))
(const 16)))
((m32r/d (unit u-mac)))
)
(dni mullo-a "mullo-a"
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mullo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 1) src2)
(set acc
(sra DI
(sll DI
(mul DI
(ext DI (sll WI src1 (const 16)))
(ext DI (trunc HI src2)))
(const 16))
(const 16)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni mulwhi "mulwhi"
((MACH m32r) (PIPE S) (IDOC ACCUM))
"mulwhi $src1,$src2"
(+ OP1_3 OP2_2 src1 src2)
(set accum
(sra DI
(sll DI
(mul DI
(ext DI src1)
(ext DI (trunc HI (sra WI src2 (const 16)))))
(const 8))
(const 8)))
((m32r/d (unit u-mac)))
)
(dni mulwhi-a "mulwhi-a"
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
"mulwhi $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 2) src2)
(set acc
(mul (ext DI src1)
(ext DI (trunc HI (sra src2 (const 16))))))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni mulwlo "mulwlo"
((MACH m32r) (PIPE S) (IDOC ACCUM))
"mulwlo $src1,$src2"
(+ OP1_3 OP2_3 src1 src2)
(set accum
(sra DI
(sll DI
(mul DI
(ext DI src1)
(ext DI (trunc HI src2)))
(const 8))
(const 8)))
((m32r/d (unit u-mac)))
)
(dni mulwlo-a "mulwlo-a"
((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
"mulwlo $src1,$src2,$acc"
(+ OP1_3 src1 acc (f-op23 3) src2)
(set acc
(mul (ext DI src1)
(ext DI (trunc HI src2))))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni mv "mv"
((PIPE OS) (IDOC ALU))
"mv $dr,$sr"
(+ OP1_1 OP2_8 dr sr)
(set dr sr)
()
)
(dni mvfachi "mvfachi"
((MACH m32r) (PIPE S) (IDOC ACCUM))
"mvfachi $dr"
(+ OP1_5 OP2_15 (f-r2 0) dr)
(set dr (trunc WI (sra DI accum (const 32))))
((m32r/d (unit u-exec (cycles 2))))
)
(dni mvfachi-a "mvfachi-a"
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvfachi $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 0))
(set dr (trunc WI (sra DI accs (const 32))))
((m32rx (unit u-exec (cycles 2)))
(m32r2 (unit u-exec (cycles 2))))
)
(dni mvfaclo "mvfaclo"
((MACH m32r) (PIPE S) (IDOC ACCUM))
"mvfaclo $dr"
(+ OP1_5 OP2_15 (f-r2 1) dr)
(set dr (trunc WI accum))
((m32r/d (unit u-exec (cycles 2))))
)
(dni mvfaclo-a "mvfaclo-a"
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvfaclo $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 1))
(set dr (trunc WI accs))
((m32rx (unit u-exec (cycles 2)))
(m32r2 (unit u-exec (cycles 2))))
)
(dni mvfacmi "mvfacmi"
((MACH m32r) (PIPE S) (IDOC ACCUM))
"mvfacmi $dr"
(+ OP1_5 OP2_15 (f-r2 2) dr)
(set dr (trunc WI (sra DI accum (const 16))))
((m32r/d (unit u-exec (cycles 2))))
)
(dni mvfacmi-a "mvfacmi-a"
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvfacmi $dr,$accs"
(+ OP1_5 dr OP2_15 accs (f-op3 2))
(set dr (trunc WI (sra DI accs (const 16))))
((m32rx (unit u-exec (cycles 2)))
(m32r2 (unit u-exec (cycles 2))))
)
(dni mvfc "mvfc"
((PIPE O) (IDOC MISC))
"mvfc $dr,$scr"
(+ OP1_1 OP2_9 dr scr)
(set dr scr)
()
)
(dni mvtachi "mvtachi"
((MACH m32r) (PIPE S) (IDOC ACCUM))
"mvtachi $src1"
(+ OP1_5 OP2_7 (f-r2 0) src1)
(set accum
(or DI
(and DI accum (const DI #xffffffff))
(sll DI (ext DI src1) (const 32))))
((m32r/d (unit u-exec (in sr src1))))
)
(dni mvtachi-a "mvtachi-a"
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvtachi $src1,$accs"
(+ OP1_5 src1 OP2_7 accs (f-op3 0))
(set accs
(or DI
(and DI accs (const DI #xffffffff))
(sll DI (ext DI src1) (const 32))))
((m32rx (unit u-exec (in sr src1)))
(m32r2 (unit u-exec (in sr src1))))
)
(dni mvtaclo "mvtaclo"
((MACH m32r) (PIPE S) (IDOC ACCUM))
"mvtaclo $src1"
(+ OP1_5 OP2_7 (f-r2 1) src1)
(set accum
(or DI
(and DI accum (const DI #xffffffff00000000))
(zext DI src1)))
((m32r/d (unit u-exec (in sr src1))))
)
(dni mvtaclo-a "mvtaclo-a"
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"mvtaclo $src1,$accs"
(+ OP1_5 src1 OP2_7 accs (f-op3 1))
(set accs
(or DI
(and DI accs (const DI #xffffffff00000000))
(zext DI src1)))
((m32rx (unit u-exec (in sr src1)))
(m32r2 (unit u-exec (in sr src1))))
)
(dni mvtc "mvtc"
((PIPE O) (IDOC MISC))
"mvtc $sr,$dcr"
(+ OP1_1 OP2_10 dcr sr)
(set dcr sr)
()
)
(dni neg "neg"
((PIPE OS) (IDOC ALU))
"neg $dr,$sr"
(+ OP1_0 OP2_3 dr sr)
(set dr (neg sr))
()
)
(dni nop "nop"
((PIPE OS) (IDOC MISC))
"nop"
(+ OP1_7 OP2_0 (f-r1 0) (f-r2 0))
(c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n")
((m32r/d (unit u-exec (cycles 0)))
(m32rx (unit u-exec (cycles 0)))
(m32r2 (unit u-exec (cycles 0))))
)
(dni not "not"
((PIPE OS) (IDOC ALU))
"not $dr,$sr"
(+ OP1_0 OP2_11 dr sr)
(set dr (inv sr))
()
)
(dni rac "rac"
((MACH m32r) (PIPE S) (IDOC MAC))
"rac"
(+ OP1_5 OP2_9 (f-r1 0) (f-r2 0))
(sequence ((DI tmp1))
(set tmp1 (sll DI accum (const 1)))
(set tmp1 (add DI tmp1 (const DI #x8000)))
(set accum
(cond DI
((gt tmp1 (const DI #x00007fffffff0000))
(const DI #x00007fffffff0000))
((lt tmp1 (const DI #xffff800000000000))
(const DI #xffff800000000000))
(else (and tmp1 (const DI #xffffffffffff0000)))))
)
((m32r/d (unit u-mac)))
)
(dni rac-dsi "rac-dsi"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rac $accd,$accs,$imm1"
(+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
(sequence ((DI tmp1))
(set tmp1 (sll accs imm1))
(set tmp1 (add tmp1 (const DI #x8000)))
(set accd
(cond DI
((gt tmp1 (const DI #x00007fffffff0000))
(const DI #x00007fffffff0000))
((lt tmp1 (const DI #xffff800000000000))
(const DI #xffff800000000000))
(else (and tmp1 (const DI #xffffffffffff0000)))))
)
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dnmi rac-d "rac-d"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rac $accd"
(emit rac-dsi accd (f-accs 0) (f-imm1 0))
)
(dnmi rac-ds "rac-ds"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rac $accd,$accs"
(emit rac-dsi accd accs (f-imm1 0))
)
(dni rach "rach"
((MACH m32r) (PIPE S) (IDOC MAC))
"rach"
(+ OP1_5 OP2_8 (f-r1 0) (f-r2 0))
(sequence ((DI tmp1))
(set tmp1 (and accum (const DI #xffffffffffffff)))
(if (andif (ge tmp1 (const DI #x003fff80000000))
(le tmp1 (const DI #x7fffffffffffff)))
(set tmp1 (const DI #x003fff80000000))
(if (andif (ge tmp1 (const DI #x80000000000000))
(le tmp1 (const DI #xffc00000000000)))
(set tmp1 (const DI #xffc00000000000))
(set tmp1 (and (add accum (const DI #x40000000))
(const DI #xffffffff80000000)))))
(set tmp1 (sll tmp1 (const 1)))
(set accum
(sra DI (sll DI tmp1 (const 7)) (const 7)))
)
((m32r/d (unit u-mac)))
)
(dni rach-dsi "rach-dsi"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rach $accd,$accs,$imm1"
(+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
(sequence ((DI tmp1))
(set tmp1 (sll accs imm1))
(set tmp1 (add tmp1 (const DI #x80000000)))
(set accd
(cond DI
((gt tmp1 (const DI #x00007fff00000000))
(const DI #x00007fff00000000))
((lt tmp1 (const DI #xffff800000000000))
(const DI #xffff800000000000))
(else (and tmp1 (const DI #xffffffff00000000)))))
)
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dnmi rach-d "rach-d"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rach $accd"
(emit rach-dsi accd (f-accs 0) (f-imm1 0))
)
(dnmi rach-ds "rach-ds"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"rach $accd,$accs"
(emit rach-dsi accd accs (f-imm1 0))
)
(dni rte "rte"
(UNCOND-CTI (PIPE O) (IDOC BR))
"rte"
(+ OP1_1 OP2_13 (f-r1 0) (f-r2 6))
(sequence ()
(set pc (and (reg h-cr 6) (const -4)))
(set (reg h-cr 6) (reg h-cr 14))
(set (reg h-psw) (reg h-bpsw))
(set (reg h-bpsw) (reg h-bbpsw))
)
()
)
(dni seth "seth"
((IDOC ALU))
"seth $dr,$hash$hi16"
(+ OP1_13 OP2_12 dr (f-r2 0) hi16)
(set dr (sll WI hi16 (const 16)))
()
)
(define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
(begin
(dni sym sym ((PIPE O_OS) (IDOC ALU))
(.str sym " $dr,$sr")
(+ OP1_1 op2-r-op dr sr)
(set dr (sem-op dr (and sr (const 31))))
()
)
(dni (.sym sym "3") sym ((IDOC ALU))
(.str sym "3 $dr,$sr,$simm16")
(+ OP1_9 op2-3-op dr sr simm16)
(set dr (sem-op sr (and WI simm16 (const 31))))
()
)
(dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU))
(.str sym "i $dr,$uimm5")
(+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
(set dr (sem-op dr uimm5))
()
)
)
)
(shift-op sll OP2_4 OP2_12 2 sll)
(shift-op sra OP2_2 OP2_10 1 sra)
(shift-op srl OP2_0 OP2_8 0 srl)
(define-pmacro (store-op suffix op2-op mode)
(begin
(dni (.sym st suffix) (.str "st" suffix)
((PIPE O) (IDOC MEM))
(.str "st" suffix " $src1,@$src2")
(+ OP1_2 op2-op src1 src2)
(set mode (mem mode src2) src1)
((m32r/d (unit u-store (cycles 1)))
(m32rx (unit u-store (cycles 1)))
(m32r2 (unit u-store (cycles 1))))
)
(dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
(NO-DIS (PIPE O) (IDOC MEM))
(.str "st" suffix " $src1,@($src2)")
(emit (.sym st suffix) src1 src2))
(dni (.sym st suffix -d) (.str "st" suffix "-d")
((IDOC MEM))
(.str "st" suffix " $src1,@($slo16,$src2)")
(+ OP1_10 op2-op src1 src2 slo16)
(set mode (mem mode (add src2 slo16)) src1)
((m32r/d (unit u-store (cycles 2)))
(m32rx (unit u-store (cycles 2)))
(m32r2 (unit u-store (cycles 2))))
)
(dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
(NO-DIS (IDOC MEM))
(.str "st" suffix " $src1,@($src2,$slo16)")
(emit (.sym st suffix -d) src1 src2 slo16))
)
)
(store-op "" OP2_4 WI)
(store-op b OP2_0 QI)
(store-op h OP2_2 HI)
(dni st-plus "st+"
((PIPE O) (IDOC MEM))
"st $src1,@+$src2"
(+ OP1_2 OP2_6 src1 src2)
(sequence ((WI new-src2))
(set new-src2 (add WI src2 (const WI 4)))
(set (mem WI new-src2) src1)
(set src2 new-src2))
((m32r/d (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32r2 (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
(dni sth-plus "sth+"
((MACH m32rx,m32r2) (PIPE O) SPECIAL)
"sth $src1,@$src2+"
(+ OP1_2 OP2_3 src1 src2)
(sequence ((HI new-src2))
(set (mem HI new-src2) src1)
(set new-src2 (add src2 (const 2)))
(set src2 new-src2))
((m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32r2 (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
(dni stb-plus "stb+"
((MACH m32rx,m32r2) (PIPE O) SPECIAL)
"stb $src1,@$src2+"
(+ OP1_2 OP2_1 src1 src2)
(sequence ((QI new-src2))
(set (mem QI new-src2) src1)
(set new-src2 (add src2 (const 1)))
(set src2 new-src2))
((m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32r2 (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
(dni st-minus "st-"
((PIPE O) (IDOC MEM))
"st $src1,@-$src2"
(+ OP1_2 OP2_7 src1 src2)
(sequence ((WI new-src2))
(set new-src2 (sub src2 (const 4)))
(set (mem WI new-src2) src1)
(set src2 new-src2))
((m32r/d (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32rx (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
(m32r2 (unit u-store)
(unit u-exec (in dr src2) (out dr src2) (cycles 0)))
)
)
(dnmi push "push" ((PIPE O) (IDOC MEM))
"push $src1"
(emit st-minus src1 (src2 15)) )
(dni sub "sub"
((PIPE OS) (IDOC ALU))
"sub $dr,$sr"
(+ OP1_0 OP2_2 dr sr)
(set dr (sub dr sr))
()
)
(dni subv "sub:rv"
((PIPE OS) (IDOC ALU))
"subv $dr,$sr"
(+ OP1_0 OP2_0 dr sr)
(parallel ()
(set dr (sub dr sr))
(set condbit (sub-oflag dr sr (const 0))))
()
)
(dni subx "sub:rx"
((PIPE OS) (IDOC ALU))
"subx $dr,$sr"
(+ OP1_0 OP2_1 dr sr)
(parallel ()
(set dr (subc dr sr condbit))
(set condbit (sub-cflag dr sr condbit)))
()
)
(dni trap "trap"
(UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC))
"trap $uimm4"
(+ OP1_1 OP2_15 (f-r1 0) uimm4)
(sequence ()
(set (reg h-cr 14) (reg h-cr 6))
(set (reg h-cr 6) (add pc (const 4)))
(set (reg h-bbpsw) (reg h-bpsw))
(set (reg h-bpsw) (reg h-psw))
(set (reg h-psw) (and (reg h-psw) (const #x80)))
(set WI pc (c-call WI "m32r_trap" pc uimm4))
)
()
)
(dni unlock "unlock"
((PIPE O) (IDOC MISC))
"unlock $src1,@$src2"
(+ OP1_2 OP2_5 src1 src2)
(sequence ()
(if (reg h-lock)
(set (mem WI src2) src1))
(set (reg h-lock) (const BI 0)))
((m32r/d (unit u-load))
(m32rx (unit u-load))
(m32r2 (unit u-load)))
)
(dni satb "satb"
((MACH m32rx,m32r2) (IDOC ALU))
"satb $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
(set dr
(cond WI
((ge sr (const 127)) (const 127))
((le sr (const -128)) (const -128))
(else sr)))
()
)
(dni sath "sath"
((MACH m32rx,m32r2) (IDOC ALU))
"sath $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
(set dr
(cond WI
((ge sr (const 32767)) (const 32767))
((le sr (const -32768)) (const -32768))
(else sr)))
()
)
(dni sat "sat"
((MACH m32rx,m32r2) SPECIAL (IDOC ALU))
"sat $dr,$sr"
(+ OP1_8 dr OP2_6 sr (f-uimm16 0))
(set dr
(if WI condbit
(if WI (lt sr (const 0))
(const #x7fffffff)
(const #x80000000))
sr))
()
)
(dni pcmpbz "pcmpbz"
((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU))
"pcmpbz $src2"
(+ OP1_0 (f-r1 3) OP2_7 src2)
(set condbit
(cond BI
((eq (and src2 (const #xff)) (const 0)) (const BI 1))
((eq (and src2 (const #xff00)) (const 0)) (const BI 1))
((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
(else (const BI 0))))
((m32rx (unit u-cmp))
(m32r2 (unit u-cmp)))
)
(dni sadd "sadd"
((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
"sadd"
(+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
(set (reg h-accums 0)
(add (sra (reg h-accums 1) (const 16))
(reg h-accums 0)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni macwu1 "macwu1"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"macwu1 $src1,$src2"
(+ OP1_5 src1 OP2_11 src2)
(set (reg h-accums 1)
(sra DI
(sll DI
(add DI
(reg h-accums 1)
(mul DI
(ext DI src1)
(ext DI (and src2 (const #xffff)))))
(const 8))
(const 8)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni msblo "msblo"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"msblo $src1,$src2"
(+ OP1_5 src1 OP2_13 src2)
(set accum
(sra DI
(sll DI
(sub accum
(sra DI
(sll DI
(mul DI
(ext DI (trunc HI src1))
(ext DI (trunc HI src2)))
(const 32))
(const 16)))
(const 8))
(const 8)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni mulwu1 "mulwu1"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"mulwu1 $src1,$src2"
(+ OP1_5 src1 OP2_10 src2)
(set (reg h-accums 1)
(sra DI
(sll DI
(mul DI
(ext DI src1)
(ext DI (and src2 (const #xffff))))
(const 16))
(const 16)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni maclh1 "maclh1"
((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
"maclh1 $src1,$src2"
(+ OP1_5 src1 OP2_12 src2)
(set (reg h-accums 1)
(sra DI
(sll DI
(add DI
(reg h-accums 1)
(sll DI
(ext DI
(mul SI
(ext SI (trunc HI src1))
(sra SI src2 (const SI 16))))
(const 16)))
(const 8))
(const 8)))
((m32rx (unit u-mac))
(m32r2 (unit u-mac)))
)
(dni sc "sc"
((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"sc"
(+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
(skip (zext INT condbit))
()
)
(dni snc "snc"
((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
"snc"
(+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
(skip (zext INT (not condbit)))
()
)
(dni clrpsw "clrpsw"
((PIPE O) SPECIAL_M32R)
"clrpsw $uimm8"
(+ OP1_7 (f-r1 2) uimm8)
(set USI (reg h-cr 0)
(and USI (reg h-cr 0)
(or USI (inv BI uimm8) (const #xff00))))
()
)
(dni setpsw "setpsw"
((PIPE O) SPECIAL_M32R)
"setpsw $uimm8"
(+ OP1_7 (f-r1 1) uimm8)
(set USI (reg h-cr 0) uimm8)
()
)
(dni bset "bset"
(SPECIAL_M32R)
"bset $uimm3,@($slo16,$sr)"
(+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)
(set QI (mem QI (add sr slo16))
(or QI (mem QI (add sr slo16))
(sll USI (const 1) (sub (const 7) uimm3))))
()
)
(dni bclr "bclr"
(SPECIAL_M32R)
"bclr $uimm3,@($slo16,$sr)"
(+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16)
(set QI (mem QI (add sr slo16))
(and QI (mem QI (add sr slo16))
(inv QI (sll USI (const 1) (sub (const 7) uimm3)))))
()
)
(dni btst "btst"
(SPECIAL_M32R (PIPE O))
"btst $uimm3,$sr"
(+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)
(set condbit (and QI (srl USI sr (sub (const 7) uimm3)) (const 1)))
()
)