@c Copyright (C) 1991, 1992, 1993, 1994, 1995, 2003 @c Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @page @node H8/500-Dependent @chapter H8/500 Dependent Features @cindex H8/500 support @menu * H8/500 Options:: Options * H8/500 Syntax:: Syntax * H8/500 Floating Point:: Floating Point * H8/500 Directives:: H8/500 Machine Directives * H8/500 Opcodes:: Opcodes @end menu @node H8/500 Options @section Options @cindex H8/500 options (none) @cindex options, H8/500 (none) @code{@value{AS}} has no additional command-line options for the Renesas (formerly Hitachi) H8/500 family. @node H8/500 Syntax @section Syntax @menu * H8/500-Chars:: Special Characters * H8/500-Regs:: Register Names * H8/500-Addressing:: Addressing Modes @end menu @node H8/500-Chars @subsection Special Characters @cindex line comment character, H8/500 @cindex H8/500 line comment character @samp{!} is the line comment character. @cindex line separator, H8/500 @cindex statement separator, H8/500 @cindex H8/500 line separator @samp{;} can be used instead of a newline to separate statements. @cindex symbol names, @samp{$} in @cindex @code{$} in symbol names Since @samp{$} has no special meaning, you may use it in symbol names. @node H8/500-Regs @subsection Register Names @cindex H8/500 registers @cindex registers, H8/500 You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2}, @samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, and @samp{r7} to refer to the H8/500 registers. The H8/500 also has these control registers: @table @code @item cp code pointer @item dp data pointer @item bp base pointer @item tp stack top pointer @item ep extra pointer @item sr status register @item ccr condition code register @end table All registers are 16 bits long. To represent 32 bit numbers, use two adjacent registers; for distant memory addresses, use one of the segment pointers (@code{cp} for the program counter; @code{dp} for @code{r0}--@code{r3}; @code{ep} for @code{r4} and @code{r5}; and @code{tp} for @code{r6} and @code{r7}. @node H8/500-Addressing @subsection Addressing Modes @cindex addressing modes, H8/500 @cindex H8/500 addressing modes @value{AS} understands the following addressing modes for the H8/500: @table @code @item R@var{n} Register direct @item @@R@var{n} Register indirect @item @@(d:8, R@var{n}) Register indirect with 8 bit signed displacement @item @@(d:16, R@var{n}) Register indirect with 16 bit signed displacement @item @@-R@var{n} Register indirect with pre-decrement @item @@R@var{n}+ Register indirect with post-increment @item @@@var{aa}:8 8 bit absolute address @item @@@var{aa}:16 16 bit absolute address @item #@var{xx}:8 8 bit immediate @item #@var{xx}:16 16 bit immediate @end table @node H8/500 Floating Point @section Floating Point @cindex floating point, H8/500 (@sc{ieee}) @cindex H8/500 floating point (@sc{ieee}) The H8/500 family has no hardware floating point, but the @code{.float} directive generates @sc{ieee} floating-point numbers for compatibility with other development tools. @node H8/500 Directives @section H8/500 Machine Directives @cindex H8/500 machine directives (none) @cindex machine directives, H8/500 (none) @cindex @code{word} directive, H8/500 @cindex @code{int} directive, H8/500 @code{@value{AS}} has no machine-dependent directives for the H8/500. However, on this platform the @samp{.int} and @samp{.word} directives generate 16-bit numbers. @node H8/500 Opcodes @section Opcodes @cindex H8/500 opcode summary @cindex opcode summary, H8/500 @cindex mnemonics, H8/500 @cindex instruction summary, H8/500 For detailed information on the H8/500 machine instruction set, see @cite{H8/500 Series Programming Manual} (Renesas M21T001). @code{@value{AS}} implements all the standard H8/500 opcodes. No additional pseudo-instructions are needed on this family. @ifset SMALL @c this table, due to the multi-col faking and hardcoded order, looks silly @c except in smallbook. See comments below "@set SMALL" near top of this file. The following table summarizes H8/500 opcodes and their operands: @c Use @group if it ever works, instead of @page @page @smallexample @i{Legend:} abs8 @r{8-bit absolute address} abs16 @r{16-bit absolute address} abs24 @r{24-bit absolute address} crb @r{@code{ccr}, @code{br}, @code{ep}, @code{dp}, @code{tp}, @code{dp}} disp8 @r{8-bit displacement} ea @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},} @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16},} @r{@code{#xx:8}, @code{#xx:16}} ea_mem @r{@code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},} @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}} ea_noimm @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},} @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}} fp r6 imm4 @r{4-bit immediate data} imm8 @r{8-bit immediate data} imm16 @r{16-bit immediate data} pcrel8 @r{8-bit offset from program counter} pcrel16 @r{16-bit offset from program counter} qim @r{@code{-2}, @code{-1}, @code{1}, @code{2}} rd @r{any register} rs @r{a register distinct from rd} rlist @r{comma-separated list of registers in parentheses;} @r{register ranges @code{rd-rs} are allowed} sp @r{stack pointer (@code{r7})} sr @r{status register} sz @r{size; @samp{.b} or @samp{.w}. If omitted, default @samp{.w}} ldc[.b] ea,crb bcc[.w] pcrel16 ldc[.w] ea,sr bcc[.b] pcrel8 add[:q] sz qim,ea_noimm bhs[.w] pcrel16 add[:g] sz ea,rd bhs[.b] pcrel8 adds sz ea,rd bcs[.w] pcrel16 addx sz ea,rd bcs[.b] pcrel8 and sz ea,rd blo[.w] pcrel16 andc[.b] imm8,crb blo[.b] pcrel8 andc[.w] imm16,sr bne[.w] pcrel16 bpt bne[.b] pcrel8 bra[.w] pcrel16 beq[.w] pcrel16 bra[.b] pcrel8 beq[.b] pcrel8 bt[.w] pcrel16 bvc[.w] pcrel16 bt[.b] pcrel8 bvc[.b] pcrel8 brn[.w] pcrel16 bvs[.w] pcrel16 brn[.b] pcrel8 bvs[.b] pcrel8 bf[.w] pcrel16 bpl[.w] pcrel16 bf[.b] pcrel8 bpl[.b] pcrel8 bhi[.w] pcrel16 bmi[.w] pcrel16 bhi[.b] pcrel8 bmi[.b] pcrel8 bls[.w] pcrel16 bge[.w] pcrel16 bls[.b] pcrel8 bge[.b] pcrel8 @page blt[.w] pcrel16 mov[:g][.b] imm8,ea_mem blt[.b] pcrel8 mov[:g][.w] imm16,ea_mem bgt[.w] pcrel16 movfpe[.b] ea,rd bgt[.b] pcrel8 movtpe[.b] rs,ea_noimm ble[.w] pcrel16 mulxu sz ea,rd ble[.b] pcrel8 neg sz ea bclr sz imm4,ea_noimm nop bclr sz rs,ea_noimm not sz ea bnot sz imm4,ea_noimm or sz ea,rd bnot sz rs,ea_noimm orc[.b] imm8,crb bset sz imm4,ea_noimm orc[.w] imm16,sr bset sz rs,ea_noimm pjmp abs24 bsr[.b] pcrel8 pjmp @@rd bsr[.w] pcrel16 pjsr abs24 btst sz imm4,ea_noimm pjsr @@rd btst sz rs,ea_noimm prtd imm8 clr sz ea prtd imm16 cmp[:e][.b] imm8,rd prts cmp[:i][.w] imm16,rd rotl sz ea cmp[:g].b imm8,ea_noimm rotr sz ea cmp[:g][.w] imm16,ea_noimm rotxl sz ea Cmp[:g] sz ea,rd rotxr sz ea dadd rs,rd rtd imm8 divxu sz ea,rd rtd imm16 dsub rs,rd rts exts[.b] rd scb/f rs,pcrel8 extu[.b] rd scb/ne rs,pcrel8 jmp @@rd scb/eq rs,pcrel8 jmp @@(imm8,rd) shal sz ea jmp @@(imm16,rd) shar sz ea jmp abs16 shll sz ea jsr @@rd shlr sz ea jsr @@(imm8,rd) sleep jsr @@(imm16,rd) stc[.b] crb,ea_noimm jsr abs16 stc[.w] sr,ea_noimm ldm @@sp+,(rlist) stm (rlist),@@-sp link fp,imm8 sub sz ea,rd link fp,imm16 subs sz ea,rd mov[:e][.b] imm8,rd subx sz ea,rd mov[:i][.w] imm16,rd swap[.b] rd mov[:l][.w] abs8,rd tas[.b] ea mov[:l].b abs8,rd trapa imm4 mov[:s][.w] rs,abs8 trap/vs mov[:s].b rs,abs8 tst sz ea mov[:f][.w] @@(disp8,fp),rd unlk fp mov[:f][.w] rs,@@(disp8,fp) xch[.w] rs,rd mov[:f].b @@(disp8,fp),rd xor sz ea,rd mov[:f].b rs,@@(disp8,fp) xorc.b imm8,crb mov[:g] sz rs,ea_mem xorc.w imm16,sr mov[:g] sz ea,rd @end smallexample @end ifset