SystemZTargetMachine.cpp [plain text]
#include "SystemZTargetMachine.h"
#include "SystemZTargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
using namespace llvm;
extern cl::opt<bool> MISchedPostRA;
extern "C" void LLVMInitializeSystemZTarget() {
RegisterTargetMachine<SystemZTargetMachine> X(TheSystemZTarget);
}
static bool UsesVectorABI(StringRef CPU, StringRef FS) {
bool VectorABI = true;
if (CPU.empty() || CPU == "generic" ||
CPU == "z10" || CPU == "z196" || CPU == "zEC12")
VectorABI = false;
SmallVector<StringRef, 3> Features;
FS.split(Features, ',', -1, false );
for (auto &Feature : Features) {
if (Feature == "vector" || Feature == "+vector")
VectorABI = true;
if (Feature == "-vector")
VectorABI = false;
}
return VectorABI;
}
static std::string computeDataLayout(const Triple &TT, StringRef CPU,
StringRef FS) {
bool VectorABI = UsesVectorABI(CPU, FS);
std::string Ret = "";
Ret += "E";
Ret += DataLayout::getManglingComponent(TT);
Ret += "-i1:8:16-i8:8:16";
Ret += "-i64:64";
Ret += "-f128:64";
if (VectorABI)
Ret += "-v128:64";
Ret += "-a:8:16";
Ret += "-n32:64";
return Ret;
}
SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(TT, CPU, FS, *this) {
initAsmInfo();
}
SystemZTargetMachine::~SystemZTargetMachine() {}
namespace {
class SystemZPassConfig : public TargetPassConfig {
public:
SystemZPassConfig(SystemZTargetMachine *TM, PassManagerBase &PM)
: TargetPassConfig(TM, PM) {}
SystemZTargetMachine &getSystemZTargetMachine() const {
return getTM<SystemZTargetMachine>();
}
void addIRPasses() override;
bool addInstSelector() override;
void addPreSched2() override;
void addPreEmitPass() override;
};
}
void SystemZPassConfig::addIRPasses() {
TargetPassConfig::addIRPasses();
}
bool SystemZPassConfig::addInstSelector() {
addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
if (getOptLevel() != CodeGenOpt::None)
addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
return false;
}
void SystemZPassConfig::addPreSched2() {
if (getOptLevel() != CodeGenOpt::None &&
getSystemZTargetMachine().getSubtargetImpl()->hasLoadStoreOnCond())
addPass(&IfConverterID);
}
void SystemZPassConfig::addPreEmitPass() {
if (getOptLevel() != CodeGenOpt::None)
addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
if (getOptLevel() != CodeGenOpt::None)
addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
if (getOptLevel() != CodeGenOpt::None) {
if (MISchedPostRA)
addPass(&PostMachineSchedulerID);
else
addPass(&PostRASchedulerID);
}
}
TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
return new SystemZPassConfig(this, PM);
}
TargetIRAnalysis SystemZTargetMachine::getTargetIRAnalysis() {
return TargetIRAnalysis([this](const Function &F) {
return TargetTransformInfo(SystemZTTIImpl(this, F));
});
}