PPCVSXSwapRemoval.cpp [plain text]
#include "PPCInstrInfo.h"
#include "PPC.h"
#include "PPCInstrBuilder.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/EquivalenceClasses.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
#define DEBUG_TYPE "ppc-vsx-swaps"
namespace llvm {
void initializePPCVSXSwapRemovalPass(PassRegistry&);
}
namespace {
struct PPCVSXSwapEntry {
MachineInstr *VSEMI;
int VSEId;
unsigned int IsLoad : 1;
unsigned int IsStore : 1;
unsigned int IsSwap : 1;
unsigned int MentionsPhysVR : 1;
unsigned int IsSwappable : 1;
unsigned int MentionsPartialVR : 1;
unsigned int SpecialHandling : 3;
unsigned int WebRejected : 1;
unsigned int WillRemove : 1;
};
enum SHValues {
SH_NONE = 0,
SH_EXTRACT,
SH_INSERT,
SH_NOSWAP_LD,
SH_NOSWAP_ST,
SH_SPLAT,
SH_XXPERMDI,
SH_COPYWIDEN
};
struct PPCVSXSwapRemoval : public MachineFunctionPass {
static char ID;
const PPCInstrInfo *TII;
MachineFunction *MF;
MachineRegisterInfo *MRI;
std::vector<PPCVSXSwapEntry> SwapVector;
DenseMap<MachineInstr*, int> SwapMap;
EquivalenceClasses<int> *EC;
PPCVSXSwapRemoval() : MachineFunctionPass(ID) {
initializePPCVSXSwapRemovalPass(*PassRegistry::getPassRegistry());
}
private:
void initialize(MachineFunction &MFParm);
bool gatherVectorInstructions();
int addSwapEntry(MachineInstr *MI, PPCVSXSwapEntry &SwapEntry);
unsigned lookThruCopyLike(unsigned SrcReg, unsigned VecIdx);
void formWebs();
void recordUnoptimizableWebs();
void markSwapsForRemoval();
bool removeSwaps();
void insertSwap(MachineInstr *MI, MachineBasicBlock::iterator InsertPoint,
unsigned DstReg, unsigned SrcReg);
void handleSpecialSwappables(int EntryIdx);
void dumpSwapVector();
bool isRegInClass(unsigned Reg, const TargetRegisterClass *RC) {
if (TargetRegisterInfo::isVirtualRegister(Reg))
return RC->hasSubClassEq(MRI->getRegClass(Reg));
return RC->contains(Reg);
}
bool isVecReg(unsigned Reg) {
return (isRegInClass(Reg, &PPC::VSRCRegClass) ||
isRegInClass(Reg, &PPC::VRRCRegClass));
}
bool isScalarVecReg(unsigned Reg) {
return (isRegInClass(Reg, &PPC::VSFRCRegClass) ||
isRegInClass(Reg, &PPC::VSSRCRegClass));
}
bool isAnyVecReg(unsigned Reg, bool &Partial) {
if (isScalarVecReg(Reg))
Partial = true;
return isScalarVecReg(Reg) || isVecReg(Reg);
}
public:
bool runOnMachineFunction(MachineFunction &MF) override {
const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
if (!STI.hasVSX())
return false;
bool Changed = false;
initialize(MF);
if (gatherVectorInstructions()) {
formWebs();
recordUnoptimizableWebs();
markSwapsForRemoval();
Changed = removeSwaps();
}
delete EC;
return Changed;
}
};
void PPCVSXSwapRemoval::initialize(MachineFunction &MFParm) {
MF = &MFParm;
MRI = &MF->getRegInfo();
TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
const int InitialVectorSize(256);
SwapVector.clear();
SwapVector.reserve(InitialVectorSize);
EC = new EquivalenceClasses<int>;
}
bool PPCVSXSwapRemoval::gatherVectorInstructions() {
bool RelevantFunction = false;
for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {
if (MI.isDebugValue())
continue;
bool RelevantInstr = false;
bool Partial = false;
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
if (isAnyVecReg(Reg, Partial)) {
RelevantInstr = true;
break;
}
}
if (!RelevantInstr)
continue;
RelevantFunction = true;
PPCVSXSwapEntry SwapEntry{};
int VecIdx = addSwapEntry(&MI, SwapEntry);
switch(MI.getOpcode()) {
default:
if (Partial)
SwapVector[VecIdx].MentionsPartialVR = 1;
else
SwapVector[VecIdx].IsSwappable = 1;
break;
case PPC::XXPERMDI: {
int immed = MI.getOperand(3).getImm();
if (immed == 2) {
unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
VecIdx);
unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
VecIdx);
if (trueReg1 == trueReg2)
SwapVector[VecIdx].IsSwap = 1;
else {
SwapVector[VecIdx].IsSwappable = 1;
SwapVector[VecIdx].SpecialHandling = SHValues::SH_XXPERMDI;
}
} else if (immed == 0 || immed == 3) {
SwapVector[VecIdx].IsSwappable = 1;
SwapVector[VecIdx].SpecialHandling = SHValues::SH_XXPERMDI;
unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
VecIdx);
unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
VecIdx);
if (trueReg1 == trueReg2)
SwapVector[VecIdx].MentionsPhysVR = 0;
} else {
SwapVector[VecIdx].IsSwappable = 1;
SwapVector[VecIdx].SpecialHandling = SHValues::SH_XXPERMDI;
}
break;
}
case PPC::LVX:
SwapVector[VecIdx].IsLoad = 1;
break;
case PPC::LXVD2X:
case PPC::LXVW4X:
SwapVector[VecIdx].IsLoad = 1;
SwapVector[VecIdx].IsSwap = 1;
break;
case PPC::LXSDX:
case PPC::LXSSPX:
SwapVector[VecIdx].IsLoad = 1;
SwapVector[VecIdx].IsSwappable = 1;
break;
case PPC::STVX:
SwapVector[VecIdx].IsStore = 1;
break;
case PPC::STXVD2X:
case PPC::STXVW4X:
SwapVector[VecIdx].IsStore = 1;
SwapVector[VecIdx].IsSwap = 1;
break;
case PPC::COPY:
if (isVecReg(MI.getOperand(0).getReg()) &&
isVecReg(MI.getOperand(1).getReg()))
SwapVector[VecIdx].IsSwappable = 1;
else if (isScalarVecReg(MI.getOperand(0).getReg()) &&
isScalarVecReg(MI.getOperand(1).getReg()))
SwapVector[VecIdx].IsSwappable = 1;
break;
case PPC::SUBREG_TO_REG: {
if (isVecReg(MI.getOperand(0).getReg()) &&
isVecReg(MI.getOperand(2).getReg()))
SwapVector[VecIdx].IsSwappable = 1;
else if (isVecReg(MI.getOperand(0).getReg()) &&
isScalarVecReg(MI.getOperand(2).getReg())) {
SwapVector[VecIdx].IsSwappable = 1;
SwapVector[VecIdx].SpecialHandling = SHValues::SH_COPYWIDEN;
}
break;
}
case PPC::VSPLTB:
case PPC::VSPLTH:
case PPC::VSPLTW:
SwapVector[VecIdx].IsSwappable = 1;
SwapVector[VecIdx].SpecialHandling = SHValues::SH_SPLAT;
break;
case PPC::INLINEASM:
case PPC::EXTRACT_SUBREG:
case PPC::INSERT_SUBREG:
case PPC::COPY_TO_REGCLASS:
case PPC::LVEBX:
case PPC::LVEHX:
case PPC::LVEWX:
case PPC::LVSL:
case PPC::LVSR:
case PPC::LVXL:
case PPC::STVEBX:
case PPC::STVEHX:
case PPC::STVEWX:
case PPC::STVXL:
case PPC::STXSDX:
case PPC::STXSSPX:
case PPC::VCIPHER:
case PPC::VCIPHERLAST:
case PPC::VMRGHB:
case PPC::VMRGHH:
case PPC::VMRGHW:
case PPC::VMRGLB:
case PPC::VMRGLH:
case PPC::VMRGLW:
case PPC::VMULESB:
case PPC::VMULESH:
case PPC::VMULESW:
case PPC::VMULEUB:
case PPC::VMULEUH:
case PPC::VMULEUW:
case PPC::VMULOSB:
case PPC::VMULOSH:
case PPC::VMULOSW:
case PPC::VMULOUB:
case PPC::VMULOUH:
case PPC::VMULOUW:
case PPC::VNCIPHER:
case PPC::VNCIPHERLAST:
case PPC::VPERM:
case PPC::VPERMXOR:
case PPC::VPKPX:
case PPC::VPKSHSS:
case PPC::VPKSHUS:
case PPC::VPKSDSS:
case PPC::VPKSDUS:
case PPC::VPKSWSS:
case PPC::VPKSWUS:
case PPC::VPKUDUM:
case PPC::VPKUDUS:
case PPC::VPKUHUM:
case PPC::VPKUHUS:
case PPC::VPKUWUM:
case PPC::VPKUWUS:
case PPC::VPMSUMB:
case PPC::VPMSUMD:
case PPC::VPMSUMH:
case PPC::VPMSUMW:
case PPC::VRLB:
case PPC::VRLD:
case PPC::VRLH:
case PPC::VRLW:
case PPC::VSBOX:
case PPC::VSHASIGMAD:
case PPC::VSHASIGMAW:
case PPC::VSL:
case PPC::VSLDOI:
case PPC::VSLO:
case PPC::VSR:
case PPC::VSRO:
case PPC::VSUM2SWS:
case PPC::VSUM4SBS:
case PPC::VSUM4SHS:
case PPC::VSUM4UBS:
case PPC::VSUMSWS:
case PPC::VUPKHPX:
case PPC::VUPKHSB:
case PPC::VUPKHSH:
case PPC::VUPKHSW:
case PPC::VUPKLPX:
case PPC::VUPKLSB:
case PPC::VUPKLSH:
case PPC::VUPKLSW:
case PPC::XXMRGHW:
case PPC::XXMRGLW:
case PPC::XXSLDWI:
case PPC::XXSPLTW:
break;
}
}
}
if (RelevantFunction) {
DEBUG(dbgs() << "Swap vector when first built\n\n");
dumpSwapVector();
}
return RelevantFunction;
}
int PPCVSXSwapRemoval::addSwapEntry(MachineInstr *MI,
PPCVSXSwapEntry& SwapEntry) {
SwapEntry.VSEMI = MI;
SwapEntry.VSEId = SwapVector.size();
SwapVector.push_back(SwapEntry);
EC->insert(SwapEntry.VSEId);
SwapMap[MI] = SwapEntry.VSEId;
return SwapEntry.VSEId;
}
unsigned PPCVSXSwapRemoval::lookThruCopyLike(unsigned SrcReg,
unsigned VecIdx) {
MachineInstr *MI = MRI->getVRegDef(SrcReg);
if (!MI->isCopyLike())
return SrcReg;
unsigned CopySrcReg;
if (MI->isCopy())
CopySrcReg = MI->getOperand(1).getReg();
else {
assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike");
CopySrcReg = MI->getOperand(2).getReg();
}
if (!TargetRegisterInfo::isVirtualRegister(CopySrcReg)) {
if (!isScalarVecReg(CopySrcReg))
SwapVector[VecIdx].MentionsPhysVR = 1;
return CopySrcReg;
}
return lookThruCopyLike(CopySrcReg, VecIdx);
}
void PPCVSXSwapRemoval::formWebs() {
DEBUG(dbgs() << "\n*** Forming webs for swap removal ***\n\n");
for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
DEBUG(dbgs() << "\n" << SwapVector[EntryIdx].VSEId << " ");
DEBUG(MI->dump());
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
if (!isVecReg(Reg) && !isScalarVecReg(Reg))
continue;
if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
if (!(MI->isCopy() && isScalarVecReg(Reg)))
SwapVector[EntryIdx].MentionsPhysVR = 1;
continue;
}
if (!MO.isUse())
continue;
MachineInstr* DefMI = MRI->getVRegDef(Reg);
assert(SwapMap.find(DefMI) != SwapMap.end() &&
"Inconsistency: def of vector reg not found in swap map!");
int DefIdx = SwapMap[DefMI];
(void)EC->unionSets(SwapVector[DefIdx].VSEId,
SwapVector[EntryIdx].VSEId);
DEBUG(dbgs() << format("Unioning %d with %d\n", SwapVector[DefIdx].VSEId,
SwapVector[EntryIdx].VSEId));
DEBUG(dbgs() << " Def: ");
DEBUG(DefMI->dump());
}
}
}
void PPCVSXSwapRemoval::recordUnoptimizableWebs() {
DEBUG(dbgs() << "\n*** Rejecting webs for swap removal ***\n\n");
for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
if (SwapVector[Repr].WebRejected)
continue;
if (SwapVector[EntryIdx].MentionsPhysVR ||
SwapVector[EntryIdx].MentionsPartialVR ||
!(SwapVector[EntryIdx].IsSwappable || SwapVector[EntryIdx].IsSwap)) {
SwapVector[Repr].WebRejected = 1;
DEBUG(dbgs() <<
format("Web %d rejected for physreg, partial reg, or not "
"swap[pable]\n", Repr));
DEBUG(dbgs() << " in " << EntryIdx << ": ");
DEBUG(SwapVector[EntryIdx].VSEMI->dump());
DEBUG(dbgs() << "\n");
}
else if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
unsigned DefReg = MI->getOperand(0).getReg();
for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
int UseIdx = SwapMap[&UseMI];
if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad ||
SwapVector[UseIdx].IsStore) {
SwapVector[Repr].WebRejected = 1;
DEBUG(dbgs() <<
format("Web %d rejected for load not feeding swap\n", Repr));
DEBUG(dbgs() << " def " << EntryIdx << ": ");
DEBUG(MI->dump());
DEBUG(dbgs() << " use " << UseIdx << ": ");
DEBUG(UseMI.dump());
DEBUG(dbgs() << "\n");
}
}
} else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) {
MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
unsigned UseReg = MI->getOperand(0).getReg();
MachineInstr *DefMI = MRI->getVRegDef(UseReg);
int DefIdx = SwapMap[DefMI];
if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
SwapVector[DefIdx].IsStore) {
SwapVector[Repr].WebRejected = 1;
DEBUG(dbgs() <<
format("Web %d rejected for store not fed by swap\n", Repr));
DEBUG(dbgs() << " def " << DefIdx << ": ");
DEBUG(DefMI->dump());
DEBUG(dbgs() << " use " << EntryIdx << ": ");
DEBUG(MI->dump());
DEBUG(dbgs() << "\n");
}
}
}
DEBUG(dbgs() << "Swap vector after web analysis:\n\n");
dumpSwapVector();
}
void PPCVSXSwapRemoval::markSwapsForRemoval() {
DEBUG(dbgs() << "\n*** Marking swaps for removal ***\n\n");
for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
if (!SwapVector[Repr].WebRejected) {
MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
unsigned DefReg = MI->getOperand(0).getReg();
for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) {
int UseIdx = SwapMap[&UseMI];
SwapVector[UseIdx].WillRemove = 1;
DEBUG(dbgs() << "Marking swap fed by load for removal: ");
DEBUG(UseMI.dump());
}
}
} else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) {
int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
if (!SwapVector[Repr].WebRejected) {
MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
unsigned UseReg = MI->getOperand(0).getReg();
MachineInstr *DefMI = MRI->getVRegDef(UseReg);
int DefIdx = SwapMap[DefMI];
SwapVector[DefIdx].WillRemove = 1;
DEBUG(dbgs() << "Marking swap feeding store for removal: ");
DEBUG(DefMI->dump());
}
} else if (SwapVector[EntryIdx].IsSwappable &&
SwapVector[EntryIdx].SpecialHandling != 0) {
int Repr = EC->getLeaderValue(SwapVector[EntryIdx].VSEId);
if (!SwapVector[Repr].WebRejected)
handleSpecialSwappables(EntryIdx);
}
}
}
void PPCVSXSwapRemoval::insertSwap(MachineInstr *MI,
MachineBasicBlock::iterator InsertPoint,
unsigned DstReg, unsigned SrcReg) {
BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
TII->get(PPC::XXPERMDI), DstReg)
.addReg(SrcReg)
.addReg(SrcReg)
.addImm(2);
}
void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) {
switch (SwapVector[EntryIdx].SpecialHandling) {
default:
llvm_unreachable("Unexpected special handling type");
case SHValues::SH_SPLAT: {
MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
unsigned NElts;
DEBUG(dbgs() << "Changing splat: ");
DEBUG(MI->dump());
switch (MI->getOpcode()) {
default:
llvm_unreachable("Unexpected splat opcode");
case PPC::VSPLTB: NElts = 16; break;
case PPC::VSPLTH: NElts = 8; break;
case PPC::VSPLTW: NElts = 4; break;
}
unsigned EltNo = MI->getOperand(1).getImm();
EltNo = (EltNo + NElts / 2) % NElts;
MI->getOperand(1).setImm(EltNo);
DEBUG(dbgs() << " Into: ");
DEBUG(MI->dump());
break;
}
case SHValues::SH_XXPERMDI: {
MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
DEBUG(dbgs() << "Changing XXPERMDI: ");
DEBUG(MI->dump());
unsigned Selector = MI->getOperand(3).getImm();
if (Selector == 0 || Selector == 3)
Selector = 3 - Selector;
MI->getOperand(3).setImm(Selector);
unsigned Reg1 = MI->getOperand(1).getReg();
unsigned Reg2 = MI->getOperand(2).getReg();
MI->getOperand(1).setReg(Reg2);
MI->getOperand(2).setReg(Reg1);
DEBUG(dbgs() << " Into: ");
DEBUG(MI->dump());
break;
}
case SHValues::SH_COPYWIDEN: {
MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
DEBUG(dbgs() << "Changing SUBREG_TO_REG: ");
DEBUG(MI->dump());
unsigned DstReg = MI->getOperand(0).getReg();
const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
unsigned NewVReg = MRI->createVirtualRegister(DstRC);
MI->getOperand(0).setReg(NewVReg);
DEBUG(dbgs() << " Into: ");
DEBUG(MI->dump());
auto InsertPoint = ++MachineBasicBlock::iterator(MI);
if (DstRC == &PPC::VRRCRegClass) {
unsigned VSRCTmp1 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
unsigned VSRCTmp2 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
TII->get(PPC::COPY), VSRCTmp1)
.addReg(NewVReg);
DEBUG(std::prev(InsertPoint)->dump());
insertSwap(MI, InsertPoint, VSRCTmp2, VSRCTmp1);
DEBUG(std::prev(InsertPoint)->dump());
BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
TII->get(PPC::COPY), DstReg)
.addReg(VSRCTmp2);
DEBUG(std::prev(InsertPoint)->dump());
} else {
insertSwap(MI, InsertPoint, DstReg, NewVReg);
DEBUG(std::prev(InsertPoint)->dump());
}
break;
}
}
}
bool PPCVSXSwapRemoval::removeSwaps() {
DEBUG(dbgs() << "\n*** Removing swaps ***\n\n");
bool Changed = false;
for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
if (SwapVector[EntryIdx].WillRemove) {
Changed = true;
MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
MachineBasicBlock *MBB = MI->getParent();
BuildMI(*MBB, MI, MI->getDebugLoc(),
TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
.addOperand(MI->getOperand(1));
DEBUG(dbgs() << format("Replaced %d with copy: ",
SwapVector[EntryIdx].VSEId));
DEBUG(MI->dump());
MI->eraseFromParent();
}
}
return Changed;
}
void PPCVSXSwapRemoval::dumpSwapVector() {
for (unsigned EntryIdx = 0; EntryIdx < SwapVector.size(); ++EntryIdx) {
MachineInstr *MI = SwapVector[EntryIdx].VSEMI;
int ID = SwapVector[EntryIdx].VSEId;
DEBUG(dbgs() << format("%6d", ID));
DEBUG(dbgs() << format("%6d", EC->getLeaderValue(ID)));
DEBUG(dbgs() << format(" BB#%3d", MI->getParent()->getNumber()));
DEBUG(dbgs() << format(" %14s ", TII->getName(MI->getOpcode())));
if (SwapVector[EntryIdx].IsLoad)
DEBUG(dbgs() << "load ");
if (SwapVector[EntryIdx].IsStore)
DEBUG(dbgs() << "store ");
if (SwapVector[EntryIdx].IsSwap)
DEBUG(dbgs() << "swap ");
if (SwapVector[EntryIdx].MentionsPhysVR)
DEBUG(dbgs() << "physreg ");
if (SwapVector[EntryIdx].MentionsPartialVR)
DEBUG(dbgs() << "partialreg ");
if (SwapVector[EntryIdx].IsSwappable) {
DEBUG(dbgs() << "swappable ");
switch(SwapVector[EntryIdx].SpecialHandling) {
default:
DEBUG(dbgs() << "special:**unknown**");
break;
case SH_NONE:
break;
case SH_EXTRACT:
DEBUG(dbgs() << "special:extract ");
break;
case SH_INSERT:
DEBUG(dbgs() << "special:insert ");
break;
case SH_NOSWAP_LD:
DEBUG(dbgs() << "special:load ");
break;
case SH_NOSWAP_ST:
DEBUG(dbgs() << "special:store ");
break;
case SH_SPLAT:
DEBUG(dbgs() << "special:splat ");
break;
case SH_XXPERMDI:
DEBUG(dbgs() << "special:xxpermdi ");
break;
case SH_COPYWIDEN:
DEBUG(dbgs() << "special:copywiden ");
break;
}
}
if (SwapVector[EntryIdx].WebRejected)
DEBUG(dbgs() << "rejected ");
if (SwapVector[EntryIdx].WillRemove)
DEBUG(dbgs() << "remove ");
DEBUG(dbgs() << "\n");
(void)MI;
(void)ID;
}
DEBUG(dbgs() << "\n");
}
}
INITIALIZE_PASS_BEGIN(PPCVSXSwapRemoval, DEBUG_TYPE,
"PowerPC VSX Swap Removal", false, false)
INITIALIZE_PASS_END(PPCVSXSwapRemoval, DEBUG_TYPE,
"PowerPC VSX Swap Removal", false, false)
char PPCVSXSwapRemoval::ID = 0;
FunctionPass*
llvm::createPPCVSXSwapRemovalPass() { return new PPCVSXSwapRemoval(); }