NVPTXInstrInfo.cpp [plain text]
#include "NVPTX.h"
#include "NVPTXInstrInfo.h"
#include "NVPTXTargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/Function.h"
using namespace llvm;
#define GET_INSTRINFO_CTOR_DTOR
#include "NVPTXGenInstrInfo.inc"
void NVPTXInstrInfo::anchor() {}
NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}
void NVPTXInstrInfo::copyPhysReg(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
if (DestRC->getSize() != SrcRC->getSize())
report_fatal_error("Copy one register into another with a different width");
unsigned Op;
if (DestRC == &NVPTX::Int1RegsRegClass) {
Op = NVPTX::IMOV1rr;
} else if (DestRC == &NVPTX::Int16RegsRegClass) {
Op = NVPTX::IMOV16rr;
} else if (DestRC == &NVPTX::Int32RegsRegClass) {
Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
: NVPTX::BITCONVERT_32_F2I);
} else if (DestRC == &NVPTX::Int64RegsRegClass) {
Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
: NVPTX::BITCONVERT_64_F2I);
} else if (DestRC == &NVPTX::Float32RegsRegClass) {
Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
: NVPTX::BITCONVERT_32_I2F);
} else if (DestRC == &NVPTX::Float64RegsRegClass) {
Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
: NVPTX::BITCONVERT_64_I2F);
} else {
llvm_unreachable("Bad register copy");
}
BuildMI(MBB, I, DL, get(Op), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
}
bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
unsigned &DestReg) const {
bool isMove = false;
unsigned TSFlags =
(MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
isMove = (TSFlags == 1);
if (isMove) {
MachineOperand dest = MI.getOperand(0);
MachineOperand src = MI.getOperand(1);
assert(dest.isReg() && "dest of a movrr is not a reg");
assert(src.isReg() && "src of a movrr is not a reg");
SrcReg = src.getReg();
DestReg = dest.getReg();
return true;
}
return false;
}
bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
unsigned &AddrSpace) const {
bool isLoad = false;
unsigned TSFlags =
(MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
isLoad = (TSFlags == 1);
if (isLoad)
AddrSpace = getLdStCodeAddrSpace(MI);
return isLoad;
}
bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
unsigned &AddrSpace) const {
bool isStore = false;
unsigned TSFlags =
(MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
isStore = (TSFlags == 1);
if (isStore)
AddrSpace = getLdStCodeAddrSpace(MI);
return isStore;
}
bool NVPTXInstrInfo::CanTailMerge(const MachineInstr *MI) const {
unsigned addrspace = 0;
if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
return false;
if (isLoadInstr(*MI, addrspace))
if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
return false;
if (isStoreInstr(*MI, addrspace))
if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
return false;
return true;
}
bool NVPTXInstrInfo::AnalyzeBranch(
MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
return false;
MachineInstr *LastInst = I;
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (LastInst->getOpcode() == NVPTX::GOTO) {
TBB = LastInst->getOperand(0).getMBB();
return false;
} else if (LastInst->getOpcode() == NVPTX::CBranch) {
TBB = LastInst->getOperand(1).getMBB();
Cond.push_back(LastInst->getOperand(0));
return false;
}
return true;
}
MachineInstr *SecondLastInst = I;
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
return true;
if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
LastInst->getOpcode() == NVPTX::GOTO) {
TBB = SecondLastInst->getOperand(1).getMBB();
Cond.push_back(SecondLastInst->getOperand(0));
FBB = LastInst->getOperand(0).getMBB();
return false;
}
if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
LastInst->getOpcode() == NVPTX::GOTO) {
TBB = SecondLastInst->getOperand(0).getMBB();
I = LastInst;
if (AllowModify)
I->eraseFromParent();
return false;
}
return true;
}
unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin())
return 0;
--I;
if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
return 0;
I->eraseFromParent();
I = MBB.end();
if (I == MBB.begin())
return 1;
--I;
if (I->getOpcode() != NVPTX::CBranch)
return 1;
I->eraseFromParent();
return 2;
}
unsigned NVPTXInstrInfo::InsertBranch(
MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) &&
"NVPTX branch conditions have two components!");
if (!FBB) {
if (Cond.empty()) BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
else BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
.addMBB(TBB);
return 1;
}
BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
return 2;
}