HexagonInstrInfo.h [plain text]
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
#include "HexagonRegisterInfo.h"
#include "MCTargetDesc/HexagonBaseInfo.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "HexagonGenInstrInfo.inc"
namespace llvm {
struct EVT;
class HexagonSubtarget;
class HexagonInstrInfo : public HexagonGenInstrInfo {
virtual void anchor();
const HexagonRegisterInfo RI;
public:
explicit HexagonInstrInfo(HexagonSubtarget &ST);
unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
DebugLoc DL) const override;
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
unsigned ExtraPredCycles,
BranchProbability Probability) const override;
bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
unsigned NumTCycles, unsigned ExtraTCycles,
MachineBasicBlock &FMBB,
unsigned NumFCycles, unsigned ExtraFCycles,
BranchProbability Probability) const override;
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
BranchProbability Probability) const override;
void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
const override;
void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const override;
bool isPredicated(const MachineInstr *MI) const override;
bool PredicateInstruction(MachineInstr *MI,
ArrayRef<MachineOperand> Cond) const override;
bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
ArrayRef<MachineOperand> Pred2) const override;
bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const override;
bool isPredicable(MachineInstr *MI) const override;
bool isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const override;
unsigned getInlineAsmLength(const char *Str,
const MCAsmInfo &MAI) const override;
ScheduleHazardRecognizer*
CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
const ScheduleDAG *DAG) const override;
bool analyzeCompare(const MachineInstr *MI,
unsigned &SrcReg, unsigned &SrcReg2,
int &Mask, int &Value) const override;
unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
unsigned *PredCost = 0) const override;
DFAPacketizer *
CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
AliasAnalysis *AA = nullptr)
const override;
const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
unsigned createVR(MachineFunction* MF, MVT VT) const;
bool isAbsoluteSet(const MachineInstr* MI) const;
bool isAccumulator(const MachineInstr *MI) const;
bool isComplex(const MachineInstr *MI) const;
bool isCompoundBranchInstr(const MachineInstr *MI) const;
bool isCondInst(const MachineInstr *MI) const;
bool isConditionalALU32 (const MachineInstr* MI) const;
bool isConditionalLoad(const MachineInstr* MI) const;
bool isConditionalStore(const MachineInstr* MI) const;
bool isConditionalTransfer(const MachineInstr* MI) const;
bool isConstExtended(const MachineInstr *MI) const;
bool isDeallocRet(const MachineInstr *MI) const;
bool isDependent(const MachineInstr *ProdMI,
const MachineInstr *ConsMI) const;
bool isDotCurInst(const MachineInstr* MI) const;
bool isDotNewInst(const MachineInstr* MI) const;
bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
bool isEarlySourceInstr(const MachineInstr *MI) const;
bool isEndLoopN(unsigned Opcode) const;
bool isExpr(unsigned OpType) const;
bool isExtendable(const MachineInstr* MI) const;
bool isExtended(const MachineInstr* MI) const;
bool isFloat(const MachineInstr *MI) const;
bool isHVXMemWithAIndirect(const MachineInstr *I,
const MachineInstr *J) const;
bool isIndirectCall(const MachineInstr *MI) const;
bool isIndirectL4Return(const MachineInstr *MI) const;
bool isJumpR(const MachineInstr *MI) const;
bool isJumpWithinBranchRange(const MachineInstr *MI, unsigned offset) const;
bool isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI,
const MachineInstr *ESMI) const;
bool isLateResultInstr(const MachineInstr *MI) const;
bool isLateSourceInstr(const MachineInstr *MI) const;
bool isLoopN(const MachineInstr *MI) const;
bool isMemOp(const MachineInstr *MI) const;
bool isNewValue(const MachineInstr* MI) const;
bool isNewValue(unsigned Opcode) const;
bool isNewValueInst(const MachineInstr* MI) const;
bool isNewValueJump(const MachineInstr* MI) const;
bool isNewValueJump(unsigned Opcode) const;
bool isNewValueStore(const MachineInstr* MI) const;
bool isNewValueStore(unsigned Opcode) const;
bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const;
bool isPostIncrement(const MachineInstr* MI) const;
bool isPredicatedNew(const MachineInstr *MI) const;
bool isPredicatedNew(unsigned Opcode) const;
bool isPredicatedTrue(const MachineInstr *MI) const;
bool isPredicatedTrue(unsigned Opcode) const;
bool isPredicated(unsigned Opcode) const;
bool isPredicateLate(unsigned Opcode) const;
bool isPredictedTaken(unsigned Opcode) const;
bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const;
bool isSolo(const MachineInstr* MI) const;
bool isSpillPredRegOp(const MachineInstr *MI) const;
bool isTC1(const MachineInstr *MI) const;
bool isTC2(const MachineInstr *MI) const;
bool isTC2Early(const MachineInstr *MI) const;
bool isTC4x(const MachineInstr *MI) const;
bool isV60VectorInstruction(const MachineInstr *MI) const;
bool isValidAutoIncImm(const EVT VT, const int Offset) const;
bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
bool isVecAcc(const MachineInstr *MI) const;
bool isVecALU(const MachineInstr *MI) const;
bool isVecUsableNextPacket(const MachineInstr *ProdMI,
const MachineInstr *ConsMI) const;
bool canExecuteInBundle(const MachineInstr *First,
const MachineInstr *Second) const;
bool hasEHLabel(const MachineBasicBlock *B) const;
bool hasNonExtEquivalent(const MachineInstr *MI) const;
bool hasPseudoInstrPair(const MachineInstr *MI) const;
bool hasUncondBranch(const MachineBasicBlock *B) const;
bool mayBeCurLoad(const MachineInstr* MI) const;
bool mayBeNewStore(const MachineInstr* MI) const;
bool producesStall(const MachineInstr *ProdMI,
const MachineInstr *ConsMI) const;
bool producesStall(const MachineInstr *MI,
MachineBasicBlock::const_instr_iterator MII) const;
bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const;
bool PredOpcodeHasJMP_c(unsigned Opcode) const;
bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
unsigned getAddrMode(const MachineInstr* MI) const;
unsigned getBaseAndOffset(const MachineInstr *MI, int &Offset,
unsigned &AccessSize) const;
bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos,
unsigned &OffsetPos) const;
SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
unsigned getCExtOpNum(const MachineInstr *MI) const;
HexagonII::CompoundGroup
getCompoundCandidateGroup(const MachineInstr *MI) const;
unsigned getCompoundOpcode(const MachineInstr *GA,
const MachineInstr *GB) const;
int getCondOpcode(int Opc, bool sense) const;
int getDotCurOp(const MachineInstr* MI) const;
int getDotNewOp(const MachineInstr* MI) const;
int getDotNewPredJumpOp(const MachineInstr *MI,
const MachineBranchProbabilityInfo *MBPI) const;
int getDotNewPredOp(const MachineInstr *MI,
const MachineBranchProbabilityInfo *MBPI) const;
int getDotOldOp(const int opc) const;
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr *MI)
const;
short getEquivalentHWInstr(const MachineInstr *MI) const;
MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const;
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI) const;
bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
unsigned getInvertedPredicatedOpcode(const int Opc) const;
int getMaxValue(const MachineInstr *MI) const;
unsigned getMemAccessSize(const MachineInstr* MI) const;
int getMinValue(const MachineInstr *MI) const;
short getNonExtOpcode(const MachineInstr *MI) const;
bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
unsigned &PredRegPos, unsigned &PredRegFlags) const;
short getPseudoInstrPair(const MachineInstr *MI) const;
short getRegForm(const MachineInstr *MI) const;
unsigned getSize(const MachineInstr *MI) const;
uint64_t getType(const MachineInstr* MI) const;
unsigned getUnits(const MachineInstr* MI) const;
unsigned getValidSubTargets(const unsigned Opcode) const;
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
void immediateExtend(MachineInstr *MI) const;
bool invertAndChangeJumpTarget(MachineInstr* MI,
MachineBasicBlock* NewTarget) const;
void genAllInsnTimingClasses(MachineFunction &MF) const;
bool reversePredSense(MachineInstr* MI) const;
unsigned reversePrediction(unsigned Opcode) const;
bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
};
}
#endif