#ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
#define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
#include "AMDGPURegisterInfo.h"
#include "AMDGPUSubtarget.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
namespace llvm {
struct SIRegisterInfo : public AMDGPURegisterInfo {
private:
unsigned SGPR32SetID;
unsigned VGPR32SetID;
void reserveRegisterTuples(BitVector &, unsigned Reg) const;
public:
SIRegisterInfo();
unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
unsigned reservedPrivateSegmentWaveByteOffsetReg(
const MachineFunction &MF) const;
BitVector getReservedRegs(const MachineFunction &MF) const override;
unsigned getRegPressureSetLimit(const MachineFunction &MF,
unsigned Idx) const override;
bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS) const override;
unsigned getHWRegIndex(unsigned Reg) const override;
const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
bool isSGPRClass(const TargetRegisterClass *RC) const {
return !hasVGPRs(RC);
}
bool isSGPRClassID(unsigned RCID) const {
return isSGPRClass(getRegClass(RCID));
}
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
if (TargetRegisterInfo::isVirtualRegister(Reg))
return isSGPRClass(MRI.getRegClass(Reg));
return getPhysRegClass(Reg);
}
bool hasVGPRs(const TargetRegisterClass *RC) const;
static bool isPseudoRegClass(const TargetRegisterClass *RC) {
return RC == &AMDGPU::VS_32RegClass || RC == &AMDGPU::VS_64RegClass;
}
const TargetRegisterClass *getEquivalentVGPRClass(
const TargetRegisterClass *SRC) const;
const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
unsigned SubIdx) const;
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
unsigned DefSubReg,
const TargetRegisterClass *SrcRC,
unsigned SrcSubReg) const override;
unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
unsigned Channel) const;
bool opCanUseLiteralConstant(unsigned OpType) const;
bool opCanUseInlineConstant(unsigned OpType) const;
enum PreloadedValue {
PRIVATE_SEGMENT_BUFFER = 0,
DISPATCH_PTR = 1,
QUEUE_PTR = 2,
KERNARG_SEGMENT_PTR = 3,
WORKGROUP_ID_X = 10,
WORKGROUP_ID_Y = 11,
WORKGROUP_ID_Z = 12,
PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14,
FIRST_VGPR_VALUE = 15,
WORKITEM_ID_X = FIRST_VGPR_VALUE,
WORKITEM_ID_Y = 16,
WORKITEM_ID_Z = 17
};
unsigned getPreloadedValue(const MachineFunction &MF,
enum PreloadedValue Value) const;
unsigned getNumVGPRsAllowed(unsigned WaveCount) const;
unsigned getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen,
unsigned WaveCount) const;
unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
const TargetRegisterClass *RC) const;
unsigned getSGPR32PressureSet() const { return SGPR32SetID; };
unsigned getVGPR32PressureSet() const { return VGPR32SetID; };
private:
void buildScratchLoadStore(MachineBasicBlock::iterator MI,
unsigned LoadStoreOp, unsigned Value,
unsigned ScratchRsrcReg, unsigned ScratchOffset,
int64_t Offset, RegScavenger *RS) const;
};
}
#endif