AggressiveAntiDepBreaker.h [plain text]
#ifndef LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
#define LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
#include "AntiDepBreaker.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <map>
namespace llvm {
class RegisterClassInfo;
class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepState {
public:
typedef struct {
MachineOperand *Operand;
const TargetRegisterClass *RC;
} RegisterReference;
private:
const unsigned NumTargetRegs;
std::vector<unsigned> GroupNodes;
std::vector<unsigned> GroupNodeIndices;
std::multimap<unsigned, RegisterReference> RegRefs;
std::vector<unsigned> KillIndices;
std::vector<unsigned> DefIndices;
public:
AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB);
std::vector<unsigned> &GetKillIndices() { return KillIndices; }
std::vector<unsigned> &GetDefIndices() { return DefIndices; }
std::multimap<unsigned, RegisterReference>& GetRegRefs() { return RegRefs; }
unsigned GetGroup(unsigned Reg);
void GetGroupRegs(
unsigned Group,
std::vector<unsigned> &Regs,
std::multimap<unsigned,
AggressiveAntiDepState::RegisterReference> *RegRefs);
unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
unsigned LeaveGroup(unsigned Reg);
bool IsLive(unsigned Reg);
};
class LLVM_LIBRARY_VISIBILITY AggressiveAntiDepBreaker
: public AntiDepBreaker {
MachineFunction& MF;
MachineRegisterInfo &MRI;
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
const RegisterClassInfo &RegClassInfo;
BitVector CriticalPathSet;
AggressiveAntiDepState *State;
public:
AggressiveAntiDepBreaker(MachineFunction& MFi,
const RegisterClassInfo &RCI,
TargetSubtargetInfo::RegClassVector& CriticalPathRCs);
~AggressiveAntiDepBreaker() override;
void StartBlock(MachineBasicBlock *BB) override;
unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex,
DbgValueVector &DbgValues) override;
void Observe(MachineInstr *MI, unsigned Count,
unsigned InsertPosIndex) override;
void FinishBlock() override;
private:
typedef std::map<const TargetRegisterClass *, unsigned> RenameOrderType;
bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO);
void GetPassthruRegs(MachineInstr *MI, std::set<unsigned>& PassthruRegs);
void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag,
const char *header = nullptr,
const char *footer = nullptr);
void PrescanInstruction(MachineInstr *MI, unsigned Count,
std::set<unsigned>& PassthruRegs);
void ScanInstruction(MachineInstr *MI, unsigned Count);
BitVector GetRenameRegisters(unsigned Reg);
bool FindSuitableFreeRegisters(unsigned AntiDepGroupIndex,
RenameOrderType& RenameOrder,
std::map<unsigned, unsigned> &RenameMap);
};
}
#endif