AArch64CollectLOH.cpp [plain text]
#include "AArch64.h"
#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64Subtarget.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
#define DEBUG_TYPE "aarch64-collect-loh"
static cl::opt<bool>
PreCollectRegister("aarch64-collect-loh-pre-collect-register", cl::Hidden,
cl::desc("Restrict analysis to registers invovled"
" in LOHs"),
cl::init(true));
static cl::opt<bool>
BasicBlockScopeOnly("aarch64-collect-loh-bb-only", cl::Hidden,
cl::desc("Restrict analysis at basic block scope"),
cl::init(true));
STATISTIC(NumADRPSimpleCandidate,
"Number of simplifiable ADRP dominate by another");
STATISTIC(NumADRPComplexCandidate2,
"Number of simplifiable ADRP reachable by 2 defs");
STATISTIC(NumADRPComplexCandidate3,
"Number of simplifiable ADRP reachable by 3 defs");
STATISTIC(NumADRPComplexCandidateOther,
"Number of simplifiable ADRP reachable by 4 or more defs");
STATISTIC(NumADDToSTRWithImm,
"Number of simplifiable STR with imm reachable by ADD");
STATISTIC(NumLDRToSTRWithImm,
"Number of simplifiable STR with imm reachable by LDR");
STATISTIC(NumADDToSTR, "Number of simplifiable STR reachable by ADD");
STATISTIC(NumLDRToSTR, "Number of simplifiable STR reachable by LDR");
STATISTIC(NumADDToLDRWithImm,
"Number of simplifiable LDR with imm reachable by ADD");
STATISTIC(NumLDRToLDRWithImm,
"Number of simplifiable LDR with imm reachable by LDR");
STATISTIC(NumADDToLDR, "Number of simplifiable LDR reachable by ADD");
STATISTIC(NumLDRToLDR, "Number of simplifiable LDR reachable by LDR");
STATISTIC(NumADRPToLDR, "Number of simplifiable LDR reachable by ADRP");
STATISTIC(NumCplxLvl1, "Number of complex case of level 1");
STATISTIC(NumTooCplxLvl1, "Number of too complex case of level 1");
STATISTIC(NumCplxLvl2, "Number of complex case of level 2");
STATISTIC(NumTooCplxLvl2, "Number of too complex case of level 2");
STATISTIC(NumADRSimpleCandidate, "Number of simplifiable ADRP + ADD");
STATISTIC(NumADRComplexCandidate, "Number of too complex ADRP + ADD");
namespace llvm {
void initializeAArch64CollectLOHPass(PassRegistry &);
}
namespace {
struct AArch64CollectLOH : public MachineFunctionPass {
static char ID;
AArch64CollectLOH() : MachineFunctionPass(ID) {
initializeAArch64CollectLOHPass(*PassRegistry::getPassRegistry());
}
bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const override {
return "AArch64 Collect Linker Optimization Hint (LOH)";
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
AU.addRequired<MachineDominatorTree>();
}
private:
};
typedef SetVector<const MachineInstr *> SetOfMachineInstr;
typedef MapVector<const MachineBasicBlock *,
std::unique_ptr<SetOfMachineInstr[]>>
BlockToSetOfInstrsPerColor;
typedef MapVector<const MachineBasicBlock *,
std::unique_ptr<const MachineInstr *[]>>
BlockToInstrPerColor;
typedef MapVector<const MachineInstr *, SetOfMachineInstr> InstrToInstrs;
typedef MapVector<const MachineBasicBlock *, BitVector> BlockToRegSet;
typedef DenseMap<unsigned, unsigned> MapRegToId;
typedef SmallVector<unsigned, 32> MapIdToReg;
}
char AArch64CollectLOH::ID = 0;
INITIALIZE_PASS_BEGIN(AArch64CollectLOH, "aarch64-collect-loh",
"AArch64 Collect Linker Optimization Hint (LOH)", false,
false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_END(AArch64CollectLOH, "aarch64-collect-loh",
"AArch64 Collect Linker Optimization Hint (LOH)", false,
false)
static SetOfMachineInstr &getSet(BlockToSetOfInstrsPerColor &sets,
const MachineBasicBlock &MBB, unsigned reg,
unsigned nbRegs) {
SetOfMachineInstr *result;
BlockToSetOfInstrsPerColor::iterator it = sets.find(&MBB);
if (it != sets.end())
result = it->second.get();
else
result = (sets[&MBB] = make_unique<SetOfMachineInstr[]>(nbRegs)).get();
return result[reg];
}
static SetOfMachineInstr &getUses(InstrToInstrs *sets, unsigned reg,
const MachineInstr &MI) {
return sets[reg][&MI];
}
static const SetOfMachineInstr *getUses(const InstrToInstrs *sets, unsigned reg,
const MachineInstr &MI) {
InstrToInstrs::const_iterator Res = sets[reg].find(&MI);
if (Res != sets[reg].end())
return &(Res->second);
return nullptr;
}
static void initReachingDef(MachineFunction &MF,
InstrToInstrs *ColorOpToReachedUses,
BlockToInstrPerColor &Gen, BlockToRegSet &Kill,
BlockToSetOfInstrsPerColor &ReachableUses,
const MapRegToId &RegToId,
const MachineInstr *DummyOp, bool ADRPMode) {
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
unsigned NbReg = RegToId.size();
for (MachineBasicBlock &MBB : MF) {
auto &BBGen = Gen[&MBB];
BBGen = make_unique<const MachineInstr *[]>(NbReg);
std::fill(BBGen.get(), BBGen.get() + NbReg, nullptr);
BitVector &BBKillSet = Kill[&MBB];
BBKillSet.resize(NbReg);
for (const MachineInstr &MI : MBB) {
bool IsADRP = MI.getOpcode() == AArch64::ADRP;
if (IsADRP || !ADRPMode)
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || (!ADRPMode && !MO.isUse()) ||
(ADRPMode && (!IsADRP || !MO.isDef())))
continue;
unsigned CurReg = MO.getReg();
MapRegToId::const_iterator ItCurRegId = RegToId.find(CurReg);
if (ItCurRegId == RegToId.end())
continue;
CurReg = ItCurRegId->second;
if (!BBGen[CurReg] && !BBKillSet.test(CurReg))
getSet(ReachableUses, MBB, CurReg, NbReg).insert(&MI);
if (BBGen[CurReg])
getUses(ColorOpToReachedUses, CurReg, *BBGen[CurReg]).insert(&MI);
}
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isRegMask())
continue;
const uint32_t *PreservedRegs = MO.getRegMask();
for (const auto Entry : RegToId) {
unsigned Reg = Entry.second;
if (MachineOperand::clobbersPhysReg(PreservedRegs, Entry.first)) {
BBGen[Reg] = ADRPMode ? &MI : nullptr;
BBKillSet.set(Reg);
}
}
}
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
unsigned CurReg = MO.getReg();
MapRegToId::const_iterator ItCurRegId = RegToId.find(CurReg);
if (ItCurRegId == RegToId.end())
continue;
for (MCRegAliasIterator AI(CurReg, TRI, true); AI.isValid(); ++AI) {
MapRegToId::const_iterator ItRegId = RegToId.find(*AI);
assert(ItRegId != RegToId.end() &&
"Sub-register of an "
"involved register, not recorded as involved!");
BBKillSet.set(ItRegId->second);
BBGen[ItRegId->second] = &MI;
}
BBGen[ItCurRegId->second] = &MI;
}
}
if (!ADRPMode && DummyOp && !MBB.succ_empty())
for (unsigned CurReg = 0; CurReg < NbReg; ++CurReg)
if (BBGen[CurReg])
getUses(ColorOpToReachedUses, CurReg, *BBGen[CurReg]).insert(DummyOp);
}
}
static void reachingDefAlgorithm(MachineFunction &MF,
InstrToInstrs *ColorOpToReachedUses,
BlockToSetOfInstrsPerColor &In,
BlockToSetOfInstrsPerColor &Out,
BlockToInstrPerColor &Gen, BlockToRegSet &Kill,
BlockToSetOfInstrsPerColor &ReachableUses,
unsigned NbReg) {
bool HasChanged;
do {
HasChanged = false;
for (MachineBasicBlock &MBB : MF) {
unsigned CurReg;
for (CurReg = 0; CurReg < NbReg; ++CurReg) {
SetOfMachineInstr &BBInSet = getSet(In, MBB, CurReg, NbReg);
SetOfMachineInstr &BBReachableUses =
getSet(ReachableUses, MBB, CurReg, NbReg);
SetOfMachineInstr &BBOutSet = getSet(Out, MBB, CurReg, NbReg);
unsigned Size = BBOutSet.size();
for (MachineBasicBlock *PredMBB : MBB.predecessors()) {
SetOfMachineInstr &PredOutSet = getSet(Out, *PredMBB, CurReg, NbReg);
BBInSet.insert(PredOutSet.begin(), PredOutSet.end());
}
for (const MachineInstr *MI : BBInSet) {
SetOfMachineInstr &OpReachedUses =
getUses(ColorOpToReachedUses, CurReg, *MI);
OpReachedUses.insert(BBReachableUses.begin(), BBReachableUses.end());
}
if (!Kill[&MBB].test(CurReg))
BBOutSet.insert(BBInSet.begin(), BBInSet.end());
if (Gen[&MBB][CurReg])
BBOutSet.insert(Gen[&MBB][CurReg]);
HasChanged |= BBOutSet.size() != Size;
}
}
} while (HasChanged);
}
static void reachingDef(MachineFunction &MF,
InstrToInstrs *ColorOpToReachedUses,
const MapRegToId &RegToId, bool ADRPMode = false,
const MachineInstr *DummyOp = nullptr) {
BlockToSetOfInstrsPerColor Out, In, ReachableUses;
BlockToInstrPerColor Gen;
BlockToRegSet Kill;
initReachingDef(MF, ColorOpToReachedUses, Gen, Kill, ReachableUses, RegToId,
DummyOp, ADRPMode);
if (!DummyOp)
reachingDefAlgorithm(MF, ColorOpToReachedUses, In, Out, Gen, Kill,
ReachableUses, RegToId.size());
}
#ifndef NDEBUG
static void printReachingDef(const InstrToInstrs *ColorOpToReachedUses,
unsigned NbReg, const TargetRegisterInfo *TRI,
const MapIdToReg &IdToReg) {
unsigned CurReg;
for (CurReg = 0; CurReg < NbReg; ++CurReg) {
if (ColorOpToReachedUses[CurReg].empty())
continue;
DEBUG(dbgs() << "*** Reg " << PrintReg(IdToReg[CurReg], TRI) << " ***\n");
for (const auto &DefsIt : ColorOpToReachedUses[CurReg]) {
DEBUG(dbgs() << "Def:\n");
DEBUG(DefsIt.first->print(dbgs()));
DEBUG(dbgs() << "Reachable uses:\n");
for (const MachineInstr *MI : DefsIt.second) {
DEBUG(MI->print(dbgs()));
}
}
}
}
#endif // NDEBUG
static bool canDefBePartOfLOH(const MachineInstr *Def) {
unsigned Opc = Def->getOpcode();
switch (Opc) {
default:
return false;
case AArch64::ADRP:
return true;
case AArch64::ADDXri:
switch (Def->getOperand(2).getType()) {
default:
return false;
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_JumpTableIndex:
case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_BlockAddress:
return true;
}
case AArch64::LDRXui:
switch (Def->getOperand(2).getType()) {
default:
return false;
case MachineOperand::MO_GlobalAddress:
return true;
}
}
return false;
}
static bool isCandidateStore(const MachineInstr *Instr) {
switch (Instr->getOpcode()) {
default:
return false;
case AArch64::STRBui:
case AArch64::STRHui:
case AArch64::STRWui:
case AArch64::STRXui:
case AArch64::STRSui:
case AArch64::STRDui:
case AArch64::STRQui:
if (Instr->getOperand(0).getReg() != Instr->getOperand(1).getReg())
return true;
}
return false;
}
static void reachedUsesToDefs(InstrToInstrs &UseToReachingDefs,
const InstrToInstrs *ColorOpToReachedUses,
const MapRegToId &RegToId,
bool ADRPMode = false) {
SetOfMachineInstr NotCandidate;
unsigned NbReg = RegToId.size();
MapRegToId::const_iterator EndIt = RegToId.end();
for (unsigned CurReg = 0; CurReg < NbReg; ++CurReg) {
if (ColorOpToReachedUses[CurReg].empty())
continue;
for (const auto &DefsIt : ColorOpToReachedUses[CurReg]) {
for (const MachineInstr *MI : DefsIt.second) {
const MachineInstr *Def = DefsIt.first;
MapRegToId::const_iterator It;
if ((ADRPMode && Def->getOpcode() != AArch64::ADRP) ||
(!ADRPMode && !canDefBePartOfLOH(Def)) ||
(!ADRPMode && isCandidateStore(MI) &&
((It = RegToId.find((MI)->getOperand(1).getReg())) == EndIt ||
It->second != CurReg))) {
NotCandidate.insert(MI);
continue;
}
if (!ADRPMode || MI != DefsIt.first) {
UseToReachingDefs[MI].insert(DefsIt.first);
if (!ADRPMode && UseToReachingDefs[MI].size() > 1)
NotCandidate.insert(MI);
}
}
}
}
for (const MachineInstr *Elem : NotCandidate) {
DEBUG(dbgs() << "Too many reaching defs: " << *Elem << "\n");
UseToReachingDefs[Elem].clear();
}
}
static void computeADRP(const InstrToInstrs &UseToDefs,
AArch64FunctionInfo &AArch64FI,
const MachineDominatorTree *MDT) {
DEBUG(dbgs() << "*** Compute LOH for ADRP\n");
for (const auto &Entry : UseToDefs) {
unsigned Size = Entry.second.size();
if (Size == 0)
continue;
if (Size == 1) {
const MachineInstr *L2 = *Entry.second.begin();
const MachineInstr *L1 = Entry.first;
if (!MDT->dominates(L2, L1)) {
DEBUG(dbgs() << "Dominance check failed:\n" << *L2 << '\n' << *L1
<< '\n');
continue;
}
DEBUG(dbgs() << "Record AdrpAdrp:\n" << *L2 << '\n' << *L1 << '\n');
SmallVector<const MachineInstr *, 2> Args;
Args.push_back(L2);
Args.push_back(L1);
AArch64FI.addLOHDirective(MCLOH_AdrpAdrp, Args);
++NumADRPSimpleCandidate;
}
#ifdef DEBUG
else if (Size == 2)
++NumADRPComplexCandidate2;
else if (Size == 3)
++NumADRPComplexCandidate3;
else
++NumADRPComplexCandidateOther;
#endif
assert(Size >= 1 && "No reaching defs for that use!");
}
}
static bool isCandidateLoad(const MachineInstr *Instr) {
switch (Instr->getOpcode()) {
default:
return false;
case AArch64::LDRSBWui:
case AArch64::LDRSBXui:
case AArch64::LDRSHWui:
case AArch64::LDRSHXui:
case AArch64::LDRSWui:
case AArch64::LDRBui:
case AArch64::LDRHui:
case AArch64::LDRWui:
case AArch64::LDRXui:
case AArch64::LDRSui:
case AArch64::LDRDui:
case AArch64::LDRQui:
if (Instr->getOperand(2).getTargetFlags() & AArch64II::MO_GOT)
return false;
return true;
}
return false;
}
static bool supportLoadFromLiteral(const MachineInstr *Instr) {
switch (Instr->getOpcode()) {
default:
return false;
case AArch64::LDRSWui:
case AArch64::LDRWui:
case AArch64::LDRXui:
case AArch64::LDRSui:
case AArch64::LDRDui:
case AArch64::LDRQui:
return true;
}
return false;
}
static bool isCandidate(const MachineInstr *Instr,
const InstrToInstrs &UseToDefs,
const MachineDominatorTree *MDT) {
if (!isCandidateLoad(Instr) && !isCandidateStore(Instr))
return false;
const MachineInstr *Def = *UseToDefs.find(Instr)->second.begin();
if (Def->getOpcode() != AArch64::ADRP) {
if (!MDT->dominates(Def, Instr))
return false;
if (UseToDefs.find(Def) ==
UseToDefs.end()
||
UseToDefs.find(Def)->second.empty())
return false;
Instr = Def;
Def = *UseToDefs.find(Def)->second.begin();
}
if (Def->getOpcode() == AArch64::ADRP)
return MDT->dominates(Def, Instr);
return false;
}
static bool registerADRCandidate(const MachineInstr &Use,
const InstrToInstrs &UseToDefs,
const InstrToInstrs *DefsPerColorToUses,
AArch64FunctionInfo &AArch64FI,
SetOfMachineInstr *InvolvedInLOHs,
const MapRegToId &RegToId) {
if (Use.getOpcode() != AArch64::ADDXri &&
(Use.getOpcode() != AArch64::LDRXui ||
!(Use.getOperand(2).getTargetFlags() & AArch64II::MO_GOT)))
return false;
InstrToInstrs::const_iterator It = UseToDefs.find(&Use);
if (It == UseToDefs.end() || It->second.empty())
return false;
const MachineInstr &Def = **It->second.begin();
if (Def.getOpcode() != AArch64::ADRP)
return false;
const SetOfMachineInstr *Users =
getUses(DefsPerColorToUses,
RegToId.find(Def.getOperand(0).getReg())->second, Def);
if (Users->size() > 1) {
++NumADRComplexCandidate;
return false;
}
++NumADRSimpleCandidate;
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(&Def)) &&
"ADRP already involved in LOH.");
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(&Use)) &&
"ADD already involved in LOH.");
DEBUG(dbgs() << "Record AdrpAdd\n" << Def << '\n' << Use << '\n');
SmallVector<const MachineInstr *, 2> Args;
Args.push_back(&Def);
Args.push_back(&Use);
AArch64FI.addLOHDirective(Use.getOpcode() == AArch64::ADDXri ? MCLOH_AdrpAdd
: MCLOH_AdrpLdrGot,
Args);
return true;
}
static void computeOthers(const InstrToInstrs &UseToDefs,
const InstrToInstrs *DefsPerColorToUses,
AArch64FunctionInfo &AArch64FI, const MapRegToId &RegToId,
const MachineDominatorTree *MDT) {
SetOfMachineInstr *InvolvedInLOHs = nullptr;
#ifdef DEBUG
SetOfMachineInstr InvolvedInLOHsStorage;
InvolvedInLOHs = &InvolvedInLOHsStorage;
#endif // DEBUG
DEBUG(dbgs() << "*** Compute LOH for Others\n");
SetOfMachineInstr PotentialCandidates;
SetOfMachineInstr PotentialADROpportunities;
for (auto &Use : UseToDefs) {
if (Use.second.empty())
continue;
if (!isCandidate(Use.first, UseToDefs, MDT)) {
PotentialADROpportunities.insert(Use.first);
continue;
}
PotentialCandidates.insert(Use.first);
}
#ifdef DEBUG
SetOfMachineInstr DefsOfPotentialCandidates;
#endif
for (const MachineInstr *Candidate : PotentialCandidates) {
const MachineInstr *Def = *UseToDefs.find(Candidate)->second.begin();
const MachineInstr *L1 = Def;
const MachineInstr *L2 = nullptr;
unsigned ImmediateDefOpc = Def->getOpcode();
if (Def->getOpcode() != AArch64::ADRP) {
const SetOfMachineInstr *Users =
getUses(DefsPerColorToUses,
RegToId.find(Def->getOperand(0).getReg())->second, *Def);
if (Users->size() > 1) {
#ifdef DEBUG
bool IsLevel2 = true;
for (const MachineInstr *MI : *Users) {
if (!PotentialCandidates.count(MI)) {
++NumTooCplxLvl2;
IsLevel2 = false;
break;
}
}
if (IsLevel2)
++NumCplxLvl2;
#endif // DEBUG
PotentialADROpportunities.insert(Def);
continue;
}
L2 = Def;
Def = *UseToDefs.find(Def)->second.begin();
L1 = Def;
}
const SetOfMachineInstr *Users =
getUses(DefsPerColorToUses,
RegToId.find(Def->getOperand(0).getReg())->second, *Def);
if (Users->size() > 1) {
#ifdef DEBUG
if (DefsOfPotentialCandidates.empty()) {
DefsOfPotentialCandidates = PotentialCandidates;
for (const MachineInstr *Candidate : PotentialCandidates) {
if (!UseToDefs.find(Candidate)->second.empty())
DefsOfPotentialCandidates.insert(
*UseToDefs.find(Candidate)->second.begin());
}
}
bool Found = false;
for (auto &Use : *Users) {
if (!DefsOfPotentialCandidates.count(Use)) {
++NumTooCplxLvl1;
Found = true;
break;
}
}
if (!Found)
++NumCplxLvl1;
#endif // DEBUG
continue;
}
bool IsL2Add = (ImmediateDefOpc == AArch64::ADDXri);
if (L2 && !IsL2Add && L2->getOperand(2).getTargetFlags() != AArch64II::MO_GOT)
continue;
SmallVector<const MachineInstr *, 3> Args;
MCLOHType Kind;
if (isCandidateLoad(Candidate)) {
if (!L2) {
if (!supportLoadFromLiteral(Candidate))
continue;
DEBUG(dbgs() << "Record AdrpLdr:\n" << *L1 << '\n' << *Candidate
<< '\n');
Kind = MCLOH_AdrpLdr;
Args.push_back(L1);
Args.push_back(Candidate);
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(L1)) &&
"L1 already involved in LOH.");
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(Candidate)) &&
"Candidate already involved in LOH.");
++NumADRPToLDR;
} else {
DEBUG(dbgs() << "Record Adrp" << (IsL2Add ? "Add" : "LdrGot")
<< "Ldr:\n" << *L1 << '\n' << *L2 << '\n' << *Candidate
<< '\n');
Kind = IsL2Add ? MCLOH_AdrpAddLdr : MCLOH_AdrpLdrGotLdr;
Args.push_back(L1);
Args.push_back(L2);
Args.push_back(Candidate);
PotentialADROpportunities.remove(L2);
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(L1)) &&
"L1 already involved in LOH.");
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(L2)) &&
"L2 already involved in LOH.");
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(Candidate)) &&
"Candidate already involved in LOH.");
#ifdef DEBUG
if (Candidate->getOperand(2).getImm() == 0)
if (ImmediateDefOpc == AArch64::ADDXri)
++NumADDToLDR;
else
++NumLDRToLDR;
else if (ImmediateDefOpc == AArch64::ADDXri)
++NumADDToLDRWithImm;
else
++NumLDRToLDRWithImm;
#endif // DEBUG
}
} else {
if (ImmediateDefOpc == AArch64::ADRP)
continue;
else {
DEBUG(dbgs() << "Record Adrp" << (IsL2Add ? "Add" : "LdrGot")
<< "Str:\n" << *L1 << '\n' << *L2 << '\n' << *Candidate
<< '\n');
Kind = IsL2Add ? MCLOH_AdrpAddStr : MCLOH_AdrpLdrGotStr;
Args.push_back(L1);
Args.push_back(L2);
Args.push_back(Candidate);
PotentialADROpportunities.remove(L2);
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(L1)) &&
"L1 already involved in LOH.");
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(L2)) &&
"L2 already involved in LOH.");
assert((!InvolvedInLOHs || InvolvedInLOHs->insert(Candidate)) &&
"Candidate already involved in LOH.");
#ifdef DEBUG
if (Candidate->getOperand(2).getImm() == 0)
if (ImmediateDefOpc == AArch64::ADDXri)
++NumADDToSTR;
else
++NumLDRToSTR;
else if (ImmediateDefOpc == AArch64::ADDXri)
++NumADDToSTRWithImm;
else
++NumLDRToSTRWithImm;
#endif // DEBUG
}
}
AArch64FI.addLOHDirective(Kind, Args);
}
for (const MachineInstr *Candidate : PotentialADROpportunities)
registerADRCandidate(*Candidate, UseToDefs, DefsPerColorToUses, AArch64FI,
InvolvedInLOHs, RegToId);
}
static void collectInvolvedReg(MachineFunction &MF, MapRegToId &RegToId,
MapIdToReg &IdToReg,
const TargetRegisterInfo *TRI) {
unsigned CurRegId = 0;
if (!PreCollectRegister) {
unsigned NbReg = TRI->getNumRegs();
for (; CurRegId < NbReg; ++CurRegId) {
RegToId[CurRegId] = CurRegId;
DEBUG(IdToReg.push_back(CurRegId));
DEBUG(assert(IdToReg[CurRegId] == CurRegId && "Reg index mismatches"));
}
return;
}
DEBUG(dbgs() << "** Collect Involved Register\n");
for (const auto &MBB : MF) {
for (const MachineInstr &MI : MBB) {
if (!canDefBePartOfLOH(&MI))
continue;
for (MachineInstr::const_mop_iterator IO = MI.operands_begin(),
IOEnd = MI.operands_end();
IO != IOEnd; ++IO) {
if (!IO->isReg() || !IO->isDef())
continue;
unsigned CurReg = IO->getReg();
for (MCRegAliasIterator AI(CurReg, TRI, true); AI.isValid(); ++AI)
if (RegToId.find(*AI) == RegToId.end()) {
DEBUG(IdToReg.push_back(*AI);
assert(IdToReg[CurRegId] == *AI &&
"Reg index mismatches insertion index."));
RegToId[*AI] = CurRegId++;
DEBUG(dbgs() << "Register: " << PrintReg(*AI, TRI) << '\n');
}
}
}
}
}
bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) {
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
const MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
MapRegToId RegToId;
MapIdToReg IdToReg;
AArch64FunctionInfo *AArch64FI = MF.getInfo<AArch64FunctionInfo>();
assert(AArch64FI && "No MachineFunctionInfo for this function!");
DEBUG(dbgs() << "Looking for LOH in " << MF.getName() << '\n');
collectInvolvedReg(MF, RegToId, IdToReg, TRI);
if (RegToId.empty())
return false;
MachineInstr *DummyOp = nullptr;
if (BasicBlockScopeOnly) {
const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
DummyOp = MF.CreateMachineInstr(TII->get(AArch64::COPY), DebugLoc());
}
unsigned NbReg = RegToId.size();
bool Modified = false;
InstrToInstrs *ColorOpToReachedUses = new InstrToInstrs[NbReg];
reachingDef(MF, ColorOpToReachedUses, RegToId, true, DummyOp);
DEBUG(dbgs() << "ADRP reaching defs\n");
DEBUG(printReachingDef(ColorOpToReachedUses, NbReg, TRI, IdToReg));
InstrToInstrs ADRPToReachingDefs;
reachedUsesToDefs(ADRPToReachingDefs, ColorOpToReachedUses, RegToId, true);
computeADRP(ADRPToReachingDefs, *AArch64FI, MDT);
delete[] ColorOpToReachedUses;
ColorOpToReachedUses = new InstrToInstrs[NbReg];
reachingDef(MF, ColorOpToReachedUses, RegToId, false, DummyOp);
DEBUG(dbgs() << "All reaching defs\n");
DEBUG(printReachingDef(ColorOpToReachedUses, NbReg, TRI, IdToReg));
InstrToInstrs UsesToReachingDefs;
reachedUsesToDefs(UsesToReachingDefs, ColorOpToReachedUses, RegToId, false);
computeOthers(UsesToReachingDefs, ColorOpToReachedUses, *AArch64FI, RegToId,
MDT);
delete[] ColorOpToReachedUses;
if (BasicBlockScopeOnly)
MF.DeleteMachineInstr(DummyOp);
return Modified;
}
FunctionPass *llvm::createAArch64CollectLOHPass() {
return new AArch64CollectLOH();
}