TargetRegisterInfo.cpp [plain text]
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
regclass_iterator RCB, regclass_iterator RCE,
const char *const *SRINames,
const unsigned *SRILaneMasks,
unsigned SRICoveringLanes)
: InfoDesc(ID), SubRegIndexNames(SRINames),
SubRegIndexLaneMasks(SRILaneMasks),
RegClassBegin(RCB), RegClassEnd(RCE),
CoveringLanes(SRICoveringLanes) {
}
TargetRegisterInfo::~TargetRegisterInfo() {}
void PrintReg::print(raw_ostream &OS) const {
if (!Reg)
OS << "%noreg";
else if (TargetRegisterInfo::isStackSlot(Reg))
OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
else if (TargetRegisterInfo::isVirtualRegister(Reg))
OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
else if (TRI && Reg < TRI->getNumRegs())
OS << '%' << TRI->getName(Reg);
else
OS << "%physreg" << Reg;
if (SubIdx) {
if (TRI)
OS << ':' << TRI->getSubRegIndexName(SubIdx);
else
OS << ":sub(" << SubIdx << ')';
}
}
void PrintRegUnit::print(raw_ostream &OS) const {
if (!TRI) {
OS << "Unit~" << Unit;
return;
}
if (Unit >= TRI->getNumRegUnits()) {
OS << "BadUnit~" << Unit;
return;
}
MCRegUnitRootIterator Roots(Unit, TRI);
assert(Roots.isValid() && "Unit has no roots.");
OS << TRI->getName(*Roots);
for (++Roots; Roots.isValid(); ++Roots)
OS << '~' << TRI->getName(*Roots);
}
void PrintVRegOrUnit::print(raw_ostream &OS) const {
if (TRI && TRI->isVirtualRegister(Unit)) {
OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit);
return;
}
PrintRegUnit::print(OS);
}
const TargetRegisterClass *
TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
if (!RC || RC->isAllocatable())
return RC;
const unsigned *SubClass = RC->getSubClassMask();
for (unsigned Base = 0, BaseE = getNumRegClasses();
Base < BaseE; Base += 32) {
unsigned Idx = Base;
for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
unsigned Offset = countTrailingZeros(Mask);
const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
if (SubRC->isAllocatable())
return SubRC;
Mask >>= Offset;
Idx += Offset + 1;
}
}
return nullptr;
}
const TargetRegisterClass *
TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const {
assert(isPhysicalRegister(reg) && "reg must be a physical register");
const TargetRegisterClass* BestRC = nullptr;
for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
const TargetRegisterClass* RC = *I;
if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
(!BestRC || BestRC->hasSubClass(RC)))
BestRC = RC;
}
assert(BestRC && "Couldn't find the register class");
return BestRC;
}
static void getAllocatableSetForRC(const MachineFunction &MF,
const TargetRegisterClass *RC, BitVector &R){
assert(RC->isAllocatable() && "invalid for nonallocatable sets");
ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
for (unsigned i = 0; i != Order.size(); ++i)
R.set(Order[i]);
}
BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
const TargetRegisterClass *RC) const {
BitVector Allocatable(getNumRegs());
if (RC) {
const TargetRegisterClass *SubClass = getAllocatableClass(RC);
if (SubClass)
getAllocatableSetForRC(MF, SubClass, Allocatable);
} else {
for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
E = regclass_end(); I != E; ++I)
if ((*I)->isAllocatable())
getAllocatableSetForRC(MF, *I, Allocatable);
}
BitVector Reserved = getReservedRegs(MF);
Allocatable &= Reserved.flip();
return Allocatable;
}
static inline
const TargetRegisterClass *firstCommonClass(const uint32_t *A,
const uint32_t *B,
const TargetRegisterInfo *TRI) {
for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
if (unsigned Common = *A++ & *B++)
return TRI->getRegClass(I + countTrailingZeros(Common));
return nullptr;
}
const TargetRegisterClass *
TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
const TargetRegisterClass *B) const {
if (A == B)
return A;
if (!A || !B)
return nullptr;
return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
}
const TargetRegisterClass *
TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
const TargetRegisterClass *B,
unsigned Idx) const {
assert(A && B && "Missing register class");
assert(Idx && "Bad sub-register index");
for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
if (RCI.getSubReg() == Idx)
return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
return nullptr;
}
const TargetRegisterClass *TargetRegisterInfo::
getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
const TargetRegisterClass *RCB, unsigned SubB,
unsigned &PreA, unsigned &PreB) const {
assert(RCA && SubA && RCB && SubB && "Invalid arguments");
const TargetRegisterClass *BestRC = nullptr;
unsigned *BestPreA = &PreA;
unsigned *BestPreB = &PreB;
if (RCA->getSize() < RCB->getSize()) {
std::swap(RCA, RCB);
std::swap(SubA, SubB);
std::swap(BestPreA, BestPreB);
}
unsigned MinSize = RCA->getSize();
for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
const TargetRegisterClass *RC =
firstCommonClass(IA.getMask(), IB.getMask(), this);
if (!RC || RC->getSize() < MinSize)
continue;
unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
if (FinalA != FinalB)
continue;
if (BestRC && RC->getSize() >= BestRC->getSize())
continue;
BestRC = RC;
*BestPreA = IA.getSubReg();
*BestPreB = IB.getSubReg();
if (BestRC->getSize() == MinSize)
return BestRC;
}
}
return BestRC;
}
void
TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
ArrayRef<MCPhysReg> Order,
SmallVectorImpl<MCPhysReg> &Hints,
const MachineFunction &MF,
const VirtRegMap *VRM) const {
const MachineRegisterInfo &MRI = MF.getRegInfo();
std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
assert(Hint.first == 0 && "Target must implement TRI::getRegAllocationHints");
unsigned Phys = Hint.second;
if (VRM && isVirtualRegister(Phys))
Phys = VRM->getPhys(Phys);
if (!isPhysicalRegister(Phys))
return;
if (MRI.isReserved(Phys))
return;
if (std::find(Order.begin(), Order.end(), Phys) == Order.end())
return;
Hints.push_back(Phys);
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
void
TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
const TargetRegisterInfo *TRI) {
dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n";
}
#endif