PeepholeOptimizer.cpp [plain text]
#include "llvm/CodeGen/Passes.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <utility>
using namespace llvm;
#define DEBUG_TYPE "peephole-opt"
static cl::opt<bool>
Aggressive("aggressive-ext-opt", cl::Hidden,
cl::desc("Aggressive extension optimization"));
static cl::opt<bool>
DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
cl::desc("Disable the peephole optimizer"));
static cl::opt<bool>
DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false),
cl::desc("Disable advanced copy optimization"));
STATISTIC(NumReuse, "Number of extension results reused");
STATISTIC(NumCmps, "Number of compares eliminated");
STATISTIC(NumImmFold, "Number of move immediate folded");
STATISTIC(NumLoadFold, "Number of loads folded");
STATISTIC(NumSelects, "Number of selects optimized");
STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized");
STATISTIC(NumRewrittenCopies, "Number of copies rewritten");
namespace {
class PeepholeOptimizer : public MachineFunctionPass {
const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI;
MachineRegisterInfo *MRI;
MachineDominatorTree *DT;
public:
static char ID; PeepholeOptimizer() : MachineFunctionPass(ID) {
initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
}
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU);
if (Aggressive) {
AU.addRequired<MachineDominatorTree>();
AU.addPreserved<MachineDominatorTree>();
}
}
private:
bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
SmallPtrSetImpl<MachineInstr*> &LocalMIs);
bool optimizeSelect(MachineInstr *MI,
SmallPtrSetImpl<MachineInstr *> &LocalMIs);
bool optimizeCondBranch(MachineInstr *MI);
bool optimizeCopyOrBitcast(MachineInstr *MI);
bool optimizeCoalescableCopy(MachineInstr *MI);
bool optimizeUncoalescableCopy(MachineInstr *MI,
SmallPtrSetImpl<MachineInstr *> &LocalMIs);
bool findNextSource(unsigned &Reg, unsigned &SubReg);
bool isMoveImmediate(MachineInstr *MI,
SmallSet<unsigned, 4> &ImmDefRegs,
DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
SmallSet<unsigned, 4> &ImmDefRegs,
DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
bool isLoadFoldable(MachineInstr *MI,
SmallSet<unsigned, 16> &FoldAsLoadDefCandidates);
bool isCoalescableCopy(const MachineInstr &MI) {
return MI.isCopy() || (!DisableAdvCopyOpt &&
(MI.isRegSequence() || MI.isInsertSubreg() ||
MI.isExtractSubreg()));
}
bool isUncoalescableCopy(const MachineInstr &MI) {
return MI.isBitcast() ||
(!DisableAdvCopyOpt &&
(MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
MI.isExtractSubregLike()));
}
};
class ValueTracker {
private:
const MachineInstr *Def;
unsigned DefIdx;
unsigned DefSubReg;
unsigned Reg;
bool UseAdvancedTracking;
const MachineRegisterInfo &MRI;
const TargetInstrInfo *TII;
bool getNextSourceImpl(unsigned &SrcReg, unsigned &SrcSubReg);
bool getNextSourceFromCopy(unsigned &SrcReg, unsigned &SrcSubReg);
bool getNextSourceFromBitcast(unsigned &SrcReg, unsigned &SrcSubReg);
bool getNextSourceFromRegSequence(unsigned &SrcReg, unsigned &SrcSubReg);
bool getNextSourceFromInsertSubreg(unsigned &SrcReg, unsigned &SrcSubReg);
bool getNextSourceFromExtractSubreg(unsigned &SrcReg, unsigned &SrcSubReg);
bool getNextSourceFromSubregToReg(unsigned &SrcReg, unsigned &SrcSubReg);
public:
ValueTracker(unsigned Reg, unsigned DefSubReg,
const MachineRegisterInfo &MRI,
bool UseAdvancedTracking = false,
const TargetInstrInfo *TII = nullptr)
: Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
Def = MRI.getVRegDef(Reg);
DefIdx = MRI.def_begin(Reg).getOperandNo();
}
}
ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
const MachineRegisterInfo &MRI,
bool UseAdvancedTracking = false,
const TargetInstrInfo *TII = nullptr)
: Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
assert(DefIdx < Def->getDesc().getNumDefs() &&
Def->getOperand(DefIdx).isReg() && "Invalid definition");
Reg = Def->getOperand(DefIdx).getReg();
}
const MachineInstr *getNextSource(unsigned &SrcReg, unsigned &SrcSubReg);
unsigned getReg() const { return Reg; }
};
}
char PeepholeOptimizer::ID = 0;
char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
INITIALIZE_PASS_BEGIN(PeepholeOptimizer, "peephole-opts",
"Peephole Optimizations", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts",
"Peephole Optimizations", false, false)
bool PeepholeOptimizer::
optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
SmallPtrSetImpl<MachineInstr*> &LocalMIs) {
unsigned SrcReg, DstReg, SubIdx;
if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
return false;
if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
TargetRegisterInfo::isPhysicalRegister(SrcReg))
return false;
if (MRI->hasOneNonDBGUse(SrcReg))
return false;
const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
if (!DstRC)
return false;
bool UseSrcSubIdx =
TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
ReachedBBs.insert(UI.getParent());
SmallVector<MachineOperand*, 8> Uses;
SmallVector<MachineOperand*, 8> ExtendedUses;
bool ExtendLife = true;
for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
MachineInstr *UseMI = UseMO.getParent();
if (UseMI == MI)
continue;
if (UseMI->isPHI()) {
ExtendLife = false;
continue;
}
if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
continue;
if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
continue;
MachineBasicBlock *UseMBB = UseMI->getParent();
if (UseMBB == MBB) {
if (!LocalMIs.count(UseMI))
Uses.push_back(&UseMO);
} else if (ReachedBBs.count(UseMBB)) {
Uses.push_back(&UseMO);
} else if (Aggressive && DT->dominates(MBB, UseMBB)) {
ExtendedUses.push_back(&UseMO);
} else {
ExtendLife = false;
break;
}
}
if (ExtendLife && !ExtendedUses.empty())
Uses.append(ExtendedUses.begin(), ExtendedUses.end());
bool Changed = false;
if (!Uses.empty()) {
SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
if (UI.isPHI())
PHIBBs.insert(UI.getParent());
const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
MachineOperand *UseMO = Uses[i];
MachineInstr *UseMI = UseMO->getParent();
MachineBasicBlock *UseMBB = UseMI->getParent();
if (PHIBBs.count(UseMBB))
continue;
if (!Changed) {
MRI->clearKillFlags(DstReg);
MRI->constrainRegClass(DstReg, DstRC);
}
unsigned NewVR = MRI->createVirtualRegister(RC);
MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVR)
.addReg(DstReg, 0, SubIdx);
if (UseSrcSubIdx) {
Copy->getOperand(0).setSubReg(SubIdx);
Copy->getOperand(0).setIsUndef();
}
UseMO->setReg(NewVR);
++NumReuse;
Changed = true;
}
}
return Changed;
}
bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr *MI,
MachineBasicBlock *MBB) {
unsigned SrcReg, SrcReg2;
int CmpMask, CmpValue;
if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
(SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
return false;
if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
++NumCmps;
return true;
}
return false;
}
bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI,
SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
unsigned TrueOp = 0;
unsigned FalseOp = 0;
bool Optimizable = false;
SmallVector<MachineOperand, 4> Cond;
if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
return false;
if (!Optimizable)
return false;
if (!TII->optimizeSelect(MI, LocalMIs))
return false;
MI->eraseFromParent();
++NumSelects;
return true;
}
bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) {
return TII->optimizeCondBranch(MI);
}
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
const TargetRegisterClass *DefRC,
unsigned DefSubReg,
const TargetRegisterClass *SrcRC,
unsigned SrcSubReg) {
if (DefRC == SrcRC)
return true;
unsigned SrcIdx, DefIdx;
if (SrcSubReg && DefSubReg)
return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
SrcIdx, DefIdx) != nullptr;
if (!SrcSubReg) {
std::swap(DefSubReg, SrcSubReg);
std::swap(DefRC, SrcRC);
}
if (SrcSubReg)
return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
}
bool PeepholeOptimizer::findNextSource(unsigned &Reg, unsigned &SubReg) {
if (TargetRegisterInfo::isPhysicalRegister(Reg))
return false;
const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
unsigned DefSubReg = SubReg;
unsigned Src;
unsigned SrcSubReg;
bool ShouldRewrite = false;
ValueTracker ValTracker(Reg, DefSubReg, *MRI, !DisableAdvCopyOpt, TII);
do {
unsigned CopySrcReg, CopySrcSubReg;
if (!ValTracker.getNextSource(CopySrcReg, CopySrcSubReg))
break;
Src = CopySrcReg;
SrcSubReg = CopySrcSubReg;
if (TargetRegisterInfo::isPhysicalRegister(Src))
break;
const TargetRegisterClass *SrcRC = MRI->getRegClass(Src);
ShouldRewrite = shareSameRegisterFile(*TRI, DefRC, DefSubReg, SrcRC,
SrcSubReg);
} while (!ShouldRewrite);
if (!ShouldRewrite || Src == Reg)
return false;
Reg = Src;
SubReg = SrcSubReg;
return true;
}
namespace {
class CopyRewriter {
protected:
MachineInstr &CopyLike;
unsigned CurrentSrcIdx;
public:
CopyRewriter(MachineInstr &MI) : CopyLike(MI), CurrentSrcIdx(0) {}
virtual ~CopyRewriter() {}
virtual bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
unsigned &TrackReg,
unsigned &TrackSubReg) {
if (!CopyLike.isCopy() || CurrentSrcIdx == 1)
return false;
CurrentSrcIdx = 1;
const MachineOperand &MOSrc = CopyLike.getOperand(1);
SrcReg = MOSrc.getReg();
SrcSubReg = MOSrc.getSubReg();
const MachineOperand &MODef = CopyLike.getOperand(0);
TrackReg = MODef.getReg();
TrackSubReg = MODef.getSubReg();
return true;
}
virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) {
if (!CopyLike.isCopy() || CurrentSrcIdx != 1)
return false;
MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
MOSrc.setReg(NewReg);
MOSrc.setSubReg(NewSubReg);
return true;
}
};
class InsertSubregRewriter : public CopyRewriter {
public:
InsertSubregRewriter(MachineInstr &MI) : CopyRewriter(MI) {
assert(MI.isInsertSubreg() && "Invalid instruction");
}
bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
unsigned &TrackReg,
unsigned &TrackSubReg) override {
if (CurrentSrcIdx == 2)
return false;
CurrentSrcIdx = 2;
const MachineOperand &MOInsertedReg = CopyLike.getOperand(2);
SrcReg = MOInsertedReg.getReg();
SrcSubReg = MOInsertedReg.getSubReg();
const MachineOperand &MODef = CopyLike.getOperand(0);
TrackReg = MODef.getReg();
if (MODef.getSubReg())
return false;
TrackSubReg = (unsigned)CopyLike.getOperand(3).getImm();
return true;
}
bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
if (CurrentSrcIdx != 2)
return false;
MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
MO.setReg(NewReg);
MO.setSubReg(NewSubReg);
return true;
}
};
class ExtractSubregRewriter : public CopyRewriter {
const TargetInstrInfo &TII;
public:
ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII)
: CopyRewriter(MI), TII(TII) {
assert(MI.isExtractSubreg() && "Invalid instruction");
}
bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
unsigned &TrackReg,
unsigned &TrackSubReg) override {
if (CurrentSrcIdx == 1)
return false;
CurrentSrcIdx = 1;
const MachineOperand &MOExtractedReg = CopyLike.getOperand(1);
SrcReg = MOExtractedReg.getReg();
if (MOExtractedReg.getSubReg())
return false;
SrcSubReg = CopyLike.getOperand(2).getImm();
const MachineOperand &MODef = CopyLike.getOperand(0);
TrackReg = MODef.getReg();
TrackSubReg = MODef.getSubReg();
return true;
}
bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
if (CurrentSrcIdx != 1)
return false;
CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
if (!NewSubReg) {
CurrentSrcIdx = -1;
CopyLike.RemoveOperand(2);
CopyLike.setDesc(TII.get(TargetOpcode::COPY));
return true;
}
CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);
return true;
}
};
class RegSequenceRewriter : public CopyRewriter {
public:
RegSequenceRewriter(MachineInstr &MI) : CopyRewriter(MI) {
assert(MI.isRegSequence() && "Invalid instruction");
}
bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
unsigned &TrackReg,
unsigned &TrackSubReg) override {
if (CurrentSrcIdx == 0) {
CurrentSrcIdx = 1;
} else {
CurrentSrcIdx += 2;
if (CurrentSrcIdx >= CopyLike.getNumOperands())
return false;
}
const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
SrcReg = MOInsertedReg.getReg();
if ((SrcSubReg = MOInsertedReg.getSubReg()))
return false;
TrackSubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
const MachineOperand &MODef = CopyLike.getOperand(0);
TrackReg = MODef.getReg();
return MODef.getSubReg() == 0;
}
bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
if ((CurrentSrcIdx & 1) != 1 || CurrentSrcIdx > CopyLike.getNumOperands())
return false;
MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
MO.setReg(NewReg);
MO.setSubReg(NewSubReg);
return true;
}
};
}
static CopyRewriter *getCopyRewriter(MachineInstr &MI,
const TargetInstrInfo &TII) {
switch (MI.getOpcode()) {
default:
return nullptr;
case TargetOpcode::COPY:
return new CopyRewriter(MI);
case TargetOpcode::INSERT_SUBREG:
return new InsertSubregRewriter(MI);
case TargetOpcode::EXTRACT_SUBREG:
return new ExtractSubregRewriter(MI, TII);
case TargetOpcode::REG_SEQUENCE:
return new RegSequenceRewriter(MI);
}
llvm_unreachable(nullptr);
}
bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr *MI) {
assert(MI && isCoalescableCopy(*MI) && "Invalid argument");
assert(MI->getDesc().getNumDefs() == 1 &&
"Coalescer can understand multiple defs?!");
const MachineOperand &MODef = MI->getOperand(0);
if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
return false;
bool Changed = false;
std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII));
if (!CpyRewriter)
return false;
unsigned SrcReg, SrcSubReg, TrackReg, TrackSubReg;
while (CpyRewriter->getNextRewritableSource(SrcReg, SrcSubReg, TrackReg,
TrackSubReg)) {
unsigned NewSrc = TrackReg;
unsigned NewSubReg = TrackSubReg;
if (!findNextSource(NewSrc, NewSubReg) || SrcReg == NewSrc)
continue;
if (CpyRewriter->RewriteCurrentSource(NewSrc, NewSubReg)) {
MRI->clearKillFlags(NewSrc);
Changed = true;
}
}
NumRewrittenCopies += Changed == true;
return Changed;
}
bool PeepholeOptimizer::optimizeUncoalescableCopy(
MachineInstr *MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
assert(MI && isUncoalescableCopy(*MI) && "Invalid argument");
SmallVector<
std::pair<TargetInstrInfo::RegSubRegPair, TargetInstrInfo::RegSubRegPair>,
4> RewritePairs;
for (const MachineOperand &MODef : MI->defs()) {
if (MODef.isDead())
continue;
if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
return false;
TargetInstrInfo::RegSubRegPair Def(MODef.getReg(), MODef.getSubReg());
TargetInstrInfo::RegSubRegPair Src = Def;
if (!findNextSource(Src.Reg, Src.SubReg))
return false;
RewritePairs.push_back(std::make_pair(Def, Src));
}
for (const auto &PairDefSrc : RewritePairs) {
const auto &Def = PairDefSrc.first;
const auto &Src = PairDefSrc.second;
assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) &&
"We do not rewrite physical registers");
const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
unsigned NewVR = MRI->createVirtualRegister(DefRC);
MachineInstr *NewCopy = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
TII->get(TargetOpcode::COPY),
NewVR).addReg(Src.Reg, 0, Src.SubReg);
NewCopy->getOperand(0).setSubReg(Def.SubReg);
if (Def.SubReg)
NewCopy->getOperand(0).setIsUndef();
LocalMIs.insert(NewCopy);
MRI->replaceRegWith(Def.Reg, NewVR);
MRI->clearKillFlags(NewVR);
MRI->clearKillFlags(Src.Reg);
}
MI->eraseFromParent();
++NumUncoalescableCopies;
return true;
}
bool PeepholeOptimizer::isLoadFoldable(
MachineInstr *MI,
SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) {
if (!MI->canFoldAsLoad() || !MI->mayLoad())
return false;
const MCInstrDesc &MCID = MI->getDesc();
if (MCID.getNumDefs() != 1)
return false;
unsigned Reg = MI->getOperand(0).getReg();
if (!MI->getOperand(0).getSubReg() &&
TargetRegisterInfo::isVirtualRegister(Reg) &&
MRI->hasOneNonDBGUse(Reg)) {
FoldAsLoadDefCandidates.insert(Reg);
return true;
}
return false;
}
bool PeepholeOptimizer::isMoveImmediate(MachineInstr *MI,
SmallSet<unsigned, 4> &ImmDefRegs,
DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
const MCInstrDesc &MCID = MI->getDesc();
if (!MI->isMoveImmediate())
return false;
if (MCID.getNumDefs() != 1)
return false;
unsigned Reg = MI->getOperand(0).getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
ImmDefMIs.insert(std::make_pair(Reg, MI));
ImmDefRegs.insert(Reg);
return true;
}
return false;
}
bool PeepholeOptimizer::foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
SmallSet<unsigned, 4> &ImmDefRegs,
DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || MO.isDef())
continue;
unsigned Reg = MO.getReg();
if (!TargetRegisterInfo::isVirtualRegister(Reg))
continue;
if (ImmDefRegs.count(Reg) == 0)
continue;
DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
assert(II != ImmDefMIs.end());
if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
++NumImmFold;
return true;
}
}
return false;
}
bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (skipOptnoneFunction(*MF.getFunction()))
return false;
DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
if (DisablePeephole)
return false;
TII = MF.getSubtarget().getInstrInfo();
TRI = MF.getSubtarget().getRegisterInfo();
MRI = &MF.getRegInfo();
DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : nullptr;
bool Changed = false;
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
MachineBasicBlock *MBB = &*I;
bool SeenMoveImm = false;
SmallPtrSet<MachineInstr*, 16> LocalMIs;
SmallSet<unsigned, 4> ImmDefRegs;
DenseMap<unsigned, MachineInstr*> ImmDefMIs;
SmallSet<unsigned, 16> FoldAsLoadDefCandidates;
for (MachineBasicBlock::iterator
MII = I->begin(), MIE = I->end(); MII != MIE; ) {
MachineInstr *MI = &*MII;
++MII;
LocalMIs.insert(MI);
if (MI->isDebugValue())
continue;
if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() ||
MI->isKill() || MI->isInlineAsm() ||
MI->hasUnmodeledSideEffects()) {
FoldAsLoadDefCandidates.clear();
continue;
}
if (MI->mayStore() || MI->isCall())
FoldAsLoadDefCandidates.clear();
if ((isUncoalescableCopy(*MI) &&
optimizeUncoalescableCopy(MI, LocalMIs)) ||
(MI->isCompare() && optimizeCmpInstr(MI, MBB)) ||
(MI->isSelect() && optimizeSelect(MI, LocalMIs))) {
LocalMIs.erase(MI);
Changed = true;
continue;
}
if (MI->isConditionalBranch() && optimizeCondBranch(MI)) {
Changed = true;
continue;
}
if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(MI)) {
Changed = true;
continue;
}
if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
SeenMoveImm = true;
} else {
Changed |= optimizeExtInstr(MI, MBB, LocalMIs);
MII = MI;
++MII;
if (SeenMoveImm)
Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
}
if (!isLoadFoldable(MI, FoldAsLoadDefCandidates) &&
!FoldAsLoadDefCandidates.empty()) {
const MCInstrDesc &MIDesc = MI->getDesc();
for (unsigned i = MIDesc.getNumDefs(); i != MIDesc.getNumOperands();
++i) {
const MachineOperand &MOp = MI->getOperand(i);
if (!MOp.isReg())
continue;
unsigned FoldAsLoadDefReg = MOp.getReg();
if (FoldAsLoadDefCandidates.count(FoldAsLoadDefReg)) {
unsigned FoldedReg = FoldAsLoadDefReg;
MachineInstr *DefMI = nullptr;
MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI,
FoldAsLoadDefReg,
DefMI);
if (FoldMI) {
DEBUG(dbgs() << "Replacing: " << *MI);
DEBUG(dbgs() << " With: " << *FoldMI);
LocalMIs.erase(MI);
LocalMIs.erase(DefMI);
LocalMIs.insert(FoldMI);
MI->eraseFromParent();
DefMI->eraseFromParent();
MRI->markUsesInDebugValueAsUndef(FoldedReg);
FoldAsLoadDefCandidates.erase(FoldedReg);
++NumLoadFold;
Changed = true;
break;
}
}
}
}
}
}
return Changed;
}
bool ValueTracker::getNextSourceFromCopy(unsigned &SrcReg,
unsigned &SrcSubReg) {
assert(Def->isCopy() && "Invalid definition");
assert(Def->getNumOperands() == 2 && "Invalid number of operands");
if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
return false;
const MachineOperand &Src = Def->getOperand(1);
SrcReg = Src.getReg();
SrcSubReg = Src.getSubReg();
return true;
}
bool ValueTracker::getNextSourceFromBitcast(unsigned &SrcReg,
unsigned &SrcSubReg) {
assert(Def->isBitcast() && "Invalid definition");
if (Def->hasUnmodeledSideEffects())
return false;
if (Def->getDesc().getNumDefs() != 1)
return false;
if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
return false;
unsigned SrcIdx = Def->getNumOperands();
for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
++OpIdx) {
const MachineOperand &MO = Def->getOperand(OpIdx);
if (!MO.isReg() || !MO.getReg())
continue;
assert(!MO.isDef() && "We should have skipped all the definitions by now");
if (SrcIdx != EndOpIdx)
return false;
SrcIdx = OpIdx;
}
const MachineOperand &Src = Def->getOperand(SrcIdx);
SrcReg = Src.getReg();
SrcSubReg = Src.getSubReg();
return true;
}
bool ValueTracker::getNextSourceFromRegSequence(unsigned &SrcReg,
unsigned &SrcSubReg) {
assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
"Invalid definition");
if (Def->getOperand(DefIdx).getSubReg())
return false;
if (!TII)
return false;
SmallVector<TargetInstrInfo::RegSubRegPairAndIdx, 8> RegSeqInputRegs;
if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
return false;
for (auto &RegSeqInput : RegSeqInputRegs) {
if (RegSeqInput.SubIdx == DefSubReg) {
if (RegSeqInput.SubReg)
return false;
SrcReg = RegSeqInput.Reg;
SrcSubReg = RegSeqInput.SubReg;
return true;
}
}
return false;
}
bool ValueTracker::getNextSourceFromInsertSubreg(unsigned &SrcReg,
unsigned &SrcSubReg) {
assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
"Invalid definition");
if (Def->getOperand(DefIdx).getSubReg())
return false;
if (!TII)
return false;
TargetInstrInfo::RegSubRegPair BaseReg;
TargetInstrInfo::RegSubRegPairAndIdx InsertedReg;
if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
return false;
if (InsertedReg.SubIdx == DefSubReg) {
SrcReg = InsertedReg.Reg;
SrcSubReg = InsertedReg.SubReg;
return true;
}
const MachineOperand &MODef = Def->getOperand(DefIdx);
if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
BaseReg.SubReg)
return false;
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
if (!TRI ||
(TRI->getSubRegIndexLaneMask(DefSubReg) &
TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) != 0)
return false;
SrcReg = BaseReg.Reg;
SrcSubReg = DefSubReg;
return true;
}
bool ValueTracker::getNextSourceFromExtractSubreg(unsigned &SrcReg,
unsigned &SrcSubReg) {
assert((Def->isExtractSubreg() ||
Def->isExtractSubregLike()) && "Invalid definition");
if (DefSubReg)
return false;
if (!TII)
return false;
TargetInstrInfo::RegSubRegPairAndIdx ExtractSubregInputReg;
if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
return false;
if (ExtractSubregInputReg.SubReg)
return false;
SrcReg = ExtractSubregInputReg.Reg;
SrcSubReg = ExtractSubregInputReg.SubIdx;
return true;
}
bool ValueTracker::getNextSourceFromSubregToReg(unsigned &SrcReg,
unsigned &SrcSubReg) {
assert(Def->isSubregToReg() && "Invalid definition");
if (DefSubReg != Def->getOperand(3).getImm())
return false;
if (Def->getOperand(2).getSubReg())
return false;
SrcReg = Def->getOperand(2).getReg();
SrcSubReg = Def->getOperand(3).getImm();
return true;
}
bool ValueTracker::getNextSourceImpl(unsigned &SrcReg, unsigned &SrcSubReg) {
assert(Def && "This method needs a valid definition");
assert(
(DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic()) &&
Def->getOperand(DefIdx).isDef() && "Invalid DefIdx");
if (Def->isCopy())
return getNextSourceFromCopy(SrcReg, SrcSubReg);
if (Def->isBitcast())
return getNextSourceFromBitcast(SrcReg, SrcSubReg);
if (!UseAdvancedTracking)
return false;
if (Def->isRegSequence() || Def->isRegSequenceLike())
return getNextSourceFromRegSequence(SrcReg, SrcSubReg);
if (Def->isInsertSubreg() || Def->isInsertSubregLike())
return getNextSourceFromInsertSubreg(SrcReg, SrcSubReg);
if (Def->isExtractSubreg() || Def->isExtractSubregLike())
return getNextSourceFromExtractSubreg(SrcReg, SrcSubReg);
if (Def->isSubregToReg())
return getNextSourceFromSubregToReg(SrcReg, SrcSubReg);
return false;
}
const MachineInstr *ValueTracker::getNextSource(unsigned &SrcReg,
unsigned &SrcSubReg) {
if (!Def)
return nullptr;
const MachineInstr *PrevDef = nullptr;
if (getNextSourceImpl(SrcReg, SrcSubReg)) {
Reg = SrcReg;
PrevDef = Def;
if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
Def = MRI.getVRegDef(Reg);
DefIdx = MRI.def_begin(Reg).getOperandNo();
DefSubReg = SrcSubReg;
return PrevDef;
}
}
Def = nullptr;
return PrevDef;
}