CodeGenRegisters.h [plain text]
#ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
#define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SparseBitVector.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/SetTheory.h"
#include <cstdlib>
#include <list>
#include <map>
#include <set>
#include <string>
#include <vector>
#include <deque>
namespace llvm {
class CodeGenRegBank;
struct MaskRolPair {
unsigned Mask;
uint8_t RotateLeft;
bool operator==(const MaskRolPair Other) {
return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
}
bool operator!=(const MaskRolPair Other) {
return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
}
};
class CodeGenSubRegIndex {
Record *const TheDef;
std::string Name;
std::string Namespace;
public:
uint16_t Size;
uint16_t Offset;
const unsigned EnumValue;
mutable unsigned LaneMask;
mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform;
bool AllSuperRegsCovered;
CodeGenSubRegIndex(Record *R, unsigned Enum);
CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
const std::string &getName() const { return Name; }
const std::string &getNamespace() const { return Namespace; }
std::string getQualifiedName() const;
typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *,
deref<llvm::less>> CompMap;
CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
CompMap::const_iterator I = Composed.find(Idx);
return I == Composed.end() ? nullptr : I->second;
}
CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
CodeGenSubRegIndex *B) {
assert(A && B);
std::pair<CompMap::iterator, bool> Ins =
Composed.insert(std::make_pair(A, B));
if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
(B->Offset == (uint16_t)-1)) {
B->Offset = Offset + A->Offset;
B->Size = A->Size;
}
return (Ins.second || Ins.first->second == B) ? nullptr
: Ins.first->second;
}
void updateComponents(CodeGenRegBank&);
const CompMap &getComposites() const { return Composed; }
unsigned computeLaneMask() const;
private:
CompMap Composed;
};
inline bool operator<(const CodeGenSubRegIndex &A,
const CodeGenSubRegIndex &B) {
return A.EnumValue < B.EnumValue;
}
struct CodeGenRegister {
Record *TheDef;
unsigned EnumValue;
unsigned CostPerUse;
bool CoveredBySubRegs;
typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<llvm::less>>
SubRegMap;
CodeGenRegister(Record *R, unsigned Enum);
const std::string &getName() const;
void buildObjectGraph(CodeGenRegBank&);
const SubRegMap &computeSubRegs(CodeGenRegBank&);
void computeSecondarySubRegs(CodeGenRegBank&);
void computeSuperRegs(CodeGenRegBank&);
const SubRegMap &getSubRegs() const {
assert(SubRegsComplete && "Must precompute sub-registers");
return SubRegs;
}
void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
CodeGenRegBank&) const;
CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
return SubReg2Idx.lookup(Reg);
}
typedef std::vector<const CodeGenRegister*> SuperRegList;
const SuperRegList &getSuperRegs() const {
assert(SubRegsComplete && "Must precompute sub-registers");
return SuperRegs;
}
ArrayRef<CodeGenRegister*> getExplicitAliases() const {
return ExplicitAliases;
}
unsigned getTopoSig() const {
assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
return TopoSig;
}
typedef SparseBitVector<> RegUnitList;
typedef SmallVector<unsigned, 16> RegUnitLaneMaskList;
RegUnitList NativeRegUnits;
const RegUnitList &getRegUnits() const { return RegUnits; }
ArrayRef<unsigned> getRegUnitLaneMasks() const {
return makeArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count());
}
RegUnitList getNativeRegUnits() const {
return NativeRegUnits;
}
void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) {
RegUnitLaneMasks = LaneMasks;
}
bool inheritRegUnits(CodeGenRegBank &RegBank);
void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); }
unsigned getWeight(const CodeGenRegBank &RegBank) const;
typedef std::vector<const CodeGenRegister*> Vec;
private:
bool SubRegsComplete;
bool SuperRegsComplete;
unsigned TopoSig;
SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
SmallVector<CodeGenRegister*, 8> ExplicitAliases;
SuperRegList LeadingSuperRegs;
SubRegMap SubRegs;
SuperRegList SuperRegs;
DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
RegUnitList RegUnits;
RegUnitLaneMaskList RegUnitLaneMasks;
};
inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) {
return A.EnumValue < B.EnumValue;
}
inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
return A.EnumValue == B.EnumValue;
}
class CodeGenRegisterClass {
CodeGenRegister::Vec Members;
std::vector<SmallVector<Record*, 16> > Orders;
BitVector SubClasses;
SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
Record *TheDef;
std::string Name;
void inheritProperties(CodeGenRegBank&);
DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
SubClassWithSubReg;
DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
SuperRegClasses;
BitVector TopoSigs;
public:
unsigned EnumValue;
std::string Namespace;
SmallVector<MVT::SimpleValueType, 4> VTs;
unsigned SpillSize;
unsigned SpillAlignment;
int CopyCost;
bool Allocatable;
std::string AltOrderSelect;
unsigned LaneMask;
Record *getDef() const { return TheDef; }
const std::string &getName() const { return Name; }
std::string getQualifiedName() const;
ArrayRef<MVT::SimpleValueType> getValueTypes() const {return VTs;}
unsigned getNumValueTypes() const { return VTs.size(); }
MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const {
if (VTNum < VTs.size())
return VTs[VTNum];
llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
}
bool contains(const CodeGenRegister*) const;
bool hasSubClass(const CodeGenRegisterClass *RC) const {
return SubClasses.test(RC->EnumValue);
}
CodeGenRegisterClass *
getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
return SubClassWithSubReg.lookup(SubIdx);
}
void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
CodeGenRegisterClass *SubRC) {
SubClassWithSubReg[SubIdx] = SubRC;
}
void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
BitVector &Out) const;
void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
CodeGenRegisterClass *SuperRC) {
SuperRegClasses[SubIdx].insert(SuperRC);
}
const BitVector &getSubClasses() const { return SubClasses; }
ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
return SuperClasses;
}
ArrayRef<Record*> getOrder(unsigned No = 0) const {
return Orders[No];
}
unsigned getNumOrders() const { return Orders.size(); }
const CodeGenRegister::Vec &getMembers() const { return Members; }
const BitVector &getTopoSigs() const { return TopoSigs; }
void buildRegUnitSet(std::vector<unsigned> &RegUnits) const;
CodeGenRegisterClass(CodeGenRegBank&, Record *R);
struct Key {
const CodeGenRegister::Vec *Members;
unsigned SpillSize;
unsigned SpillAlignment;
Key(const CodeGenRegister::Vec *M, unsigned S = 0, unsigned A = 0)
: Members(M), SpillSize(S), SpillAlignment(A) {}
Key(const CodeGenRegisterClass &RC)
: Members(&RC.getMembers()),
SpillSize(RC.SpillSize),
SpillAlignment(RC.SpillAlignment) {}
bool operator<(const Key&) const;
};
CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
static void computeSubClasses(CodeGenRegBank&);
};
struct RegUnit {
unsigned Weight;
const CodeGenRegister *Roots[2];
unsigned RegClassUnitSetsIdx;
RegUnit() : Weight(0), RegClassUnitSetsIdx(0) {
Roots[0] = Roots[1] = nullptr;
}
ArrayRef<const CodeGenRegister*> getRoots() const {
assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]);
}
};
struct RegUnitSet {
typedef std::vector<unsigned>::const_iterator iterator;
std::string Name;
std::vector<unsigned> Units;
unsigned Weight; unsigned Order;
RegUnitSet() : Weight(0), Order(0) {}
};
typedef SmallVector<unsigned, 16> TopoSigId;
class CodeGenRegBank {
SetTheory Sets;
std::deque<CodeGenSubRegIndex> SubRegIndices;
DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
CodeGenSubRegIndex*> ConcatIdxMap;
ConcatIdxMap ConcatIdx;
std::deque<CodeGenRegister> Registers;
StringMap<CodeGenRegister*> RegistersByName;
DenseMap<Record*, CodeGenRegister*> Def2Reg;
unsigned NumNativeRegUnits;
std::map<TopoSigId, unsigned> TopoSigs;
SmallVector<RegUnit, 8> RegUnits;
std::list<CodeGenRegisterClass> RegClasses;
DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
RCKeyMap Key2RC;
std::vector<RegUnitSet> RegUnitSets;
std::vector<std::vector<unsigned> > RegClassUnitSets;
std::vector<unsigned> RegUnitSetOrder;
void addToMaps(CodeGenRegisterClass*);
CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
const CodeGenRegister::Vec *Membs,
StringRef Name);
void computeInferredRegisterClasses();
void inferCommonSubClass(CodeGenRegisterClass *RC);
void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) {
inferMatchingSuperRegClass(RC, RegClasses.begin());
}
void inferMatchingSuperRegClass(
CodeGenRegisterClass *RC,
std::list<CodeGenRegisterClass>::iterator FirstSubRegRC);
void pruneUnitSets();
void computeRegUnitWeights();
void computeRegUnitSets();
void computeComposites();
void computeSubRegLaneMasks();
void computeRegUnitLaneMasks();
public:
CodeGenRegBank(RecordKeeper&);
SetTheory &getSets() { return Sets; }
const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
return SubRegIndices;
}
CodeGenSubRegIndex *getSubRegIdx(Record*);
CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
CodeGenSubRegIndex *B);
CodeGenSubRegIndex *
getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
void
addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts,
CodeGenSubRegIndex *Idx) {
ConcatIdx.insert(std::make_pair(Parts, Idx));
}
const std::deque<CodeGenRegister> &getRegisters() { return Registers; }
const StringMap<CodeGenRegister*> &getRegistersByName() {
return RegistersByName;
}
CodeGenRegister *getReg(Record*);
unsigned getRegIndex(const CodeGenRegister *Reg) const {
return Reg->EnumValue - 1;
}
unsigned getNumTopoSigs() const {
return TopoSigs.size();
}
unsigned getTopoSig(const TopoSigId &Id) {
return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
}
unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
RegUnits.resize(RegUnits.size() + 1);
RegUnits.back().Roots[0] = R0;
RegUnits.back().Roots[1] = R1;
return RegUnits.size() - 1;
}
unsigned newRegUnit(unsigned Weight) {
RegUnits.resize(RegUnits.size() + 1);
RegUnits.back().Weight = Weight;
return RegUnits.size() - 1;
}
bool isNativeUnit(unsigned RUID) {
return RUID < NumNativeRegUnits;
}
unsigned getNumNativeRegUnits() const {
return NumNativeRegUnits;
}
RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
const std::list<CodeGenRegisterClass> &getRegClasses() const {
return RegClasses;
}
CodeGenRegisterClass *getRegClass(Record*);
const CodeGenRegisterClass* getRegClassForRegister(Record *R);
unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
unsigned Weight = 0;
for (std::vector<unsigned>::const_iterator
I = Units.begin(), E = Units.end(); I != E; ++I)
Weight += getRegUnit(*I).Weight;
return Weight;
}
unsigned getRegSetIDAt(unsigned Order) const {
return RegUnitSetOrder[Order];
}
const RegUnitSet &getRegSetAt(unsigned Order) const {
return RegUnitSets[RegUnitSetOrder[Order]];
}
void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
getRegUnit(RUID).Weight += Inc;
}
unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
const RegUnitSet &getRegPressureSet(unsigned Idx) const {
return RegUnitSets[Idx];
}
unsigned getNumRegClassPressureSetLists() const {
return RegClassUnitSets.size();
}
ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
return RegClassUnitSets[RCIdx];
}
void computeDerivedInfo();
BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
unsigned CoveringLanes;
};
}
#endif