#ifndef LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
#define LLVM_LIB_TARGET_R600_SIREGISTERINFO_H
#include "AMDGPURegisterInfo.h"
#include "AMDGPUSubtarget.h"
#include "llvm/Support/Debug.h"
namespace llvm {
struct SIRegisterInfo : public AMDGPURegisterInfo {
SIRegisterInfo();
BitVector getReservedRegs(const MachineFunction &MF) const override;
unsigned getRegPressureSetLimit(const MachineFunction &MF,
unsigned Idx) const override;
bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS) const override;
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
unsigned getHWRegIndex(unsigned Reg) const override;
const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
bool isSGPRClass(const TargetRegisterClass *RC) const {
if (!RC)
return false;
return !hasVGPRs(RC);
}
bool isSGPRClassID(unsigned RCID) const {
if (static_cast<int>(RCID) == -1)
return false;
return isSGPRClass(getRegClass(RCID));
}
bool hasVGPRs(const TargetRegisterClass *RC) const;
const TargetRegisterClass *getEquivalentVGPRClass(
const TargetRegisterClass *SRC) const;
const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
unsigned SubIdx) const;
unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
unsigned Channel) const;
bool opCanUseLiteralConstant(unsigned OpType) const;
bool opCanUseInlineConstant(unsigned OpType) const;
enum PreloadedValue {
TGID_X,
TGID_Y,
TGID_Z,
SCRATCH_WAVE_OFFSET,
SCRATCH_PTR,
INPUT_PTR,
TIDIG_X,
TIDIG_Y,
TIDIG_Z
};
unsigned getPreloadedValue(const MachineFunction &MF,
enum PreloadedValue Value) const;
unsigned getNumVGPRsAllowed(unsigned WaveCount) const;
unsigned getNumSGPRsAllowed(AMDGPUSubtarget::Generation gen,
unsigned WaveCount) const;
unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
const TargetRegisterClass *RC) const;
private:
void buildScratchLoadStore(MachineBasicBlock::iterator MI,
unsigned LoadStoreOp, unsigned Value,
unsigned ScratchRsrcReg, unsigned ScratchOffset,
int64_t Offset, RegScavenger *RS) const;
};
}
#endif