HexagonMachineScheduler.h [plain text]
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
#include "llvm/ADT/PriorityQueue.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ResourcePriorityQueue.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
using namespace llvm;
namespace llvm {
class VLIWResourceModel {
DFAPacketizer *ResourcesModel;
const TargetSchedModel *SchedModel;
std::vector<SUnit*> Packet;
unsigned TotalPackets;
public:
VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
: SchedModel(SM), TotalPackets(0) {
ResourcesModel = STI.getInstrInfo()->CreateTargetScheduleState(STI);
assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.");
Packet.resize(SchedModel->getIssueWidth());
Packet.clear();
ResourcesModel->clearResources();
}
~VLIWResourceModel() {
delete ResourcesModel;
}
void resetPacketState() {
Packet.clear();
}
void resetDFA() {
ResourcesModel->clearResources();
}
void reset() {
Packet.clear();
ResourcesModel->clearResources();
}
bool isResourceAvailable(SUnit *SU);
bool reserveResources(SUnit *SU);
unsigned getTotalPackets() const { return TotalPackets; }
};
class VLIWMachineScheduler : public ScheduleDAGMILive {
public:
VLIWMachineScheduler(MachineSchedContext *C,
std::unique_ptr<MachineSchedStrategy> S)
: ScheduleDAGMILive(C, std::move(S)) {}
void schedule() override;
void postprocessDAG();
};
class ConvergingVLIWScheduler : public MachineSchedStrategy {
struct SchedCandidate {
SUnit *SU;
RegPressureDelta RPDelta;
int SCost;
SchedCandidate(): SU(nullptr), SCost(0) {}
};
enum CandResult {
NoCand, NodeOrder, SingleExcess, SingleCritical, SingleMax, MultiPressure,
BestCost};
struct VLIWSchedBoundary {
VLIWMachineScheduler *DAG;
const TargetSchedModel *SchedModel;
ReadyQueue Available;
ReadyQueue Pending;
bool CheckPending;
ScheduleHazardRecognizer *HazardRec;
VLIWResourceModel *ResourceModel;
unsigned CurrCycle;
unsigned IssueCount;
unsigned MinReadyCycle;
unsigned MaxMinLatency;
VLIWSchedBoundary(unsigned ID, const Twine &Name):
DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P"),
CheckPending(false), HazardRec(nullptr), ResourceModel(nullptr),
CurrCycle(0), IssueCount(0),
MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
~VLIWSchedBoundary() {
delete ResourceModel;
delete HazardRec;
}
void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) {
DAG = dag;
SchedModel = smodel;
}
bool isTop() const {
return Available.getID() == ConvergingVLIWScheduler::TopQID;
}
bool checkHazard(SUnit *SU);
void releaseNode(SUnit *SU, unsigned ReadyCycle);
void bumpCycle();
void bumpNode(SUnit *SU);
void releasePending();
void removeReady(SUnit *SU);
SUnit *pickOnlyChoice();
};
VLIWMachineScheduler *DAG;
const TargetSchedModel *SchedModel;
VLIWSchedBoundary Top;
VLIWSchedBoundary Bot;
public:
enum {
TopQID = 1,
BotQID = 2,
LogMaxQID = 2
};
ConvergingVLIWScheduler()
: DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
Bot(BotQID, "BotQ") {}
void initialize(ScheduleDAGMI *dag) override;
SUnit *pickNode(bool &IsTopNode) override;
void schedNode(SUnit *SU, bool IsTopNode) override;
void releaseTopNode(SUnit *SU) override;
void releaseBottomNode(SUnit *SU) override;
unsigned ReportPackets() {
return Top.ResourceModel->getTotalPackets() +
Bot.ResourceModel->getTotalPackets();
}
protected:
SUnit *pickNodeBidrectional(bool &IsTopNode);
int SchedulingCost(ReadyQueue &Q,
SUnit *SU, SchedCandidate &Candidate,
RegPressureDelta &Delta, bool verbose);
CandResult pickNodeFromQueue(ReadyQueue &Q,
const RegPressureTracker &RPTracker,
SchedCandidate &Candidate);
#ifndef NDEBUG
void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU,
PressureChange P = PressureChange());
#endif
};
}
#endif