A15SDOptimizer.cpp [plain text]
#include "ARM.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMSubtarget.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <map>
#include <set>
using namespace llvm;
#define DEBUG_TYPE "a15-sd-optimizer"
namespace {
struct A15SDOptimizer : public MachineFunctionPass {
static char ID;
A15SDOptimizer() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &Fn) override;
const char *getPassName() const override {
return "ARM A15 S->D optimizer";
}
private:
const ARMBaseInstrInfo *TII;
const TargetRegisterInfo *TRI;
MachineRegisterInfo *MRI;
bool runOnInstruction(MachineInstr *MI);
unsigned createDupLane(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL,
unsigned Reg, unsigned Lane,
bool QPR=false);
unsigned createExtractSubreg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL,
unsigned DReg, unsigned Lane,
const TargetRegisterClass *TRC);
unsigned createVExt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL,
unsigned Ssub0, unsigned Ssub1);
unsigned createRegSequence(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL,
unsigned Reg1, unsigned Reg2);
unsigned createInsertSubreg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL, unsigned DReg, unsigned Lane,
unsigned ToInsert);
unsigned createImplicitDef(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL);
bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
bool hasPartialWrite(MachineInstr *MI);
SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
unsigned getDPRLaneFromSPR(unsigned SReg);
MachineInstr *elideCopies(MachineInstr *MI);
void elideCopiesAndPHIs(MachineInstr *MI,
SmallVectorImpl<MachineInstr*> &Outs);
unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
unsigned optimizeSDPattern(MachineInstr *MI);
unsigned getPrefSPRLane(unsigned SReg);
void eraseInstrWithNoUses(MachineInstr *MI);
std::map<MachineInstr*, unsigned> Replacements;
std::set<MachineInstr *> DeadInstr;
};
char A15SDOptimizer::ID = 0;
}
bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
const TargetRegisterClass *TRC) {
if (!MO.isReg())
return false;
unsigned Reg = MO.getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg))
return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
else
return TRC->contains(Reg);
}
unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
&ARM::DPRRegClass);
if (DReg != ARM::NoRegister) return ARM::ssub_1;
return ARM::ssub_0;
}
unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
if (!TRI->isVirtualRegister(SReg))
return getDPRLaneFromSPR(SReg);
MachineInstr *MI = MRI->getVRegDef(SReg);
if (!MI) return ARM::ssub_0;
MachineOperand *MO = MI->findRegisterDefOperand(SReg);
assert(MO->isReg() && "Non-register operand found!");
if (!MO) return ARM::ssub_0;
if (MI->isCopy() && usesRegClass(MI->getOperand(1),
&ARM::SPRRegClass)) {
SReg = MI->getOperand(1).getReg();
}
if (TargetRegisterInfo::isVirtualRegister(SReg)) {
if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
return ARM::ssub_0;
}
return getDPRLaneFromSPR(SReg);
}
void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
SmallVector<MachineInstr *, 8> Front;
DeadInstr.insert(MI);
DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
Front.push_back(MI);
while (Front.size() != 0) {
MI = Front.back();
Front.pop_back();
for (unsigned int i = 0; i < MI->getNumOperands(); ++i) {
MachineOperand &MO = MI->getOperand(i);
if ((!MO.isReg()) || (!MO.isUse()))
continue;
unsigned Reg = MO.getReg();
if (!TRI->isVirtualRegister(Reg))
continue;
MachineOperand *Op = MI->findRegisterDefOperand(Reg);
if (!Op)
continue;
MachineInstr *Def = Op->getParent();
if (DeadInstr.find(Def) != DeadInstr.end())
continue;
bool IsDead = true;
for (unsigned int j = 0; j < Def->getNumOperands(); ++j) {
MachineOperand &MODef = Def->getOperand(j);
if ((!MODef.isReg()) || (!MODef.isDef()))
continue;
unsigned DefReg = MODef.getReg();
if (!TRI->isVirtualRegister(DefReg)) {
IsDead = false;
break;
}
for (MachineRegisterInfo::use_instr_iterator
II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end();
II != EE; ++II) {
if (&*II == Def)
continue;
if (DeadInstr.find(&*II) == DeadInstr.end()) {
IsDead = false;
break;
}
}
}
if (!IsDead) continue;
DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
DeadInstr.insert(Def);
}
}
}
unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
if (MI->isCopy()) {
return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
}
if (MI->isInsertSubreg()) {
unsigned DPRReg = MI->getOperand(1).getReg();
unsigned SPRReg = MI->getOperand(2).getReg();
if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
if (DPRMI && SPRMI) {
MachineInstr *ECDef = elideCopies(DPRMI);
if (ECDef && ECDef->isImplicitDef()) {
MachineInstr *EC = elideCopies(SPRMI);
if (EC && EC->isCopy() &&
EC->getOperand(1).getSubReg() == ARM::ssub_0) {
DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
unsigned FullReg = SPRMI->getOperand(1).getReg();
const TargetRegisterClass *TRC =
MRI->getRegClass(MI->getOperand(1).getReg());
if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
DEBUG(dbgs() << "Subreg copy is compatible - returning ");
DEBUG(dbgs() << PrintReg(FullReg) << "\n");
eraseInstrWithNoUses(MI);
return FullReg;
}
}
return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
}
}
}
return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
}
if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
&ARM::SPRRegClass)) {
unsigned NumImplicit = 0, NumTotal = 0;
unsigned NonImplicitReg = ~0U;
for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
if (!MI->getOperand(I).isReg())
continue;
++NumTotal;
unsigned OpReg = MI->getOperand(I).getReg();
if (!TRI->isVirtualRegister(OpReg))
break;
MachineInstr *Def = MRI->getVRegDef(OpReg);
if (!Def)
break;
if (Def->isImplicitDef())
++NumImplicit;
else
NonImplicitReg = MI->getOperand(I).getReg();
}
if (NumImplicit == NumTotal - 1)
return optimizeAllLanesPattern(MI, NonImplicitReg);
else
return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
}
llvm_unreachable("Unhandled update pattern!");
}
bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
return true;
if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
&ARM::SPRRegClass))
return true;
if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
return true;
return false;
}
MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
if (!MI->isFullCopy())
return MI;
if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
return nullptr;
MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
if (!Def)
return nullptr;
return elideCopies(Def);
}
void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
SmallVectorImpl<MachineInstr*> &Outs) {
std::set<MachineInstr *> Reached;
SmallVector<MachineInstr *, 8> Front;
Front.push_back(MI);
while (Front.size() != 0) {
MI = Front.back();
Front.pop_back();
if (Reached.find(MI) != Reached.end())
continue;
Reached.insert(MI);
if (MI->isPHI()) {
for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
unsigned Reg = MI->getOperand(I).getReg();
if (!TRI->isVirtualRegister(Reg)) {
continue;
}
MachineInstr *NewMI = MRI->getVRegDef(Reg);
if (!NewMI)
continue;
Front.push_back(NewMI);
}
} else if (MI->isFullCopy()) {
if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
continue;
MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
if (!NewMI)
continue;
Front.push_back(NewMI);
} else {
DEBUG(dbgs() << "Found partial copy" << *MI <<"\n");
Outs.push_back(MI);
}
}
}
SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
MI->isKill())
return SmallVector<unsigned, 8>();
SmallVector<unsigned, 8> Defs;
for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
if (!usesRegClass(MO, &ARM::DPRRegClass) &&
!usesRegClass(MO, &ARM::QPRRegClass) &&
!usesRegClass(MO, &ARM::DPairRegClass)) continue;
Defs.push_back(MO.getReg());
}
return Defs;
}
unsigned
A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL,
unsigned Reg, unsigned Lane, bool QPR) {
unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
&ARM::DPRRegClass);
AddDefaultPred(BuildMI(MBB,
InsertBefore,
DL,
TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
Out)
.addReg(Reg)
.addImm(Lane));
return Out;
}
unsigned
A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL,
unsigned DReg, unsigned Lane,
const TargetRegisterClass *TRC) {
unsigned Out = MRI->createVirtualRegister(TRC);
BuildMI(MBB,
InsertBefore,
DL,
TII->get(TargetOpcode::COPY), Out)
.addReg(DReg, 0, Lane);
return Out;
}
unsigned
A15SDOptimizer::createRegSequence(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL,
unsigned Reg1, unsigned Reg2) {
unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
BuildMI(MBB,
InsertBefore,
DL,
TII->get(TargetOpcode::REG_SEQUENCE), Out)
.addReg(Reg1)
.addImm(ARM::dsub_0)
.addReg(Reg2)
.addImm(ARM::dsub_1);
return Out;
}
unsigned
A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL,
unsigned Ssub0, unsigned Ssub1) {
unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
AddDefaultPred(BuildMI(MBB,
InsertBefore,
DL,
TII->get(ARM::VEXTd32), Out)
.addReg(Ssub0)
.addReg(Ssub1)
.addImm(1));
return Out;
}
unsigned
A15SDOptimizer::createInsertSubreg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL, unsigned DReg, unsigned Lane,
unsigned ToInsert) {
unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
BuildMI(MBB,
InsertBefore,
DL,
TII->get(TargetOpcode::INSERT_SUBREG), Out)
.addReg(DReg)
.addReg(ToInsert)
.addImm(Lane);
return Out;
}
unsigned
A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
MachineBasicBlock::iterator InsertBefore,
DebugLoc DL) {
unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
BuildMI(MBB,
InsertBefore,
DL,
TII->get(TargetOpcode::IMPLICIT_DEF), Out);
return Out;
}
unsigned
A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
MachineBasicBlock::iterator InsertPt(MI);
DebugLoc DL = MI->getDebugLoc();
MachineBasicBlock &MBB = *MI->getParent();
InsertPt++;
unsigned Out;
if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
ARM::dsub_0, &ARM::DPRRegClass);
unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
ARM::dsub_1, &ARM::DPRRegClass);
unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
} else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
} else {
assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
"Found unexpected regclass!");
unsigned PrefLane = getPrefSPRLane(Reg);
unsigned Lane;
switch (PrefLane) {
case ARM::ssub_0: Lane = 0; break;
case ARM::ssub_1: Lane = 1; break;
default: llvm_unreachable("Unknown preferred lane!");
}
bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
Out = createImplicitDef(MBB, InsertPt, DL);
Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
eraseInstrWithNoUses(MI);
}
return Out;
}
bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
bool Modified = false;
for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
I != E; ++I) {
SmallVector<MachineInstr *, 8> DefSrcs;
if (!TRI->isVirtualRegister(*I))
continue;
MachineInstr *Def = MRI->getVRegDef(*I);
if (!Def)
continue;
elideCopiesAndPHIs(Def, DefSrcs);
for (SmallVectorImpl<MachineInstr *>::iterator II = DefSrcs.begin(),
EE = DefSrcs.end(); II != EE; ++II) {
MachineInstr *MI = *II;
if (Replacements.find(MI) != Replacements.end())
continue;
if (!hasPartialWrite(MI))
continue;
SmallVector<MachineOperand*, 8> Uses;
unsigned DPRDefReg = MI->getOperand(0).getReg();
for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
E = MRI->use_end(); I != E; ++I)
Uses.push_back(&*I);
unsigned NewReg = optimizeSDPattern(MI);
if (NewReg != 0) {
Modified = true;
for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
E = Uses.end(); I != E; ++I) {
MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
DEBUG(dbgs() << "Replacing operand "
<< **I << " with "
<< PrintReg(NewReg) << "\n");
(*I)->substVirtReg(NewReg, 0, *TRI);
}
}
Replacements[MI] = NewReg;
}
}
return Modified;
}
bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
if (!(STI.isCortexA15() && STI.hasNEON()))
return false;
TII = STI.getInstrInfo();
TRI = STI.getRegisterInfo();
MRI = &Fn.getRegInfo();
bool Modified = false;
DEBUG(dbgs() << "Running on function " << Fn.getName()<< "\n");
DeadInstr.clear();
Replacements.clear();
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
++MFI) {
for (MachineBasicBlock::iterator MI = MFI->begin(), ME = MFI->end();
MI != ME;) {
Modified |= runOnInstruction(MI++);
}
}
for (std::set<MachineInstr *>::iterator I = DeadInstr.begin(),
E = DeadInstr.end();
I != E; ++I) {
(*I)->eraseFromParent();
}
return Modified;
}
FunctionPass *llvm::createA15SDOptimizerPass() {
return new A15SDOptimizer();
}