X86FloatingPoint.cpp [plain text]
#include "X86.h"
#include "X86InstrInfo.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DepthFirstIterator.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/EdgeBundles.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
using namespace llvm;
#define DEBUG_TYPE "x86-codegen"
STATISTIC(NumFXCH, "Number of fxch instructions inserted");
STATISTIC(NumFP , "Number of floating point instructions");
namespace {
const unsigned ScratchFPReg = 7;
struct FPS : public MachineFunctionPass {
static char ID;
FPS() : MachineFunctionPass(ID) {
initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
memset(Stack, 0, sizeof(Stack));
memset(RegMap, 0, sizeof(RegMap));
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
AU.addRequired<EdgeBundles>();
AU.addPreservedID(MachineLoopInfoID);
AU.addPreservedID(MachineDominatorsID);
MachineFunctionPass::getAnalysisUsage(AU);
}
bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const override { return "X86 FP Stackifier"; }
private:
const TargetInstrInfo *TII;
struct LiveBundle {
unsigned Mask;
unsigned FixCount;
unsigned char FixStack[8];
LiveBundle() : Mask(0), FixCount(0) {}
bool isFixed() const { return !Mask || FixCount; }
};
SmallVector<LiveBundle, 8> LiveBundles;
EdgeBundles *Bundles;
static unsigned calcLiveInMask(MachineBasicBlock *MBB) {
unsigned Mask = 0;
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
E = MBB->livein_end(); I != E; ++I) {
unsigned Reg = *I;
if (Reg < X86::FP0 || Reg > X86::FP6)
continue;
Mask |= 1 << (Reg - X86::FP0);
}
return Mask;
}
void bundleCFG(MachineFunction &MF);
MachineBasicBlock *MBB;
unsigned Stack[8]; unsigned StackTop;
enum {
NumFPRegs = 8 };
unsigned RegMap[NumFPRegs];
void setupBlockStack();
void finishBlockStack();
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
void dumpStack() const {
dbgs() << "Stack contents:";
for (unsigned i = 0; i != StackTop; ++i) {
dbgs() << " FP" << Stack[i];
assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
}
}
#endif
unsigned getSlot(unsigned RegNo) const {
assert(RegNo < NumFPRegs && "Regno out of range!");
return RegMap[RegNo];
}
bool isLive(unsigned RegNo) const {
unsigned Slot = getSlot(RegNo);
return Slot < StackTop && Stack[Slot] == RegNo;
}
unsigned getStackEntry(unsigned STi) const {
if (STi >= StackTop)
report_fatal_error("Access past stack top!");
return Stack[StackTop-1-STi];
}
unsigned getSTReg(unsigned RegNo) const {
return StackTop - 1 - getSlot(RegNo) + X86::ST0;
}
void pushReg(unsigned Reg) {
assert(Reg < NumFPRegs && "Register number out of range!");
if (StackTop >= 8)
report_fatal_error("Stack overflow!");
Stack[StackTop] = Reg;
RegMap[Reg] = StackTop++;
}
bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
if (isAtTop(RegNo)) return;
unsigned STReg = getSTReg(RegNo);
unsigned RegOnTop = getStackEntry(0);
std::swap(RegMap[RegNo], RegMap[RegOnTop]);
if (RegMap[RegOnTop] >= StackTop)
report_fatal_error("Access past stack top!");
std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
++NumFXCH;
}
void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
unsigned STReg = getSTReg(RegNo);
pushReg(AsReg);
BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
}
void popStackAfter(MachineBasicBlock::iterator &I);
void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
MachineBasicBlock::iterator
freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
MachineBasicBlock::iterator I);
bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
void handleCall(MachineBasicBlock::iterator &I);
void handleZeroArgFP(MachineBasicBlock::iterator &I);
void handleOneArgFP(MachineBasicBlock::iterator &I);
void handleOneArgFPRW(MachineBasicBlock::iterator &I);
void handleTwoArgFP(MachineBasicBlock::iterator &I);
void handleCompareFP(MachineBasicBlock::iterator &I);
void handleCondMovFP(MachineBasicBlock::iterator &I);
void handleSpecialFP(MachineBasicBlock::iterator &I);
static bool isFPCopy(MachineInstr *MI) {
unsigned DstReg = MI->getOperand(0).getReg();
unsigned SrcReg = MI->getOperand(1).getReg();
return X86::RFP80RegClass.contains(DstReg) ||
X86::RFP80RegClass.contains(SrcReg);
}
void setKillFlags(MachineBasicBlock &MBB) const;
};
char FPS::ID = 0;
}
FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
static unsigned getFPReg(const MachineOperand &MO) {
assert(MO.isReg() && "Expected an FP register!");
unsigned Reg = MO.getReg();
assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
return Reg - X86::FP0;
}
bool FPS::runOnMachineFunction(MachineFunction &MF) {
bool FPIsUsed = false;
assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
for (unsigned i = 0; i <= 6; ++i)
if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
FPIsUsed = true;
break;
}
if (!FPIsUsed) return false;
Bundles = &getAnalysis<EdgeBundles>();
TII = MF.getSubtarget().getInstrInfo();
bundleCFG(MF);
StackTop = 0;
SmallPtrSet<MachineBasicBlock*, 8> Processed;
MachineBasicBlock *Entry = MF.begin();
bool Changed = false;
for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> >
I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
I != E; ++I)
Changed |= processBasicBlock(MF, **I);
if (MF.size() != Processed.size())
for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
if (Processed.insert(BB))
Changed |= processBasicBlock(MF, *BB);
LiveBundles.clear();
return Changed;
}
void FPS::bundleCFG(MachineFunction &MF) {
assert(LiveBundles.empty() && "Stale data in LiveBundles");
LiveBundles.resize(Bundles->getNumBundles());
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
MachineBasicBlock *MBB = I;
const unsigned Mask = calcLiveInMask(MBB);
if (!Mask)
continue;
LiveBundles[Bundles->getBundle(MBB->getNumber(), false)].Mask |= Mask;
}
}
bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
bool Changed = false;
MBB = &BB;
setKillFlags(BB);
setupBlockStack();
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
MachineInstr *MI = I;
uint64_t Flags = MI->getDesc().TSFlags;
unsigned FPInstClass = Flags & X86II::FPTypeMask;
if (MI->isInlineAsm())
FPInstClass = X86II::SpecialFP;
if (MI->isCopy() && isFPCopy(MI))
FPInstClass = X86II::SpecialFP;
if (MI->isImplicitDef() &&
X86::RFP80RegClass.contains(MI->getOperand(0).getReg()))
FPInstClass = X86II::SpecialFP;
if (MI->isCall())
FPInstClass = X86II::SpecialFP;
if (FPInstClass == X86II::NotFP)
continue;
MachineInstr *PrevMI = nullptr;
if (I != BB.begin())
PrevMI = std::prev(I);
++NumFP; DEBUG(dbgs() << "\nFPInst:\t" << *MI);
SmallVector<unsigned, 8> DeadRegs;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isDead())
DeadRegs.push_back(MO.getReg());
}
switch (FPInstClass) {
case X86II::ZeroArgFP: handleZeroArgFP(I); break;
case X86II::OneArgFP: handleOneArgFP(I); break; case X86II::OneArgFPRW: handleOneArgFPRW(I); break; case X86II::TwoArgFP: handleTwoArgFP(I); break;
case X86II::CompareFP: handleCompareFP(I); break;
case X86II::CondMovFP: handleCondMovFP(I); break;
case X86II::SpecialFP: handleSpecialFP(I); break;
default: llvm_unreachable("Unknown FP Type!");
}
for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
unsigned Reg = DeadRegs[i];
if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
freeStackSlotAfter(I, Reg-X86::FP0);
}
}
DEBUG(
MachineBasicBlock::iterator PrevI(PrevMI);
if (I == PrevI) {
dbgs() << "Just deleted pseudo instruction\n";
} else {
MachineBasicBlock::iterator Start = I;
while (Start != BB.begin() && std::prev(Start) != PrevI) --Start;
dbgs() << "Inserted instructions:\n\t";
Start->print(dbgs(), &MF.getTarget());
while (++Start != std::next(I)) {}
}
dumpStack();
);
(void)PrevMI;
Changed = true;
}
finishBlockStack();
return Changed;
}
void FPS::setupBlockStack() {
DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber()
<< " derived from " << MBB->getName() << ".\n");
StackTop = 0;
const LiveBundle &Bundle =
LiveBundles[Bundles->getBundle(MBB->getNumber(), false)];
if (!Bundle.Mask) {
DEBUG(dbgs() << "Block has no FP live-ins.\n");
return;
}
assert(Bundle.isFixed() && "Reached block before any predecessors");
for (unsigned i = Bundle.FixCount; i > 0; --i) {
MBB->addLiveIn(X86::ST0+i-1);
DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP"
<< unsigned(Bundle.FixStack[i-1]) << '\n');
pushReg(Bundle.FixStack[i-1]);
}
adjustLiveRegs(calcLiveInMask(MBB), MBB->begin());
DEBUG(MBB->dump());
}
void FPS::finishBlockStack() {
if (MBB->succ_empty())
return;
DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber()
<< " derived from " << MBB->getName() << ".\n");
unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true);
LiveBundle &Bundle = LiveBundles[BundleIdx];
MachineBasicBlock::iterator Term = MBB->getFirstTerminator();
adjustLiveRegs(Bundle.Mask, Term);
if (!Bundle.Mask) {
DEBUG(dbgs() << "No live-outs.\n");
return;
}
DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
if (Bundle.isFixed()) {
DEBUG(dbgs() << "Shuffling stack to match.\n");
shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
} else {
DEBUG(dbgs() << "Fixing stack order now.\n");
Bundle.FixCount = StackTop;
for (unsigned i = 0; i < StackTop; ++i)
Bundle.FixStack[i] = getStackEntry(i);
}
}
namespace {
struct TableEntry {
uint16_t from;
uint16_t to;
bool operator<(const TableEntry &TE) const { return from < TE.from; }
friend bool operator<(const TableEntry &TE, unsigned V) {
return TE.from < V;
}
friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V,
const TableEntry &TE) {
return V < TE.from;
}
};
}
#ifndef NDEBUG
static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
for (unsigned i = 0; i != NumEntries-1; ++i)
if (!(Table[i] < Table[i+1])) return false;
return true;
}
#endif
static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
if (I != Table+N && I->from == Opcode)
return I->to;
return -1;
}
#ifdef NDEBUG
#define ASSERT_SORTED(TABLE)
#else
#define ASSERT_SORTED(TABLE) \
{ static bool TABLE##Checked = false; \
if (!TABLE##Checked) { \
assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
"All lookup tables must be sorted for efficient access!"); \
TABLE##Checked = true; \
} \
}
#endif
static const TableEntry OpcodeTable[] = {
{ X86::ABS_Fp32 , X86::ABS_F },
{ X86::ABS_Fp64 , X86::ABS_F },
{ X86::ABS_Fp80 , X86::ABS_F },
{ X86::ADD_Fp32m , X86::ADD_F32m },
{ X86::ADD_Fp64m , X86::ADD_F64m },
{ X86::ADD_Fp64m32 , X86::ADD_F32m },
{ X86::ADD_Fp80m32 , X86::ADD_F32m },
{ X86::ADD_Fp80m64 , X86::ADD_F64m },
{ X86::ADD_FpI16m32 , X86::ADD_FI16m },
{ X86::ADD_FpI16m64 , X86::ADD_FI16m },
{ X86::ADD_FpI16m80 , X86::ADD_FI16m },
{ X86::ADD_FpI32m32 , X86::ADD_FI32m },
{ X86::ADD_FpI32m64 , X86::ADD_FI32m },
{ X86::ADD_FpI32m80 , X86::ADD_FI32m },
{ X86::CHS_Fp32 , X86::CHS_F },
{ X86::CHS_Fp64 , X86::CHS_F },
{ X86::CHS_Fp80 , X86::CHS_F },
{ X86::CMOVBE_Fp32 , X86::CMOVBE_F },
{ X86::CMOVBE_Fp64 , X86::CMOVBE_F },
{ X86::CMOVBE_Fp80 , X86::CMOVBE_F },
{ X86::CMOVB_Fp32 , X86::CMOVB_F },
{ X86::CMOVB_Fp64 , X86::CMOVB_F },
{ X86::CMOVB_Fp80 , X86::CMOVB_F },
{ X86::CMOVE_Fp32 , X86::CMOVE_F },
{ X86::CMOVE_Fp64 , X86::CMOVE_F },
{ X86::CMOVE_Fp80 , X86::CMOVE_F },
{ X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
{ X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
{ X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
{ X86::CMOVNB_Fp32 , X86::CMOVNB_F },
{ X86::CMOVNB_Fp64 , X86::CMOVNB_F },
{ X86::CMOVNB_Fp80 , X86::CMOVNB_F },
{ X86::CMOVNE_Fp32 , X86::CMOVNE_F },
{ X86::CMOVNE_Fp64 , X86::CMOVNE_F },
{ X86::CMOVNE_Fp80 , X86::CMOVNE_F },
{ X86::CMOVNP_Fp32 , X86::CMOVNP_F },
{ X86::CMOVNP_Fp64 , X86::CMOVNP_F },
{ X86::CMOVNP_Fp80 , X86::CMOVNP_F },
{ X86::CMOVP_Fp32 , X86::CMOVP_F },
{ X86::CMOVP_Fp64 , X86::CMOVP_F },
{ X86::CMOVP_Fp80 , X86::CMOVP_F },
{ X86::COS_Fp32 , X86::COS_F },
{ X86::COS_Fp64 , X86::COS_F },
{ X86::COS_Fp80 , X86::COS_F },
{ X86::DIVR_Fp32m , X86::DIVR_F32m },
{ X86::DIVR_Fp64m , X86::DIVR_F64m },
{ X86::DIVR_Fp64m32 , X86::DIVR_F32m },
{ X86::DIVR_Fp80m32 , X86::DIVR_F32m },
{ X86::DIVR_Fp80m64 , X86::DIVR_F64m },
{ X86::DIVR_FpI16m32, X86::DIVR_FI16m},
{ X86::DIVR_FpI16m64, X86::DIVR_FI16m},
{ X86::DIVR_FpI16m80, X86::DIVR_FI16m},
{ X86::DIVR_FpI32m32, X86::DIVR_FI32m},
{ X86::DIVR_FpI32m64, X86::DIVR_FI32m},
{ X86::DIVR_FpI32m80, X86::DIVR_FI32m},
{ X86::DIV_Fp32m , X86::DIV_F32m },
{ X86::DIV_Fp64m , X86::DIV_F64m },
{ X86::DIV_Fp64m32 , X86::DIV_F32m },
{ X86::DIV_Fp80m32 , X86::DIV_F32m },
{ X86::DIV_Fp80m64 , X86::DIV_F64m },
{ X86::DIV_FpI16m32 , X86::DIV_FI16m },
{ X86::DIV_FpI16m64 , X86::DIV_FI16m },
{ X86::DIV_FpI16m80 , X86::DIV_FI16m },
{ X86::DIV_FpI32m32 , X86::DIV_FI32m },
{ X86::DIV_FpI32m64 , X86::DIV_FI32m },
{ X86::DIV_FpI32m80 , X86::DIV_FI32m },
{ X86::ILD_Fp16m32 , X86::ILD_F16m },
{ X86::ILD_Fp16m64 , X86::ILD_F16m },
{ X86::ILD_Fp16m80 , X86::ILD_F16m },
{ X86::ILD_Fp32m32 , X86::ILD_F32m },
{ X86::ILD_Fp32m64 , X86::ILD_F32m },
{ X86::ILD_Fp32m80 , X86::ILD_F32m },
{ X86::ILD_Fp64m32 , X86::ILD_F64m },
{ X86::ILD_Fp64m64 , X86::ILD_F64m },
{ X86::ILD_Fp64m80 , X86::ILD_F64m },
{ X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
{ X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
{ X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
{ X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
{ X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
{ X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
{ X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
{ X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
{ X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
{ X86::IST_Fp16m32 , X86::IST_F16m },
{ X86::IST_Fp16m64 , X86::IST_F16m },
{ X86::IST_Fp16m80 , X86::IST_F16m },
{ X86::IST_Fp32m32 , X86::IST_F32m },
{ X86::IST_Fp32m64 , X86::IST_F32m },
{ X86::IST_Fp32m80 , X86::IST_F32m },
{ X86::IST_Fp64m32 , X86::IST_FP64m },
{ X86::IST_Fp64m64 , X86::IST_FP64m },
{ X86::IST_Fp64m80 , X86::IST_FP64m },
{ X86::LD_Fp032 , X86::LD_F0 },
{ X86::LD_Fp064 , X86::LD_F0 },
{ X86::LD_Fp080 , X86::LD_F0 },
{ X86::LD_Fp132 , X86::LD_F1 },
{ X86::LD_Fp164 , X86::LD_F1 },
{ X86::LD_Fp180 , X86::LD_F1 },
{ X86::LD_Fp32m , X86::LD_F32m },
{ X86::LD_Fp32m64 , X86::LD_F32m },
{ X86::LD_Fp32m80 , X86::LD_F32m },
{ X86::LD_Fp64m , X86::LD_F64m },
{ X86::LD_Fp64m80 , X86::LD_F64m },
{ X86::LD_Fp80m , X86::LD_F80m },
{ X86::MUL_Fp32m , X86::MUL_F32m },
{ X86::MUL_Fp64m , X86::MUL_F64m },
{ X86::MUL_Fp64m32 , X86::MUL_F32m },
{ X86::MUL_Fp80m32 , X86::MUL_F32m },
{ X86::MUL_Fp80m64 , X86::MUL_F64m },
{ X86::MUL_FpI16m32 , X86::MUL_FI16m },
{ X86::MUL_FpI16m64 , X86::MUL_FI16m },
{ X86::MUL_FpI16m80 , X86::MUL_FI16m },
{ X86::MUL_FpI32m32 , X86::MUL_FI32m },
{ X86::MUL_FpI32m64 , X86::MUL_FI32m },
{ X86::MUL_FpI32m80 , X86::MUL_FI32m },
{ X86::SIN_Fp32 , X86::SIN_F },
{ X86::SIN_Fp64 , X86::SIN_F },
{ X86::SIN_Fp80 , X86::SIN_F },
{ X86::SQRT_Fp32 , X86::SQRT_F },
{ X86::SQRT_Fp64 , X86::SQRT_F },
{ X86::SQRT_Fp80 , X86::SQRT_F },
{ X86::ST_Fp32m , X86::ST_F32m },
{ X86::ST_Fp64m , X86::ST_F64m },
{ X86::ST_Fp64m32 , X86::ST_F32m },
{ X86::ST_Fp80m32 , X86::ST_F32m },
{ X86::ST_Fp80m64 , X86::ST_F64m },
{ X86::ST_FpP80m , X86::ST_FP80m },
{ X86::SUBR_Fp32m , X86::SUBR_F32m },
{ X86::SUBR_Fp64m , X86::SUBR_F64m },
{ X86::SUBR_Fp64m32 , X86::SUBR_F32m },
{ X86::SUBR_Fp80m32 , X86::SUBR_F32m },
{ X86::SUBR_Fp80m64 , X86::SUBR_F64m },
{ X86::SUBR_FpI16m32, X86::SUBR_FI16m},
{ X86::SUBR_FpI16m64, X86::SUBR_FI16m},
{ X86::SUBR_FpI16m80, X86::SUBR_FI16m},
{ X86::SUBR_FpI32m32, X86::SUBR_FI32m},
{ X86::SUBR_FpI32m64, X86::SUBR_FI32m},
{ X86::SUBR_FpI32m80, X86::SUBR_FI32m},
{ X86::SUB_Fp32m , X86::SUB_F32m },
{ X86::SUB_Fp64m , X86::SUB_F64m },
{ X86::SUB_Fp64m32 , X86::SUB_F32m },
{ X86::SUB_Fp80m32 , X86::SUB_F32m },
{ X86::SUB_Fp80m64 , X86::SUB_F64m },
{ X86::SUB_FpI16m32 , X86::SUB_FI16m },
{ X86::SUB_FpI16m64 , X86::SUB_FI16m },
{ X86::SUB_FpI16m80 , X86::SUB_FI16m },
{ X86::SUB_FpI32m32 , X86::SUB_FI32m },
{ X86::SUB_FpI32m64 , X86::SUB_FI32m },
{ X86::SUB_FpI32m80 , X86::SUB_FI32m },
{ X86::TST_Fp32 , X86::TST_F },
{ X86::TST_Fp64 , X86::TST_F },
{ X86::TST_Fp80 , X86::TST_F },
{ X86::UCOM_FpIr32 , X86::UCOM_FIr },
{ X86::UCOM_FpIr64 , X86::UCOM_FIr },
{ X86::UCOM_FpIr80 , X86::UCOM_FIr },
{ X86::UCOM_Fpr32 , X86::UCOM_Fr },
{ X86::UCOM_Fpr64 , X86::UCOM_Fr },
{ X86::UCOM_Fpr80 , X86::UCOM_Fr },
};
static unsigned getConcreteOpcode(unsigned Opcode) {
ASSERT_SORTED(OpcodeTable);
int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
return Opc;
}
static const TableEntry PopTable[] = {
{ X86::ADD_FrST0 , X86::ADD_FPrST0 },
{ X86::DIVR_FrST0, X86::DIVR_FPrST0 },
{ X86::DIV_FrST0 , X86::DIV_FPrST0 },
{ X86::IST_F16m , X86::IST_FP16m },
{ X86::IST_F32m , X86::IST_FP32m },
{ X86::MUL_FrST0 , X86::MUL_FPrST0 },
{ X86::ST_F32m , X86::ST_FP32m },
{ X86::ST_F64m , X86::ST_FP64m },
{ X86::ST_Frr , X86::ST_FPrr },
{ X86::SUBR_FrST0, X86::SUBR_FPrST0 },
{ X86::SUB_FrST0 , X86::SUB_FPrST0 },
{ X86::UCOM_FIr , X86::UCOM_FIPr },
{ X86::UCOM_FPr , X86::UCOM_FPPr },
{ X86::UCOM_Fr , X86::UCOM_FPr },
};
void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
MachineInstr* MI = I;
DebugLoc dl = MI->getDebugLoc();
ASSERT_SORTED(PopTable);
if (StackTop == 0)
report_fatal_error("Cannot pop empty stack!");
RegMap[Stack[--StackTop]] = ~0;
int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
if (Opcode != -1) {
I->setDesc(TII->get(Opcode));
if (Opcode == X86::UCOM_FPPr)
I->RemoveOperand(0);
} else { I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
}
}
void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
if (getStackEntry(0) == FPRegNo) { popStackAfter(I);
return;
}
I = freeStackSlotBefore(++I, FPRegNo);
}
MachineBasicBlock::iterator
FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
unsigned STReg = getSTReg(FPRegNo);
unsigned OldSlot = getSlot(FPRegNo);
unsigned TopReg = Stack[StackTop-1];
Stack[OldSlot] = TopReg;
RegMap[TopReg] = OldSlot;
RegMap[FPRegNo] = ~0;
Stack[--StackTop] = ~0;
return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)).addReg(STReg);
}
void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
unsigned Defs = Mask;
unsigned Kills = 0;
for (unsigned i = 0; i < StackTop; ++i) {
unsigned RegNo = Stack[i];
if (!(Defs & (1 << RegNo)))
Kills |= (1 << RegNo);
else
Defs &= ~(1 << RegNo);
}
assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
while (Kills && Defs) {
unsigned KReg = countTrailingZeros(Kills);
unsigned DReg = countTrailingZeros(Defs);
DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n");
std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
std::swap(RegMap[KReg], RegMap[DReg]);
Kills &= ~(1 << KReg);
Defs &= ~(1 << DReg);
}
if (Kills && I != MBB->begin()) {
MachineBasicBlock::iterator I2 = std::prev(I);
while (StackTop) {
unsigned KReg = getStackEntry(0);
if (!(Kills & (1 << KReg)))
break;
DEBUG(dbgs() << "Popping %FP" << KReg << "\n");
popStackAfter(I2);
Kills &= ~(1 << KReg);
}
}
while (Kills) {
unsigned KReg = countTrailingZeros(Kills);
DEBUG(dbgs() << "Killing %FP" << KReg << "\n");
freeStackSlotBefore(I, KReg);
Kills &= ~(1 << KReg);
}
while(Defs) {
unsigned DReg = countTrailingZeros(Defs);
DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n");
BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
pushReg(DReg);
Defs &= ~(1 << DReg);
}
DEBUG(dumpStack());
assert(StackTop == CountPopulation_32(Mask) && "Live count mismatch");
}
void FPS::shuffleStackTop(const unsigned char *FixStack,
unsigned FixCount,
MachineBasicBlock::iterator I) {
while (FixCount--) {
unsigned OldReg = getStackEntry(FixCount);
unsigned Reg = FixStack[FixCount];
if (Reg == OldReg)
continue;
moveToTop(Reg, I);
if (FixCount > 0)
moveToTop(OldReg, I);
}
DEBUG(dumpStack());
}
void FPS::handleCall(MachineBasicBlock::iterator &I) {
unsigned STReturns = 0;
for (const auto &MO : I->operands()) {
if (!MO.isReg())
continue;
unsigned R = MO.getReg() - X86::FP0;
if (R < 8) {
assert(MO.isDef() && MO.isImplicit());
STReturns |= 1 << R;
}
}
unsigned N = CountTrailingOnes_32(STReturns);
assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2));
for (unsigned I = 0; I < N; ++I)
pushReg(N - I - 1);
}
void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
unsigned DestReg = getFPReg(MI->getOperand(0));
MI->RemoveOperand(0); MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
pushReg(DestReg);
}
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
unsigned NumOps = MI->getDesc().getNumOperands();
assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
"Can only handle fst* & ftst instructions!");
unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
if (!KillsSrc &&
(MI->getOpcode() == X86::IST_Fp64m32 ||
MI->getOpcode() == X86::ISTT_Fp16m32 ||
MI->getOpcode() == X86::ISTT_Fp32m32 ||
MI->getOpcode() == X86::ISTT_Fp64m32 ||
MI->getOpcode() == X86::IST_Fp64m64 ||
MI->getOpcode() == X86::ISTT_Fp16m64 ||
MI->getOpcode() == X86::ISTT_Fp32m64 ||
MI->getOpcode() == X86::ISTT_Fp64m64 ||
MI->getOpcode() == X86::IST_Fp64m80 ||
MI->getOpcode() == X86::ISTT_Fp16m80 ||
MI->getOpcode() == X86::ISTT_Fp32m80 ||
MI->getOpcode() == X86::ISTT_Fp64m80 ||
MI->getOpcode() == X86::ST_FpP80m)) {
duplicateToTop(Reg, ScratchFPReg, I);
} else {
moveToTop(Reg, I); }
MI->RemoveOperand(NumOps-1); MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
if (MI->getOpcode() == X86::IST_FP64m ||
MI->getOpcode() == X86::ISTT_FP16m ||
MI->getOpcode() == X86::ISTT_FP32m ||
MI->getOpcode() == X86::ISTT_FP64m ||
MI->getOpcode() == X86::ST_FP80m) {
if (StackTop == 0)
report_fatal_error("Stack empty??");
--StackTop;
} else if (KillsSrc) { popStackAfter(I);
}
}
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
#ifndef NDEBUG
unsigned NumOps = MI->getDesc().getNumOperands();
assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
#endif
unsigned Reg = getFPReg(MI->getOperand(1));
bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
if (KillsSrc) {
moveToTop(Reg, I);
if (StackTop == 0)
report_fatal_error("Stack cannot be empty!");
--StackTop;
pushReg(getFPReg(MI->getOperand(0)));
} else {
duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
}
MI->RemoveOperand(1); MI->RemoveOperand(0); MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
}
static const TableEntry ForwardST0Table[] = {
{ X86::ADD_Fp32 , X86::ADD_FST0r },
{ X86::ADD_Fp64 , X86::ADD_FST0r },
{ X86::ADD_Fp80 , X86::ADD_FST0r },
{ X86::DIV_Fp32 , X86::DIV_FST0r },
{ X86::DIV_Fp64 , X86::DIV_FST0r },
{ X86::DIV_Fp80 , X86::DIV_FST0r },
{ X86::MUL_Fp32 , X86::MUL_FST0r },
{ X86::MUL_Fp64 , X86::MUL_FST0r },
{ X86::MUL_Fp80 , X86::MUL_FST0r },
{ X86::SUB_Fp32 , X86::SUB_FST0r },
{ X86::SUB_Fp64 , X86::SUB_FST0r },
{ X86::SUB_Fp80 , X86::SUB_FST0r },
};
static const TableEntry ReverseST0Table[] = {
{ X86::ADD_Fp32 , X86::ADD_FST0r }, { X86::ADD_Fp64 , X86::ADD_FST0r }, { X86::ADD_Fp80 , X86::ADD_FST0r }, { X86::DIV_Fp32 , X86::DIVR_FST0r },
{ X86::DIV_Fp64 , X86::DIVR_FST0r },
{ X86::DIV_Fp80 , X86::DIVR_FST0r },
{ X86::MUL_Fp32 , X86::MUL_FST0r }, { X86::MUL_Fp64 , X86::MUL_FST0r }, { X86::MUL_Fp80 , X86::MUL_FST0r }, { X86::SUB_Fp32 , X86::SUBR_FST0r },
{ X86::SUB_Fp64 , X86::SUBR_FST0r },
{ X86::SUB_Fp80 , X86::SUBR_FST0r },
};
static const TableEntry ForwardSTiTable[] = {
{ X86::ADD_Fp32 , X86::ADD_FrST0 }, { X86::ADD_Fp64 , X86::ADD_FrST0 }, { X86::ADD_Fp80 , X86::ADD_FrST0 }, { X86::DIV_Fp32 , X86::DIVR_FrST0 },
{ X86::DIV_Fp64 , X86::DIVR_FrST0 },
{ X86::DIV_Fp80 , X86::DIVR_FrST0 },
{ X86::MUL_Fp32 , X86::MUL_FrST0 }, { X86::MUL_Fp64 , X86::MUL_FrST0 }, { X86::MUL_Fp80 , X86::MUL_FrST0 }, { X86::SUB_Fp32 , X86::SUBR_FrST0 },
{ X86::SUB_Fp64 , X86::SUBR_FrST0 },
{ X86::SUB_Fp80 , X86::SUBR_FrST0 },
};
static const TableEntry ReverseSTiTable[] = {
{ X86::ADD_Fp32 , X86::ADD_FrST0 },
{ X86::ADD_Fp64 , X86::ADD_FrST0 },
{ X86::ADD_Fp80 , X86::ADD_FrST0 },
{ X86::DIV_Fp32 , X86::DIV_FrST0 },
{ X86::DIV_Fp64 , X86::DIV_FrST0 },
{ X86::DIV_Fp80 , X86::DIV_FrST0 },
{ X86::MUL_Fp32 , X86::MUL_FrST0 },
{ X86::MUL_Fp64 , X86::MUL_FrST0 },
{ X86::MUL_Fp80 , X86::MUL_FrST0 },
{ X86::SUB_Fp32 , X86::SUB_FrST0 },
{ X86::SUB_Fp64 , X86::SUB_FrST0 },
{ X86::SUB_Fp80 , X86::SUB_FrST0 },
};
void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
unsigned NumOperands = MI->getDesc().getNumOperands();
assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
unsigned Dest = getFPReg(MI->getOperand(0));
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
DebugLoc dl = MI->getDebugLoc();
unsigned TOS = getStackEntry(0);
if (Op0 != TOS && Op1 != TOS) { if (KillsOp0) {
moveToTop(Op0, I); TOS = Op0;
} else if (KillsOp1) {
moveToTop(Op1, I);
TOS = Op1;
} else {
duplicateToTop(Op0, Dest, I);
Op0 = TOS = Dest;
KillsOp0 = true;
}
} else if (!KillsOp0 && !KillsOp1) {
duplicateToTop(Op0, Dest, I);
Op0 = TOS = Dest;
KillsOp0 = true;
}
assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
"Stack conditions not set up right!");
const TableEntry *InstTable;
bool isForward = TOS == Op0;
bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
if (updateST0) {
if (isForward)
InstTable = ForwardST0Table;
else
InstTable = ReverseST0Table;
} else {
if (isForward)
InstTable = ForwardSTiTable;
else
InstTable = ReverseSTiTable;
}
int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
MI->getOpcode());
assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
MBB->remove(I++);
I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
if (KillsOp0 && KillsOp1 && Op0 != Op1) {
assert(!updateST0 && "Should have updated other operand!");
popStackAfter(I); }
unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
assert(UpdatedSlot < StackTop && Dest < 7);
Stack[UpdatedSlot] = Dest;
RegMap[Dest] = UpdatedSlot;
MBB->getParent()->DeleteMachineInstr(MI); }
void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
unsigned NumOperands = MI->getDesc().getNumOperands();
assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
moveToTop(Op0, I);
MI->getOperand(0).setReg(getSTReg(Op1));
MI->RemoveOperand(1);
MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
if (KillsOp0) freeStackSlotAfter(I, Op0);
if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
}
void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
unsigned Op0 = getFPReg(MI->getOperand(0));
unsigned Op1 = getFPReg(MI->getOperand(2));
bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
moveToTop(Op0, I);
MI->RemoveOperand(0);
MI->RemoveOperand(1);
MI->getOperand(0).setReg(getSTReg(Op1));
MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
if (Op0 != Op1 && KillsOp1) {
freeStackSlotAfter(I, Op1);
}
}
void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
MachineInstr *MI = Inst;
if (MI->isCall()) {
handleCall(Inst);
return;
}
switch (MI->getOpcode()) {
default: llvm_unreachable("Unknown SpecialFP instruction!");
case TargetOpcode::COPY: {
const MachineOperand &MO1 = MI->getOperand(1);
const MachineOperand &MO0 = MI->getOperand(0);
bool KillsSrc = MI->killsRegister(MO1.getReg());
unsigned DstFP = getFPReg(MO0);
unsigned SrcFP = getFPReg(MO1);
assert(isLive(SrcFP) && "Cannot copy dead register");
if (KillsSrc) {
unsigned Slot = getSlot(SrcFP);
Stack[Slot] = DstFP;
RegMap[DstFP] = Slot;
} else {
duplicateToTop(SrcFP, DstFP, Inst);
}
break;
}
case TargetOpcode::IMPLICIT_DEF: {
unsigned Reg = MI->getOperand(0).getReg() - X86::FP0;
DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n');
BuildMI(*MBB, Inst, MI->getDebugLoc(), TII->get(X86::LD_F0));
pushReg(Reg);
break;
}
case TargetOpcode::INLINEASM: {
unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;
unsigned NumOps = 0;
SmallSet<unsigned, 1> FRegIdx;
unsigned RCID;
for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) {
unsigned Flags = MI->getOperand(i).getImm();
NumOps = InlineAsm::getNumOperandRegisters(Flags);
if (NumOps != 1)
continue;
const MachineOperand &MO = MI->getOperand(i + 1);
if (!MO.isReg())
continue;
unsigned STReg = MO.getReg() - X86::FP0;
if (STReg >= 8)
continue;
if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
FRegIdx.insert(i + 1);
continue;
}
switch (InlineAsm::getKind(Flags)) {
case InlineAsm::Kind_RegUse:
STUses |= (1u << STReg);
break;
case InlineAsm::Kind_RegDef:
case InlineAsm::Kind_RegDefEarlyClobber:
STDefs |= (1u << STReg);
if (MO.isDead())
STDeadDefs |= (1u << STReg);
break;
case InlineAsm::Kind_Clobber:
STClobbers |= (1u << STReg);
break;
default:
break;
}
}
if (STUses && !isMask_32(STUses))
MI->emitError("fixed input regs must be last on the x87 stack");
unsigned NumSTUses = CountTrailingOnes_32(STUses);
if (STDefs && !isMask_32(STDefs)) {
MI->emitError("output regs must be last on the x87 stack");
STDefs = NextPowerOf2(STDefs) - 1;
}
unsigned NumSTDefs = CountTrailingOnes_32(STDefs);
if (STClobbers && !isMask_32(STDefs | STClobbers))
MI->emitError("clobbers must be last on the x87 stack");
unsigned STPopped = STUses & (STDefs | STClobbers);
if (STPopped && !isMask_32(STPopped))
MI->emitError("implicitly popped regs must be last on the x87 stack");
unsigned NumSTPopped = CountTrailingOnes_32(STPopped);
DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
<< NumSTPopped << ", and defines " << NumSTDefs << " regs.\n");
#ifndef NDEBUG
for (unsigned I = 0, E = MI->getNumOperands(); I < E; ++I)
if (FRegIdx.count(I)) {
assert((1 << getFPReg(MI->getOperand(I)) & STDefs) == 0 &&
"Operands with constraint \"f\" cannot overlap with defs");
}
#endif
unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &Op = MI->getOperand(i);
if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
continue;
unsigned FPReg = getFPReg(Op);
if (Op.isUse() && Op.isKill())
FPKills |= 1U << FPReg;
}
FPKills &= ~(STDefs | STClobbers);
unsigned char STUsesArray[8];
for (unsigned I = 0; I < NumSTUses; ++I)
STUsesArray[I] = I;
shuffleStackTop(STUsesArray, NumSTUses, Inst);
DEBUG({dbgs() << "Before asm: "; dumpStack();});
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &Op = MI->getOperand(i);
if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
continue;
unsigned FPReg = getFPReg(Op);
if (FRegIdx.count(i))
Op.setReg(getSTReg(FPReg));
else
Op.setReg(X86::ST0 + FPReg);
}
StackTop -= NumSTPopped;
for (unsigned i = 0; i < NumSTDefs; ++i)
pushReg(NumSTDefs - i - 1);
while (FPKills) {
unsigned FPReg = countTrailingZeros(FPKills);
if (isLive(FPReg))
freeStackSlotAfter(Inst, FPReg);
FPKills &= ~(1U << FPReg);
}
return;
}
case X86::WIN_FTOL_32:
case X86::WIN_FTOL_64: {
MachineOperand &Op = MI->getOperand(0);
assert(Op.isUse() && Op.isReg() &&
Op.getReg() >= X86::FP0 && Op.getReg() <= X86::FP6);
unsigned FPReg = getFPReg(Op);
if (Op.isKill())
moveToTop(FPReg, Inst);
else
duplicateToTop(FPReg, FPReg, Inst);
BuildMI(*MBB, Inst, MI->getDebugLoc(), TII->get(X86::CALLpcrel32))
.addExternalSymbol("_ftol2")
.addReg(X86::ST0, RegState::ImplicitKill)
.addReg(X86::ECX, RegState::ImplicitDefine)
.addReg(X86::EAX, RegState::Define | RegState::Implicit)
.addReg(X86::EDX, RegState::Define | RegState::Implicit)
.addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
--StackTop;
break;
}
case X86::RETQ:
case X86::RETL:
case X86::RETIL:
case X86::RETIQ:
unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
unsigned LiveMask = 0;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &Op = MI->getOperand(i);
if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
continue;
assert(Op.isUse() &&
(Op.isKill() || getFPReg(Op) == FirstFPRegOp || MI->killsRegister(Op.getReg())) && "Ret only defs operands, and values aren't live beyond it");
if (FirstFPRegOp == ~0U)
FirstFPRegOp = getFPReg(Op);
else {
assert(SecondFPRegOp == ~0U && "More than two fp operands!");
SecondFPRegOp = getFPReg(Op);
}
LiveMask |= (1 << getFPReg(Op));
MI->RemoveOperand(i);
--i, --e;
}
adjustLiveRegs(LiveMask, MI);
if (!LiveMask) return;
if (SecondFPRegOp == ~0U) {
assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
"Top of stack not the right register for RET!");
StackTop = 0;
return;
}
if (StackTop == 1) {
assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
"Stack misconfiguration for RET!");
unsigned NewReg = ScratchFPReg;
duplicateToTop(FirstFPRegOp, NewReg, MI);
FirstFPRegOp = NewReg;
}
assert(StackTop == 2 && "Must have two values live!");
if (getStackEntry(0) == SecondFPRegOp) {
assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
moveToTop(FirstFPRegOp, MI);
}
assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
StackTop = 0;
return;
}
Inst = MBB->erase(Inst);
if (Inst == MBB->begin()) {
DEBUG(dbgs() << "Inserting dummy KILL\n");
Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
} else
--Inst;
}
void FPS::setKillFlags(MachineBasicBlock &MBB) const {
const TargetRegisterInfo *TRI =
MBB.getParent()->getSubtarget().getRegisterInfo();
LivePhysRegs LPR(TRI);
LPR.addLiveOuts(&MBB);
for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
I != E; ++I) {
if (I->isDebugValue())
continue;
BitVector Defs(8);
SmallVector<MachineOperand *, 2> Uses;
MachineInstr &MI = *I;
for (auto &MO : I->operands()) {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg() - X86::FP0;
if (Reg >= 8)
continue;
if (MO.isDef()) {
Defs.set(Reg);
if (!LPR.contains(MO.getReg()))
MO.setIsDead();
} else
Uses.push_back(&MO);
}
for (auto *MO : Uses)
if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg()))
MO->setIsKill();
LPR.stepBackward(MI);
}
}