SIMCCodeEmitter.cpp [plain text]
#include "AMDGPU.h"
#include "SIDefines.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
#include "MCTargetDesc/AMDGPUFixupKinds.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace {
typedef union {
int32_t I;
float F;
} IntFloatUnion;
class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
SIMCCodeEmitter(const SIMCCodeEmitter &) LLVM_DELETED_FUNCTION;
void operator=(const SIMCCodeEmitter &) LLVM_DELETED_FUNCTION;
const MCInstrInfo &MCII;
const MCRegisterInfo &MRI;
MCContext &Ctx;
bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
uint32_t getLitEncoding(const MCOperand &MO) const;
public:
SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
MCContext &ctx)
: MCII(mcii), MRI(mri), Ctx(ctx) { }
~SIMCCodeEmitter() { }
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const override;
};
}
MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
return new SIMCCodeEmitter(MCII, MRI, Ctx);
}
bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc,
unsigned OpNo) const {
if (OpNo == 1 && (Desc.TSFlags & (SIInstrFlags::VOP1 | SIInstrFlags::VOP2 |
SIInstrFlags::VOPC)))
return true;
unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
return (AMDGPU::SSrc_32RegClassID == RegClass) ||
(AMDGPU::SSrc_64RegClassID == RegClass) ||
(AMDGPU::VSrc_32RegClassID == RegClass) ||
(AMDGPU::VSrc_64RegClassID == RegClass);
}
uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO) const {
IntFloatUnion Imm;
if (MO.isImm())
Imm.I = MO.getImm();
else if (MO.isFPImm())
Imm.F = MO.getFPImm();
else if (MO.isExpr())
return 255;
else
return ~0;
if (Imm.I >= 0 && Imm.I <= 64)
return 128 + Imm.I;
if (Imm.I >= -16 && Imm.I <= -1)
return 192 + abs(Imm.I);
if (Imm.F == 0.5f)
return 240;
if (Imm.F == -0.5f)
return 241;
if (Imm.F == 1.0f)
return 242;
if (Imm.F == -1.0f)
return 243;
if (Imm.F == 2.0f)
return 244;
if (Imm.F == -2.0f)
return 245;
if (Imm.F == 4.0f)
return 246;
if (Imm.F == -4.0f)
return 247;
return 255;
}
void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
unsigned bytes = Desc.getSize();
for (unsigned i = 0; i < bytes; i++) {
OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
}
if (bytes > 4)
return;
for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
if (!isSrcOperand(Desc, i))
continue;
const MCOperand &Op = MI.getOperand(i);
if (getLitEncoding(Op) != 255)
continue;
IntFloatUnion Imm;
if (Op.isImm())
Imm.I = Op.getImm();
else if (Op.isFPImm())
Imm.F = Op.getFPImm();
else {
assert(Op.isExpr());
Imm.I = 0;
}
for (unsigned j = 0; j < 4; j++) {
OS.write((uint8_t) ((Imm.I >> (8 * j)) & 0xff));
}
break;
}
}
unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isExpr()) {
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
return 0;
}
return getMachineOpValue(MI, MO, Fixups, STI);
}
uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
if (MO.isReg())
return MRI.getEncodingValue(MO.getReg());
if (MO.isExpr()) {
const MCSymbolRefExpr *Expr = cast<MCSymbolRefExpr>(MO.getExpr());
MCFixupKind Kind;
const MCSymbol *Sym =
Ctx.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
if (&Expr->getSymbol() == Sym) {
Kind = (MCFixupKind)AMDGPU::fixup_si_end_of_text;
} else {
Kind = (MCFixupKind)AMDGPU::fixup_si_rodata;
}
Fixups.push_back(MCFixup::Create(4, Expr, Kind, MI.getLoc()));
}
unsigned OpNo = 0;
for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
if (&MO == &MI.getOperand(OpNo))
break;
}
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
if (isSrcOperand(Desc, OpNo)) {
uint32_t Enc = getLitEncoding(MO);
if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
return Enc;
} else if (MO.isImm())
return MO.getImm();
llvm_unreachable("Encoding of this operand type is not supported yet.");
return 0;
}