AArch64Subtarget.h [plain text]
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
#include "AArch64FrameLowering.h"
#include "AArch64ISelLowering.h"
#include "AArch64InstrInfo.h"
#include "AArch64RegisterInfo.h"
#include "AArch64SelectionDAGInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
#include "AArch64GenSubtargetInfo.inc"
namespace llvm {
class GlobalValue;
class StringRef;
class AArch64Subtarget : public AArch64GenSubtargetInfo {
protected:
enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
ARMProcFamilyEnum ARMProcFamily;
bool HasFPARMv8;
bool HasNEON;
bool HasCrypto;
bool HasCRC;
bool HasZeroCycleRegMove;
bool HasZeroCycleZeroing;
bool HasAddressTopByteIgnored;
std::string CPUString;
Triple TargetTriple;
bool IsLittleEndian;
const DataLayout DL;
AArch64FrameLowering FrameLowering;
AArch64InstrInfo InstrInfo;
AArch64SelectionDAGInfo TSInfo;
AArch64TargetLowering TLInfo;
private:
AArch64Subtarget &initializeSubtargetDependencies(StringRef FS);
public:
AArch64Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, TargetMachine &TM, bool LittleEndian);
const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
return &TSInfo;
}
const AArch64FrameLowering *getFrameLowering() const override {
return &FrameLowering;
}
const AArch64TargetLowering *getTargetLowering() const override {
return &TLInfo;
}
const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
const DataLayout *getDataLayout() const override { return &DL; }
const AArch64RegisterInfo *getRegisterInfo() const override {
return &getInstrInfo()->getRegisterInfo();
}
bool enableMachineScheduler() const override { return true; }
bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
bool hasFPARMv8() const { return HasFPARMv8; }
bool hasNEON() const { return HasNEON; }
bool hasCrypto() const { return HasCrypto; }
bool hasCRC() const { return HasCRC; }
bool supportsAddressTopByteIgnored() const;
bool isLittleEndian() const { return DL.isLittleEndian(); }
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
bool isTargetIOS() const { return TargetTriple.isiOS(); }
bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
bool isCyclone() const { return CPUString == "cyclone"; }
bool isCortexA57() const { return CPUString == "cortex-a57"; }
bool isCortexA53() const { return CPUString == "cortex-a53"; }
unsigned getMaxInlineSizeThreshold() const { return 64; }
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
unsigned char ClassifyGlobalReference(const GlobalValue *GV,
const TargetMachine &TM) const;
const char *getBZeroEntry() const;
void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
MachineInstr *end,
unsigned NumRegionInstrs) const override;
bool enableEarlyIfConversion() const override;
};
}
#endif