ARM64StorePairSuppress.cpp [plain text]
#define DEBUG_TYPE "arm64-stp-suppress"
#include "ARM64InstrInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace {
class ARM64StorePairSuppress : public MachineFunctionPass {
const ARM64InstrInfo *TII;
const TargetRegisterInfo *TRI;
const MachineRegisterInfo *MRI;
MachineFunction *MF;
TargetSchedModel SchedModel;
MachineTraceMetrics *Traces;
MachineTraceMetrics::Ensemble *MinInstr;
public:
static char ID;
ARM64StorePairSuppress() : MachineFunctionPass(ID) {}
virtual const char *getPassName() const {
return "ARM64 Store Pair Suppression";
}
bool runOnMachineFunction(MachineFunction &F);
private:
bool shouldAddSTPToBlock(const MachineBasicBlock* BB);
bool isNarrowFPStore(const MachineInstr *MI);
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineTraceMetrics>();
AU.addPreserved<MachineTraceMetrics>();
MachineFunctionPass::getAnalysisUsage(AU);
}
};
char ARM64StorePairSuppress::ID = 0;
}
FunctionPass *llvm::createARM64StorePairSuppressPass() {
return new ARM64StorePairSuppress();
}
bool ARM64StorePairSuppress::shouldAddSTPToBlock(const MachineBasicBlock* BB) {
if (!MinInstr)
MinInstr = Traces->getEnsemble(MachineTraceMetrics::TS_MinInstrCount);
MachineTraceMetrics::Trace BBTrace = MinInstr->getTrace(BB);
unsigned ResLength = BBTrace.getResourceLength();
unsigned SCIdx = TII->get(ARM64::STPDi).getSchedClass();
const MCSchedClassDesc *SCDesc =
SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx);
if (SCDesc->isValid() && !SCDesc->isVariant()) {
unsigned ResLenWithSTP =
BBTrace.getResourceLength(ArrayRef<const MachineBasicBlock*>(), SCDesc);
if (ResLenWithSTP > ResLength) {
DEBUG(dbgs()
<< " Suppress STP in BB: " << BB->getNumber()
<< " resources " << ResLength << " -> " << ResLenWithSTP << "\n");
return false;
}
}
return true;
}
bool ARM64StorePairSuppress::isNarrowFPStore(const MachineInstr *MI) {
switch (MI->getOpcode()) {
default:
return false;
case ARM64::STRSui:
case ARM64::STRDui:
case ARM64::STURSi:
case ARM64::STURDi:
return true;
}
}
bool ARM64StorePairSuppress::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
TII = static_cast<const ARM64InstrInfo*>(MF->getTarget().getInstrInfo());
TRI = MF->getTarget().getRegisterInfo();
MRI = &MF->getRegInfo();
const TargetSubtargetInfo &ST =
MF->getTarget().getSubtarget<TargetSubtargetInfo>();
SchedModel.init(*ST.getSchedModel(), &ST, TII);
Traces = &getAnalysis<MachineTraceMetrics>();
MinInstr = 0;
DEBUG(dbgs() << "*** " << getPassName() << ": " << MF->getName() << '\n' );
if (!SchedModel.hasInstrSchedModel()) {
DEBUG(dbgs() << " Skipping pass: no machine model present.\n");
return false;
}
for (MachineFunction::iterator
BI = MF->begin(), BE = MF->end(); BI != BE; ++BI) {
bool SuppressSTP = false;
unsigned PrevBaseReg = 0;
for (MachineBasicBlock::iterator
I = BI->begin(), E = BI->end(); I != E; ++I) {
if (!isNarrowFPStore(I))
continue;
unsigned BaseReg;
unsigned Offset;
if (TII->getLdStBaseRegImmOfs(I, BaseReg, Offset, TRI)) {
if (PrevBaseReg == BaseReg) {
if (!SuppressSTP && shouldAddSTPToBlock(I->getParent()))
break;
DEBUG(dbgs() << "Unpairing store " << *I << "\n");
SuppressSTP = true;
TII->suppressLdStPair(I);
}
PrevBaseReg = BaseReg;
}
else
PrevBaseReg = 0;
}
}
return false;
}