ARM64RegisterInfo.h [plain text]
#ifndef LLVM_TARGET_ARM64REGISTERINFO_H
#define LLVM_TARGET_ARM64REGISTERINFO_H
#define GET_REGINFO_HEADER
#include "ARM64GenRegisterInfo.inc"
namespace llvm {
class ARM64InstrInfo;
class ARM64Subtarget;
class MachineFunction;
class RegScavenger;
class TargetRegisterClass;
struct ARM64RegisterInfo : public ARM64GenRegisterInfo {
private:
const ARM64InstrInfo *TII;
const ARM64Subtarget *STI;
public:
ARM64RegisterInfo(const ARM64InstrInfo *tii, const ARM64Subtarget *sti);
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const uint32_t *getCallPreservedMask(CallingConv::ID) const;
unsigned getCSRFirstUseCost() const {
return 5;
}
const uint32_t *getTLSCallPreservedMask() const;
const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
const TargetRegisterClass* getPointerRegClass(const MachineFunction &MF,
unsigned Kind = 0) const;
const TargetRegisterClass*
getCrossCopyRegClass(const TargetRegisterClass *RC) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const;
bool useFPForScavengingIndex(const MachineFunction &MF) const;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
void materializeFrameBaseRegister(MachineBasicBlock *MBB,
unsigned BaseReg, int FrameIdx,
int64_t Offset) const;
void resolveFrameIndex(MachineBasicBlock::iterator I,
unsigned BaseReg, int64_t Offset) const;
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = NULL) const;
bool cannotEliminateFrame(const MachineFunction &MF) const;
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
bool hasBasePointer(const MachineFunction &MF) const;
unsigned getBaseRegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const;
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const;
};
}
#endif // LLVM_TARGET_ARM64REGISTERINFO_H