AArch64ISelLowering.h [plain text]
#ifndef LLVM_TARGET_AARCH64_ISELLOWERING_H
#define LLVM_TARGET_AARCH64_ISELLOWERING_H
#include "Utils/AArch64BaseInfo.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Target/TargetLowering.h"
namespace llvm {
namespace AArch64ISD {
enum NodeType {
FIRST_NUMBER = ISD::BUILTIN_OP_END,
BR_CC,
Call,
FPMOV,
EXTR,
GOTLoad,
BFI,
Ret,
SBFX,
SELECT_CC,
SETCC,
TC_RETURN,
TLSDESCCALL,
THREAD_POINTER,
UBFX,
WrapperLarge,
WrapperSmall,
NEON_MOVIMM,
NEON_MVNIMM,
NEON_FMOVIMM,
NEON_UZP1,
NEON_UZP2,
NEON_ZIP1,
NEON_ZIP2,
NEON_TRN1,
NEON_TRN2,
NEON_REV64,
NEON_REV32,
NEON_REV16,
NEON_CMP,
NEON_CMPZ,
NEON_TST,
NEON_QSHLs,
NEON_QSHLu,
NEON_VDUP,
NEON_VDUPLANE,
NEON_VEXTRACT,
NEON_LD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
NEON_LD3DUP,
NEON_LD4DUP,
NEON_LD1_UPD,
NEON_LD2_UPD,
NEON_LD3_UPD,
NEON_LD4_UPD,
NEON_LD1x2_UPD,
NEON_LD1x3_UPD,
NEON_LD1x4_UPD,
NEON_ST1_UPD,
NEON_ST2_UPD,
NEON_ST3_UPD,
NEON_ST4_UPD,
NEON_ST1x2_UPD,
NEON_ST1x3_UPD,
NEON_ST1x4_UPD,
NEON_LD2DUP_UPD,
NEON_LD3DUP_UPD,
NEON_LD4DUP_UPD,
NEON_LD2LN_UPD,
NEON_LD3LN_UPD,
NEON_LD4LN_UPD,
NEON_ST2LN_UPD,
NEON_ST3LN_UPD,
NEON_ST4LN_UPD
};
}
class AArch64Subtarget;
class AArch64TargetMachine;
class AArch64TargetLowering : public TargetLowering {
public:
explicit AArch64TargetLowering(AArch64TargetMachine &TM);
const char *getTargetNodeName(unsigned Opcode) const;
CCAssignFn *CCAssignFnForNode(CallingConv::ID CC) const;
SDValue LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
SDLoc dl, SelectionDAG &DAG) const;
virtual unsigned getByValTypeAlignment(Type *Ty) const LLVM_OVERRIDE;
SDValue LowerCall(CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &Res) const;
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
const AArch64Subtarget *ST) const;
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
void SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
SDValue &Chain) const;
bool IsEligibleForTailCallOptimization(SDValue Callee,
CallingConv::ID CalleeCC,
bool IsVarArg,
bool IsCalleeStructRet,
bool IsCallerStructRet,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const;
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
MachineFrameInfo *MFI, int ClobberedFI) const;
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
bool IsTailCallConvention(CallingConv::ID CallCC) const;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
bool isLegalICmpImmediate(int64_t Val) const;
SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &A64cc, SelectionDAG &DAG, SDLoc &dl) const;
virtual MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
MachineBasicBlock *
emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB,
unsigned Size, unsigned Opcode) const;
MachineBasicBlock *
emitAtomicBinaryMinMax(MachineInstr *MI, MachineBasicBlock *BB,
unsigned Size, unsigned CmpOp,
A64CC::CondCodes Cond) const;
MachineBasicBlock *
emitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB,
unsigned Size) const;
MachineBasicBlock *
EmitF128CSEL(MachineInstr *MI, MachineBasicBlock *MBB) const;
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
RTLIB::Libcall Call) const;
SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddressELFSmall(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddressELFLarge(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL,
SelectionDAG &DAG) const;
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool IsSigned) const;
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
ConstraintType getConstraintType(const std::string &Constraint) const;
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info,
const char *Constraint) const;
void LowerAsmOperandForConstraint(SDValue Op,
std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
unsigned Intrinsic) const LLVM_OVERRIDE;
protected:
std::pair<const TargetRegisterClass*, uint8_t>
findRepresentativeClass(MVT VT) const;
private:
const InstrItineraryData *Itins;
const AArch64Subtarget *getSubtarget() const {
return &getTargetMachine().getSubtarget<AArch64Subtarget>();
}
};
enum NeonModImmType {
Neon_Mov_Imm,
Neon_Mvn_Imm
};
extern SDValue ScanBUILD_VECTOR(SDValue Op, bool &isOnlyLowElement,
bool &usesOnlyOneValue, bool &hasDominantValue,
bool &isConstant, bool &isUNDEF);
}
#endif // LLVM_TARGET_AARCH64_ISELLOWERING_H