#ifndef LLVM_MC_MCSUBTARGET_H
#define LLVM_MC_MCSUBTARGET_H
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/SubtargetFeature.h"
#include <string>
namespace llvm {
class StringRef;
class MCSubtargetInfo {
std::string TargetTriple; const SubtargetFeatureKV *ProcFeatures; const SubtargetFeatureKV *ProcDesc;
const SubtargetInfoKV *ProcSchedModels;
const MCWriteProcResEntry *WriteProcResTable;
const MCWriteLatencyEntry *WriteLatencyTable;
const MCReadAdvanceEntry *ReadAdvanceTable;
const MCSchedModel *CPUSchedModel;
const InstrStage *Stages; const unsigned *OperandCycles; const unsigned *ForwardingPaths; unsigned NumFeatures; unsigned NumProcs; uint64_t FeatureBits;
public:
void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
const SubtargetFeatureKV *PF,
const SubtargetFeatureKV *PD,
const SubtargetInfoKV *ProcSched,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA,
const InstrStage *IS,
const unsigned *OC, const unsigned *FP,
unsigned NF, unsigned NP);
StringRef getTargetTriple() const {
return TargetTriple;
}
uint64_t getFeatureBits() const {
return FeatureBits;
}
void InitMCProcessorInfo(StringRef CPU, StringRef FS);
void InitCPUSchedModel(StringRef CPU);
uint64_t ToggleFeature(uint64_t FB);
uint64_t ToggleFeature(StringRef FS);
const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
const MCSchedModel *getSchedModel() const { return CPUSchedModel; }
const MCWriteProcResEntry *getWriteProcResBegin(
const MCSchedClassDesc *SC) const {
return &WriteProcResTable[SC->WriteProcResIdx];
}
const MCWriteProcResEntry *getWriteProcResEnd(
const MCSchedClassDesc *SC) const {
return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
}
const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
unsigned DefIdx) const {
assert(DefIdx < SC->NumWriteLatencyEntries &&
"MachineModel does not specify a WriteResource for DefIdx");
return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
}
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
unsigned WriteResID) const {
for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
*E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
if (I->UseIdx < UseIdx)
continue;
if (I->UseIdx > UseIdx)
break;
if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
return I->Cycles;
}
}
return 0;
}
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
void initInstrItins(InstrItineraryData &InstrItins) const;
};
}
#endif