SystemZInstrInfo.h [plain text]
#ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
#define LLVM_TARGET_SYSTEMZINSTRINFO_H
#include "SystemZ.h"
#include "SystemZRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "SystemZGenInstrInfo.inc"
namespace llvm {
class SystemZTargetMachine;
namespace SystemZII {
enum {
SimpleBDXLoad = (1 << 0),
SimpleBDXStore = (1 << 1),
Has20BitOffset = (1 << 2),
HasIndex = (1 << 3),
Is128Bit = (1 << 4),
AccessSizeMask = (31 << 5),
AccessSizeShift = 5,
CCValuesMask = (15 << 10),
CCValuesShift = 10,
CompareZeroCCMaskMask = (15 << 14),
CompareZeroCCMaskShift = 14,
CCMaskFirst = (1 << 18),
CCMaskLast = (1 << 19),
IsLogical = (1 << 20)
};
static inline unsigned getAccessSize(unsigned int Flags) {
return (Flags & AccessSizeMask) >> AccessSizeShift;
}
static inline unsigned getCCValues(unsigned int Flags) {
return (Flags & CCValuesMask) >> CCValuesShift;
}
static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
}
enum {
MO_SYMBOL_MODIFIER = (1 << 0),
MO_GOT = (1 << 0)
};
enum BranchType {
BranchNormal,
BranchC,
BranchCL,
BranchCG,
BranchCLG,
BranchCT,
BranchCTG
};
struct Branch {
BranchType Type;
unsigned CCValid;
unsigned CCMask;
const MachineOperand *Target;
Branch(BranchType type, unsigned ccValid, unsigned ccMask,
const MachineOperand *target)
: Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
};
}
class SystemZInstrInfo : public SystemZGenInstrInfo {
const SystemZRegisterInfo RI;
SystemZTargetMachine &TM;
void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
void expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
unsigned HighOpcode, bool ConvertHigh) const;
void expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
unsigned LowOpcodeK, unsigned HighOpcode) const;
void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
unsigned HighOpcode) const;
void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
unsigned Size) const;
void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
DebugLoc DL, unsigned DestReg, unsigned SrcReg,
unsigned LowLowOpcode, unsigned Size, bool KillSrc) const;
virtual void anchor();
public:
explicit SystemZInstrInfo(SystemZTargetMachine &TM);
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const LLVM_OVERRIDE;
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const LLVM_OVERRIDE;
virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
int &SrcFrameIndex) const LLVM_OVERRIDE;
virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const LLVM_OVERRIDE;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const LLVM_OVERRIDE;
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
unsigned &SrcReg2, int &Mask, int &Value) const
LLVM_OVERRIDE;
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
unsigned SrcReg2, int Mask, int Value,
const MachineRegisterInfo *MRI) const LLVM_OVERRIDE;
virtual bool isPredicable(MachineInstr *MI) const LLVM_OVERRIDE;
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
unsigned ExtraPredCycles,
const BranchProbability &Probability) const
LLVM_OVERRIDE;
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
unsigned NumCyclesT,
unsigned ExtraPredCyclesT,
MachineBasicBlock &FMBB,
unsigned NumCyclesF,
unsigned ExtraPredCyclesF,
const BranchProbability &Probability) const
LLVM_OVERRIDE;
virtual bool
PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const
LLVM_OVERRIDE;
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const LLVM_OVERRIDE;
virtual void
storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
virtual void
loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
virtual MachineInstr *
convertToThreeAddress(MachineFunction::iterator &MFI,
MachineBasicBlock::iterator &MBBI,
LiveVariables *LV) const;
virtual MachineInstr *
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
const SmallVectorImpl<unsigned> &Ops,
int FrameIndex) const;
virtual MachineInstr *
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
const SmallVectorImpl<unsigned> &Ops,
MachineInstr* LoadMI) const;
virtual bool
expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
virtual bool
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
LLVM_OVERRIDE;
const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
void getLoadStoreOpcodes(const TargetRegisterClass *RC,
unsigned &LoadOpcode, unsigned &StoreOpcode) const;
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
unsigned getLoadAndTest(unsigned Opcode) const;
bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
unsigned &Start, unsigned &End) const;
unsigned getCompareAndBranch(unsigned Opcode,
const MachineInstr *MI = 0) const;
void loadImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned Reg, uint64_t Value) const;
};
}
#endif