R600EmitClauseMarkers.cpp [plain text]
#include "AMDGPU.h"
#include "R600Defines.h"
#include "R600InstrInfo.h"
#include "R600MachineFunctionInfo.h"
#include "R600RegisterInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
using namespace llvm;
namespace llvm {
void initializeR600EmitClauseMarkersPass(PassRegistry&);
}
namespace {
class R600EmitClauseMarkers : public MachineFunctionPass {
private:
const R600InstrInfo *TII;
int Address;
unsigned OccupiedDwords(MachineInstr *MI) const {
switch (MI->getOpcode()) {
case AMDGPU::INTERP_PAIR_XY:
case AMDGPU::INTERP_PAIR_ZW:
case AMDGPU::INTERP_VEC_LOAD:
case AMDGPU::DOT_4:
return 4;
case AMDGPU::KILL:
return 0;
default:
break;
}
if (TII->isLDSRetInstr(MI->getOpcode()))
return 2;
if(TII->isVector(*MI) ||
TII->isCubeOp(MI->getOpcode()) ||
TII->isReductionOp(MI->getOpcode()))
return 4;
unsigned NumLiteral = 0;
for (MachineInstr::mop_iterator It = MI->operands_begin(),
E = MI->operands_end(); It != E; ++It) {
MachineOperand &MO = *It;
if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
++NumLiteral;
}
return 1 + NumLiteral;
}
bool isALU(const MachineInstr *MI) const {
if (TII->isALUInstr(MI->getOpcode()))
return true;
if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode()))
return true;
switch (MI->getOpcode()) {
case AMDGPU::PRED_X:
case AMDGPU::INTERP_PAIR_XY:
case AMDGPU::INTERP_PAIR_ZW:
case AMDGPU::INTERP_VEC_LOAD:
case AMDGPU::COPY:
case AMDGPU::DOT_4:
return true;
default:
return false;
}
}
bool IsTrivialInst(MachineInstr *MI) const {
switch (MI->getOpcode()) {
case AMDGPU::KILL:
case AMDGPU::RETURN:
case AMDGPU::IMPLICIT_DEF:
return true;
default:
return false;
}
}
std::pair<unsigned, unsigned> getAccessedBankLine(unsigned Sel) const {
return std::pair<unsigned, unsigned>(
((Sel >> 2) - 512) >> 12, ((((Sel >> 2) - 512) & 4095) >> 5) << 1);
}
bool SubstituteKCacheBank(MachineInstr *MI,
std::vector<std::pair<unsigned, unsigned> > &CachedConsts,
bool UpdateInstr = true) const {
std::vector<std::pair<unsigned, unsigned> > UsedKCache;
if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() != AMDGPU::DOT_4)
return true;
const SmallVectorImpl<std::pair<MachineOperand *, int64_t> > &Consts =
TII->getSrcs(MI);
assert((TII->isALUInstr(MI->getOpcode()) ||
MI->getOpcode() == AMDGPU::DOT_4) && "Can't assign Const");
for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
continue;
unsigned Sel = Consts[i].second;
unsigned Chan = Sel & 3, Index = ((Sel >> 2) - 512) & 31;
unsigned KCacheIndex = Index * 4 + Chan;
const std::pair<unsigned, unsigned> &BankLine = getAccessedBankLine(Sel);
if (CachedConsts.empty()) {
CachedConsts.push_back(BankLine);
UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
continue;
}
if (CachedConsts[0] == BankLine) {
UsedKCache.push_back(std::pair<unsigned, unsigned>(0, KCacheIndex));
continue;
}
if (CachedConsts.size() == 1) {
CachedConsts.push_back(BankLine);
UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
continue;
}
if (CachedConsts[1] == BankLine) {
UsedKCache.push_back(std::pair<unsigned, unsigned>(1, KCacheIndex));
continue;
}
return false;
}
if (!UpdateInstr)
return true;
for (unsigned i = 0, j = 0, n = Consts.size(); i < n; ++i) {
if (Consts[i].first->getReg() != AMDGPU::ALU_CONST)
continue;
switch(UsedKCache[j].first) {
case 0:
Consts[i].first->setReg(
AMDGPU::R600_KC0RegClass.getRegister(UsedKCache[j].second));
break;
case 1:
Consts[i].first->setReg(
AMDGPU::R600_KC1RegClass.getRegister(UsedKCache[j].second));
break;
default:
llvm_unreachable("Wrong Cache Line");
}
j++;
}
return true;
}
bool canClauseLocalKillFitInClause(
unsigned AluInstCount,
std::vector<std::pair<unsigned, unsigned> > KCacheBanks,
MachineBasicBlock::iterator Def,
MachineBasicBlock::iterator BBEnd) {
const R600RegisterInfo &TRI = TII->getRegisterInfo();
for (MachineInstr::const_mop_iterator
MOI = Def->operands_begin(),
MOE = Def->operands_end(); MOI != MOE; ++MOI) {
if (!MOI->isReg() || !MOI->isDef() ||
TRI.isPhysRegLiveAcrossClauses(MOI->getReg()))
continue;
unsigned LastUseCount = 0;
for (MachineBasicBlock::iterator UseI = Def; UseI != BBEnd; ++UseI) {
AluInstCount += OccupiedDwords(UseI);
if (!SubstituteKCacheBank(UseI, KCacheBanks, false))
return false;
if (AluInstCount >= TII->getMaxAlusPerClause())
return false;
if (UseI->findRegisterUseOperandIdx(MOI->getReg()))
LastUseCount = AluInstCount;
if (UseI != Def && UseI->findRegisterDefOperandIdx(MOI->getReg()) != -1)
break;
}
if (LastUseCount)
return LastUseCount <= TII->getMaxAlusPerClause();
llvm_unreachable("Clause local register live at end of clause.");
}
return true;
}
MachineBasicBlock::iterator
MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) {
MachineBasicBlock::iterator ClauseHead = I;
std::vector<std::pair<unsigned, unsigned> > KCacheBanks;
bool PushBeforeModifier = false;
unsigned AluInstCount = 0;
for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
if (IsTrivialInst(I))
continue;
if (!isALU(I))
break;
if (AluInstCount > TII->getMaxAlusPerClause())
break;
if (I->getOpcode() == AMDGPU::PRED_X) {
if (AluInstCount > 0)
break;
if (TII->getFlagOp(I).getImm() & MO_FLAG_PUSH)
PushBeforeModifier = true;
AluInstCount ++;
continue;
}
if (TII->mustBeLastInClause(I->getOpcode())) {
I++;
break;
}
if (!canClauseLocalKillFitInClause(AluInstCount, KCacheBanks, I, E))
break;
if (!SubstituteKCacheBank(I, KCacheBanks))
break;
AluInstCount += OccupiedDwords(I);
}
unsigned Opcode = PushBeforeModifier ?
AMDGPU::CF_ALU_PUSH_BEFORE : AMDGPU::CF_ALU;
BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
.addImm(Address++) .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) .addImm(KCacheBanks.empty()?0:2) .addImm((KCacheBanks.size() < 2)?0:2) .addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) .addImm(AluInstCount) .addImm(1); return I;
}
public:
static char ID;
R600EmitClauseMarkers() : MachineFunctionPass(ID), TII(0), Address(0) {
initializeR600EmitClauseMarkersPass(*PassRegistry::getPassRegistry());
}
virtual bool runOnMachineFunction(MachineFunction &MF) {
TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
MachineBasicBlock::iterator I = MBB.begin();
if (I->getOpcode() == AMDGPU::CF_ALU)
continue; for (MachineBasicBlock::iterator E = MBB.end(); I != E;) {
if (isALU(I))
I = MakeALUClause(MBB, I);
else
++I;
}
}
return false;
}
const char *getPassName() const {
return "R600 Emit Clause Markers Pass";
}
};
char R600EmitClauseMarkers::ID = 0;
}
INITIALIZE_PASS_BEGIN(R600EmitClauseMarkers, "emitclausemarkers",
"R600 Emit Clause Markters", false, false)
INITIALIZE_PASS_END(R600EmitClauseMarkers, "emitclausemarkers",
"R600 Emit Clause Markters", false, false)
llvm::FunctionPass *llvm::createR600EmitClauseMarkers() {
return new R600EmitClauseMarkers();
}