HexagonVLIWPacketizer.cpp [plain text]
#define DEBUG_TYPE "packets"
#include "llvm/CodeGen/DFAPacketizer.h"
#include "Hexagon.h"
#include "HexagonMachineFunctionInfo.h"
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "HexagonTargetMachine.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LatencyPriorityQueue.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <map>
#include <vector>
using namespace llvm;
static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
cl::ZeroOrMore, cl::Hidden, cl::init(true),
cl::desc("Allow non-solo packetization of volatile memory references"));
namespace llvm {
void initializeHexagonPacketizerPass(PassRegistry&);
}
namespace {
class HexagonPacketizer : public MachineFunctionPass {
public:
static char ID;
HexagonPacketizer() : MachineFunctionPass(ID) {
initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry());
}
void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTree>();
AU.addRequired<MachineBranchProbabilityInfo>();
AU.addPreserved<MachineDominatorTree>();
AU.addRequired<MachineLoopInfo>();
AU.addPreserved<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU);
}
const char *getPassName() const {
return "Hexagon Packetizer";
}
bool runOnMachineFunction(MachineFunction &Fn);
};
char HexagonPacketizer::ID = 0;
class HexagonPacketizerList : public VLIWPacketizerList {
private:
bool PromotedToDotNew;
bool GlueAllocframeStore;
bool GlueToNewValueJump;
bool Dependence;
bool FoundSequentialDependence;
const MachineBranchProbabilityInfo *MBPI;
std::vector<MachineInstr*> IgnoreDepMIs;
public:
HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
MachineDominatorTree &MDT,
const MachineBranchProbabilityInfo *MBPI);
void initPacketizerState();
bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
bool isSoloInstruction(MachineInstr *MI);
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
private:
bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC);
bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
unsigned DepReg,
std::map <MachineInstr*, SUnit*> MIToSUnit,
MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC);
bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
unsigned DepReg,
std::map <MachineInstr*, SUnit*> MIToSUnit,
MachineBasicBlock::iterator &MII);
bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
unsigned DepReg,
std::map <MachineInstr*, SUnit*> MIToSUnit);
bool DemoteToDotOld(MachineInstr* MI);
bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
std::map <MachineInstr*, SUnit*> MIToSUnit);
bool RestrictingDepExistInPacket(MachineInstr*,
unsigned, std::map <MachineInstr*, SUnit*>);
bool isNewifiable(MachineInstr* MI);
bool isCondInst(MachineInstr* MI);
bool tryAllocateResourcesForConstExt(MachineInstr* MI);
bool canReserveResourcesForConstExt(MachineInstr *MI);
void reserveResourcesForConstExt(MachineInstr* MI);
bool isNewValueInst(MachineInstr* MI);
};
}
INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
false, false)
HexagonPacketizerList::HexagonPacketizerList(
MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT,
const MachineBranchProbabilityInfo *MBPI)
: VLIWPacketizerList(MF, MLI, MDT, true){
this->MBPI = MBPI;
}
bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
const MachineBranchProbabilityInfo *MBPI =
&getAnalysis<MachineBranchProbabilityInfo>();
HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI);
assert(Packetizer.getResourceTracker() && "Empty DFA table!");
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB) {
MachineBasicBlock::iterator End = MBB->end();
MachineBasicBlock::iterator MI = MBB->begin();
while (MI != End) {
if (MI->isKill()) {
MachineBasicBlock::iterator DeleteMI = MI;
++MI;
MBB->erase(DeleteMI);
End = MBB->end();
continue;
}
++MI;
}
}
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB) {
unsigned RemainingCount = MBB->size();
for(MachineBasicBlock::iterator RegionEnd = MBB->end();
RegionEnd != MBB->begin();) {
MachineBasicBlock::iterator I = RegionEnd;
for(;I != MBB->begin(); --I, --RemainingCount) {
if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
break;
}
I = MBB->begin();
if (I == RegionEnd) {
RegionEnd = llvm::prior(RegionEnd);
--RemainingCount;
continue;
}
if (I == llvm::prior(RegionEnd)) {
RegionEnd = llvm::prior(RegionEnd);
continue;
}
Packetizer.PacketizeMIs(MBB, I, RegionEnd);
RegionEnd = I;
}
}
return true;
}
static bool IsIndirectCall(MachineInstr* MI) {
return ((MI->getOpcode() == Hexagon::CALLR) ||
(MI->getOpcode() == Hexagon::CALLRv3));
}
void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
MachineFunction *MF = MI->getParent()->getParent();
MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
MI->getDebugLoc());
if (ResourceTracker->canReserveResources(PseudoMI)) {
ResourceTracker->reserveResources(PseudoMI);
MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
} else {
MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
llvm_unreachable("can not reserve resources for constant extender.");
}
return;
}
bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
"Should only be called for constant extended instructions");
MachineFunction *MF = MI->getParent()->getParent();
MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
MI->getDebugLoc());
bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
MF->DeleteMachineInstr(PseudoMI);
return CanReserve;
}
bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
MachineFunction *MF = MI->getParent()->getParent();
MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
MI->getDebugLoc());
if (ResourceTracker->canReserveResources(PseudoMI)) {
ResourceTracker->reserveResources(PseudoMI);
MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
return true;
} else {
MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
return false;
}
}
bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
SDep::Kind DepType,
unsigned DepReg) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
const HexagonRegisterInfo* QRI =
(const HexagonRegisterInfo *) TM.getRegisterInfo();
if (DepReg == QRI->getRARegister()) {
return true;
}
if (QII->isDeallocRet(MI)) {
if (DepReg == QRI->getFrameRegister() ||
DepReg == QRI->getStackRegister())
return true;
}
const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
if (RC == &Hexagon::PredRegsRegClass) {
return true;
}
if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
MachineOperand MO = MI->getOperand(0);
if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
return true;
}
}
return false;
}
static bool IsRegDependence(const SDep::Kind DepType) {
return (DepType == SDep::Data || DepType == SDep::Anti ||
DepType == SDep::Output);
}
static bool IsDirectJump(MachineInstr* MI) {
return (MI->getOpcode() == Hexagon::JMP);
}
static bool IsSchedBarrier(MachineInstr* MI) {
switch (MI->getOpcode()) {
case Hexagon::BARRIER:
return true;
}
return false;
}
static bool IsControlFlow(MachineInstr* MI) {
return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
}
static bool IsLoopN(MachineInstr *MI) {
return (MI->getOpcode() == Hexagon::LOOP0_i ||
MI->getOpcode() == Hexagon::LOOP0_r);
}
static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
const TargetRegisterInfo *TRI) {
for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
unsigned CalleeSavedReg = *CSR;
if (MI->modifiesRegister(CalleeSavedReg, TRI))
return true;
}
return false;
}
bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
if ( isCondInst(MI) || QII->mayBeNewStore(MI))
return true;
else
return false;
}
bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
const MCInstrDesc& TID = MI->getDesc();
if ( TID.isConditionalBranch() || QII->isConditionalTransfer(MI)
|| QII->isConditionalALU32(MI)
|| QII->isConditionalLoad(MI)
|| QII->isConditionalStore(MI)) {
return true;
}
return false;
}
bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
SDep::Kind DepType, MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC) {
assert (DepType == SDep::Data);
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
int NewOpcode;
if (RC == &Hexagon::PredRegsRegClass)
NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
else
NewOpcode = QII->GetDotNewOp(MI);
MI->setDesc(QII->get(NewOpcode));
return true;
}
bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
int NewOpcode = QII->GetDotOldOp(MI->getOpcode());
MI->setDesc(QII->get(NewOpcode));
return true;
}
enum PredicateKind {
PK_False,
PK_True,
PK_Unknown
};
static PredicateKind getPredicateSense(MachineInstr* MI,
const HexagonInstrInfo *QII) {
if (!QII->isPredicated(MI))
return PK_Unknown;
if (QII->isPredicatedTrue(MI))
return PK_True;
return PK_False;
}
static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
const HexagonInstrInfo *QII) {
assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
#ifndef NDEBUG
DenseMap<unsigned, unsigned> DefRegsSet;
for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
if (MI->getOperand(opNum).isReg() &&
MI->getOperand(opNum).isDef()) {
DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
}
for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
if (MI->getOperand(opNum).isReg() &&
MI->getOperand(opNum).isUse()) {
if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
return MI->getOperand(opNum);
}
}
#else
if (MI->getDesc().mayLoad()) {
assert(MI->getOperand(1).isReg() &&
"Post increment operand has be to a register.");
return (MI->getOperand(1));
}
if (MI->getDesc().mayStore()) {
assert(MI->getOperand(0).isReg() &&
"Post increment operand has be to a register.");
return (MI->getOperand(0));
}
#endif
llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
}
static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
return (MI->getOperand(MI->getNumOperands()-1));
}
bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
MachineInstr *PacketMI, unsigned DepReg,
std::map <MachineInstr*, SUnit*> MIToSUnit) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
if (!QII->mayBeNewStore(MI))
return false;
if (GetStoreValueOperand(MI).isReg() &&
GetStoreValueOperand(MI).getReg() != DepReg)
return false;
const HexagonRegisterInfo* QRI =
(const HexagonRegisterInfo *) TM.getRegisterInfo();
const MCInstrDesc& MCID = PacketMI->getDesc();
const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
VE = CurrentPacketMIs.end();
(VI != VE); ++VI) {
SUnit* PacketSU = MIToSUnit[*VI];
if (PacketSU->getInstr()->getDesc().mayStore() ||
PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
return false;
}
if (PacketRC == &Hexagon::DoubleRegsRegClass) {
return false;
}
if (QII->isPostIncrement(MI) &&
MI->getDesc().mayStore() &&
GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
return false;
}
if (QII->isPostIncrement(PacketMI) &&
PacketMI->getDesc().mayLoad() &&
GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
return false;
}
if (QII->isPredicated(PacketMI)) {
if (!QII->isPredicated(MI))
return false;
unsigned predRegNumSrc = 0;
unsigned predRegNumDst = 0;
const TargetRegisterClass* predRegClass = NULL;
for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
if ( PacketMI->getOperand(opNum).isReg())
predRegNumSrc = PacketMI->getOperand(opNum).getReg();
predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
if (predRegClass == &Hexagon::PredRegsRegClass) {
break;
}
}
assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
("predicate register not found in a predicated PacketMI instruction"));
for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
if ( MI->getOperand(opNum).isReg())
predRegNumDst = MI->getOperand(opNum).getReg();
predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
if (predRegClass == &Hexagon::PredRegsRegClass) {
break;
}
}
assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
("predicate register not found in a predicated MI instruction"));
if (( predRegNumDst != predRegNumSrc) ||
QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI) ||
getPredicateSense(MI, QII) != getPredicateSense(PacketMI, QII)) {
return false;
}
}
std::vector<MachineInstr*>::iterator VI;
std::vector<MachineInstr*>::iterator VE;
unsigned StartCheck = 0;
for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
(VI != VE); ++VI) {
SUnit* TempSU = MIToSUnit[*VI];
MachineInstr* TempMI = TempSU->getInstr();
if (TempMI != PacketMI && !StartCheck) continue;
StartCheck = 1;
if (TempMI == PacketMI) continue;
for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
if (MI->getOperand(opNum).isReg() &&
TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
QRI))
return false;
}
}
if (!QII->isPostIncrement(MI) &&
GetStoreValueOperand(MI).isReg() &&
GetStoreValueOperand(MI).getReg() == DepReg) {
for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
if (MI->getOperand(opNum).isReg() &&
MI->getOperand(opNum).getReg() == DepReg) {
return false;
}
}
for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
if (PacketMI->getOperand(opNum).isReg() &&
PacketMI->getOperand(opNum).getReg() == DepReg &&
PacketMI->getOperand(opNum).isDef() &&
PacketMI->getOperand(opNum).isImplicit()) {
return false;
}
}
}
return true;
}
bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
SUnit *PacketSU, unsigned DepReg,
std::map <MachineInstr*, SUnit*> MIToSUnit,
MachineBasicBlock::iterator &MII)
{
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
const HexagonRegisterInfo* QRI =
(const HexagonRegisterInfo *) TM.getRegisterInfo();
if (!QRI->Subtarget.hasV4TOps() ||
!QII->mayBeNewStore(MI))
return false;
MachineInstr *PacketMI = PacketSU->getInstr();
if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
return true;
return false;
}
bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
SUnit *PacketSU, unsigned DepReg,
std::map <MachineInstr*, SUnit*> MIToSUnit,
MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC )
{
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
if (QII->isDotNewInst(MI) && !QII->mayBeNewStore(MI))
return false;
if (!isNewifiable(MI))
return false;
if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
return true;
else if (RC != &Hexagon::PredRegsRegClass &&
!QII->mayBeNewStore(MI)) return false;
else {
int NewOpcode = QII->GetDotNewOp(MI);
const MCInstrDesc &desc = QII->get(NewOpcode);
DebugLoc dl;
MachineInstr *NewMI =
MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
if (!ResourcesAvailable)
return false;
if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
return false;
}
}
return true;
}
bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
unsigned DepReg,
std::map <MachineInstr*, SUnit*> MIToSUnit) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
SUnit* PacketSUDep = MIToSUnit[MI];
for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
if(!QII->isPredicated(*VIN)) continue;
SUnit* PacketSU = MIToSUnit[*VIN];
if (PacketSU->isSucc(PacketSUDep)) {
for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
(PacketSU->Succs[i].getKind() == SDep::Anti) &&
(PacketSU->Succs[i].getReg() == DepReg)) {
return true;
}
}
}
}
return false;
}
static unsigned getPredicatedRegister(MachineInstr *MI,
const HexagonInstrInfo *QII) {
assert(QII->isPredicated(MI) && "Must be predicated instruction");
for (MachineInstr::mop_iterator OI = MI->operands_begin(),
OE = MI->operands_end(); OI != OE; ++OI) {
MachineOperand &Op = *OI;
if (Op.isReg() && Op.getReg() && Op.isUse() &&
Hexagon::PredRegsRegClass.contains(Op.getReg()))
return Op.getReg();
}
llvm_unreachable("Unknown instruction operand layout");
return 0;
}
bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
if (getPredicateSense(MI1, QII) == PK_Unknown ||
getPredicateSense(MI2, QII) == PK_Unknown)
return false;
SUnit* SU = MIToSUnit[MI1];
for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
SUnit* PacketSU = MIToSUnit[*VIN];
if (PacketSU->isSucc(SU)) {
for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
if (PacketSU->Succs[i].getSUnit() == SU &&
PacketSU->Succs[i].getKind() == SDep::Data &&
Hexagon::PredRegsRegClass.contains(
PacketSU->Succs[i].getReg()) &&
RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
MIToSUnit)) {
return false;
}
}
}
}
unsigned PReg1 = getPredicatedRegister(MI1, QII);
unsigned PReg2 = getPredicatedRegister(MI2, QII);
return ((PReg1 == PReg2) &&
Hexagon::PredRegsRegClass.contains(PReg1) &&
Hexagon::PredRegsRegClass.contains(PReg2) &&
(getPredicateSense(MI1, QII) != getPredicateSense(MI2, QII)) &&
(QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
}
void HexagonPacketizerList::initPacketizerState() {
Dependence = false;
PromotedToDotNew = false;
GlueToNewValueJump = false;
GlueAllocframeStore = false;
FoundSequentialDependence = false;
return;
}
bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
MachineBasicBlock *MBB) {
if (MI->isDebugValue())
return true;
if (MI->isInlineAsm())
return false;
const MCInstrDesc& TID = MI->getDesc();
unsigned SchedClass = TID.getSchedClass();
const InstrStage* IS =
ResourceTracker->getInstrItins()->beginStage(SchedClass);
unsigned FuncUnits = IS->getUnits();
return !FuncUnits;
}
bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
if (MI->isInlineAsm())
return true;
if (MI->isEHLabel())
return true;
if (IsSchedBarrier(MI))
return true;
return false;
}
bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
MachineInstr *I = SUI->getInstr();
MachineInstr *J = SUJ->getInstr();
assert(I && J && "Unable to packetize null instruction!");
const MCInstrDesc &MCIDI = I->getDesc();
const MCInstrDesc &MCIDJ = J->getDesc();
MachineBasicBlock::iterator II = I;
const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
const HexagonRegisterInfo* QRI =
(const HexagonRegisterInfo *) TM.getRegisterInfo();
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
if (I->getOpcode() == Hexagon::INLINEASM)
llvm_unreachable("Should not meet inline asm here!");
if (isSoloInstruction(I))
llvm_unreachable("Should not meet solo instr here!");
if ((QII->isSaveCalleeSavedRegsCall(I) &&
DoesModifyCalleeSavedReg(J, QRI)) ||
(QII->isSaveCalleeSavedRegsCall(J) &&
DoesModifyCalleeSavedReg(I, QRI))) {
Dependence = true;
return false;
}
if (IsControlFlow(I) && IsControlFlow(J)) {
Dependence = true;
return false;
}
if (IsLoopN(I) &&
(IsDirectJump(J) || MCIDJ.isCall() || QII->isDeallocRet(J))) {
Dependence = true;
return false;
}
if (IsLoopN(J) &&
(IsDirectJump(I) || MCIDI.isCall() || QII->isDeallocRet(I))) {
Dependence = true;
return false;
}
if (QII->isDeallocRet(I) &&
(MCIDJ.isBranch() || MCIDJ.isCall() || MCIDJ.isBarrier())) {
Dependence = true;
return false;
}
if (QRI->Subtarget.hasV4TOps()) {
if (MCIDI.mayStore() && MCIDJ.mayStore() &&
(QII->isNewValueInst(J) || QII->isMemOp(J) || QII->isMemOp(I))) {
Dependence = true;
return false;
}
if ((QII->isMemOp(J) && MCIDI.mayStore())
|| (MCIDJ.mayStore() && QII->isMemOp(I))
|| (QII->isMemOp(J) && QII->isMemOp(I))) {
Dependence = true;
return false;
}
if (MCIDJ.mayStore() && QII->isDeallocRet(I)) {
Dependence = true;
return false;
}
MachineBasicBlock::iterator NextMII = I;
++NextMII;
if (NextMII != I->getParent()->end() && QII->isNewValueJump(NextMII)) {
MachineInstr *NextMI = NextMII;
bool secondRegMatch = false;
bool maintainNewValueJump = false;
if (NextMI->getOperand(1).isReg() &&
I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
secondRegMatch = true;
maintainNewValueJump = true;
}
if (!secondRegMatch &&
I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
maintainNewValueJump = true;
}
for (std::vector<MachineInstr*>::iterator
VI = CurrentPacketMIs.begin(),
VE = CurrentPacketMIs.end();
(VI != VE && maintainNewValueJump); ++VI) {
SUnit* PacketSU = MIToSUnit[*VI];
if (PacketSU->getInstr()->getDesc().isCall()) {
Dependence = true;
break;
}
if (PacketSU->getInstr()->getDesc().mayStore() ||
PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
(!secondRegMatch && NextMI->getOperand(1).isReg() &&
PacketSU->getInstr()->modifiesRegister(
NextMI->getOperand(1).getReg(), QRI)) ||
(secondRegMatch &&
PacketSU->getInstr()->modifiesRegister(
NextMI->getOperand(0).getReg(), QRI))) {
Dependence = true;
break;
}
}
if (!Dependence)
GlueToNewValueJump = true;
else
return false;
}
}
if (SUJ->isSucc(SUI)) {
for (unsigned i = 0;
(i < SUJ->Succs.size()) && !FoundSequentialDependence;
++i) {
if (SUJ->Succs[i].getSUnit() != SUI) {
continue;
}
SDep::Kind DepType = SUJ->Succs[i].getKind();
unsigned DepReg = 0;
const TargetRegisterClass* RC = NULL;
if (DepType == SDep::Data) {
DepReg = SUJ->Succs[i].getReg();
RC = QRI->getMinimalPhysRegClass(DepReg);
}
if ((MCIDI.isCall() || MCIDI.isReturn()) &&
(!IsRegDependence(DepType) ||
!IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
}
else if ((DepType == SDep::Data) &&
CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
PromoteToDotNew(I, DepType, II, RC)) {
PromotedToDotNew = true;
}
else if ((DepType == SDep::Data) &&
(QII->isNewValueJump(I))) {
}
else if (QII->isPredicated(I) &&
QII->isPredicated(J) &&
ArePredicatesComplements(I, J, MIToSUnit)) {
}
else if (IsDirectJump(I) &&
!MCIDJ.isBranch() &&
!MCIDJ.isCall() &&
(DepType == SDep::Order)) {
}
else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
(DepType != SDep::Output)) {
}
else if (DepType == SDep::Output) {
unsigned DepReg = SUJ->Succs[i].getReg();
if (I->definesRegister(DepReg) ||
J->definesRegister(DepReg)) {
FoundSequentialDependence = true;
break;
}
}
else if ((DepType == SDep::Order) &&
!I->hasOrderedMemoryRef() &&
!J->hasOrderedMemoryRef()) {
if (QRI->Subtarget.hasV4TOps() &&
MCIDI.mayStore() && MCIDJ.mayStore()) {
}
else if ( !MCIDJ.mayStore()) {
}
else {
FoundSequentialDependence = true;
break;
}
}
else if (DepType == SDep::Data
&& QRI->Subtarget.hasV4TOps()
&& J->getOpcode() == Hexagon::ALLOCFRAME
&& (I->getOpcode() == Hexagon::STrid
|| I->getOpcode() == Hexagon::STriw
|| I->getOpcode() == Hexagon::STrib)
&& I->getOperand(0).getReg() == QRI->getStackRegister()
&& QII->isValidOffset(I->getOpcode(),
I->getOperand(1).getImm() -
(FrameSize + HEXAGON_LRFP_SIZE)))
{
GlueAllocframeStore = true;
I->getOperand(1).setImm(I->getOperand(1).getImm() -
(FrameSize + HEXAGON_LRFP_SIZE));
}
else if (DepType != SDep::Anti) {
FoundSequentialDependence = true;
break;
}
}
if (FoundSequentialDependence) {
Dependence = true;
return false;
}
}
return true;
}
bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
MachineInstr *I = SUI->getInstr();
assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
if (Dependence) {
if (PromotedToDotNew) {
DemoteToDotOld(I);
}
if (GlueAllocframeStore) {
I->getOperand(1).setImm(I->getOperand(1).getImm() +
FrameSize + HEXAGON_LRFP_SIZE);
}
return false;
}
return true;
}
MachineBasicBlock::iterator
HexagonPacketizerList::addToPacket(MachineInstr *MI) {
MachineBasicBlock::iterator MII = MI;
MachineBasicBlock *MBB = MI->getParent();
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
if (GlueToNewValueJump) {
++MII;
MachineInstr *nvjMI = MII;
assert(ResourceTracker->canReserveResources(MI));
ResourceTracker->reserveResources(MI);
if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
!tryAllocateResourcesForConstExt(MI)) {
endPacket(MBB, MI);
ResourceTracker->reserveResources(MI);
assert(canReserveResourcesForConstExt(MI) &&
"Ensure that there is a slot");
reserveResourcesForConstExt(MI);
assert(canReserveResourcesForConstExt(MI) &&
"Ensure that there is a slot");
reserveResourcesForConstExt(nvjMI);
assert(ResourceTracker->canReserveResources(nvjMI) &&
"Ensure that there is a slot");
} else if ( (QII->isExtended(nvjMI)
&& (!tryAllocateResourcesForConstExt(nvjMI)
|| !ResourceTracker->canReserveResources(nvjMI)))
|| (!QII->isExtended(nvjMI) &&
!ResourceTracker->canReserveResources(nvjMI)))
{
endPacket(MBB, MI);
ResourceTracker->reserveResources(MI);
if (QII->isExtended(nvjMI))
reserveResourcesForConstExt(nvjMI);
}
ResourceTracker->reserveResources(nvjMI);
CurrentPacketMIs.push_back(MI);
CurrentPacketMIs.push_back(nvjMI);
} else {
if ( (QII->isExtended(MI) || QII->isConstExtended(MI))
&& ( !tryAllocateResourcesForConstExt(MI)
|| !ResourceTracker->canReserveResources(MI)))
{
endPacket(MBB, MI);
if (PromotedToDotNew) {
DemoteToDotOld(MI);
}
reserveResourcesForConstExt(MI);
}
ResourceTracker->reserveResources(MI);
CurrentPacketMIs.push_back(MI);
}
return MII;
}
FunctionPass *llvm::createHexagonPacketizer() {
return new HexagonPacketizer();
}