ARM64Subtarget.cpp [plain text]
#include "ARM64InstrInfo.h"
#include "ARM64Subtarget.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/Support/TargetRegistry.h"
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_TARGET_DESC
#include "ARM64GenSubtargetInfo.inc"
using namespace llvm;
static cl::opt<bool>
UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
"an address is ignored"), cl::init(false), cl::Hidden);
ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS)
: ARM64GenSubtargetInfo(TT, CPU, FS),
HasZeroCycleRegMove(false),
HasZeroCycleZeroing(false),
HasAddressTopByteIgnored(false),
CPUString(CPU),
TargetTriple(TT) {
if (CPUString.empty())
CPUString = "cyclone";
ParseSubtargetFeatures(CPUString, FS);
}
unsigned char
ARM64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
const TargetMachine &TM) const {
bool isDecl = GV->hasAvailableExternallyLinkage();
if (GV->isDeclaration() && !GV->isMaterializable())
isDecl = true;
if (TM.getRelocationModel() != Reloc::Static && GV->hasDefaultVisibility() &&
(isDecl || GV->isWeakForLinker()))
return ARM64II::MO_GOT;
if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
return ARM64II::MO_GOT;
return ARM64II::MO_NO_FLAG;
}
const char *ARM64Subtarget::getBZeroEntry() const {
return "bzero";
}
void ARM64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
MachineInstr *begin,
MachineInstr *end,
unsigned NumRegionInstrs) const {
Policy.OnlyTopDown = false;
Policy.OnlyBottomUp = false;
}
bool ARM64Subtarget::supportsAddressTopByteIgnored() const {
if (!HasAddressTopByteIgnored || !UseAddressTopByteIgnored)
return false;
if (TargetTriple.isiOS()) {
unsigned Major, Minor, Micro;
TargetTriple.getiOSVersion(Major, Minor, Micro);
return Major >= 8;
}
return false;
}