ARM64AsmPrinter.cpp [plain text]
#define DEBUG_TYPE "asm-printer"
#include "ARM64.h"
#include "ARM64MachineFunctionInfo.h"
#include "ARM64MCInstLower.h"
#include "ARM64RegisterInfo.h"
#include "InstPrinter/ARM64InstPrinter.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/DebugInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/MCLinkerOptimizationHint.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
namespace {
class ARM64AsmPrinter : public AsmPrinter {
ARM64MCInstLower MCInstLowering;
StackMaps SM;
public:
ARM64AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
: AsmPrinter(TM, Streamer), MCInstLowering(OutContext, *Mang, *this),
SM(*this), ARM64FI(NULL), LOHLabelCounter(0) {}
virtual const char *getPassName() const {
return "ARM64 Assembly Printer";
}
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
return MCInstLowering.lowerOperand(MO, MCOp);
}
bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
const MachineInstr *MI);
void EmitInstruction(const MachineInstr *MI);
void getAnalysisUsage(AnalysisUsage &AU) const {
AsmPrinter::getAnalysisUsage(AU);
AU.setPreservesAll();
}
bool runOnMachineFunction(MachineFunction &F) {
ARM64FI = F.getInfo<ARM64FunctionInfo>();
return AsmPrinter::runOnMachineFunction(F);
}
private:
MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
bool printAsmRegInClass(const MachineOperand &MO,
const TargetRegisterClass *RC,
bool isVector, raw_ostream &O);
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant,
const char *ExtraCode, raw_ostream &O);
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant,
const char *ExtraCode, raw_ostream &O);
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
void EmitFunctionBodyEnd();
MCSymbol *GetCPISymbol(unsigned CPID) const;
void EmitEndOfAsmFile(Module &M);
ARM64FunctionInfo *ARM64FI;
void EmitLOHs();
typedef std::map<const MachineInstr *, MCSymbol *> MInstToMCSymbol;
MInstToMCSymbol LOHInstToLabel;
unsigned LOHLabelCounter;
};
}
void ARM64AsmPrinter::EmitEndOfAsmFile(Module &M) {
OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
SM.serializeToStackMapSection();
}
MachineLocation ARM64AsmPrinter::
getDebugValueLocation(const MachineInstr *MI) const {
MachineLocation Location;
assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
else {
DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
}
return Location;
}
void ARM64AsmPrinter::EmitLOHs() {
const ARM64FunctionInfo::MILOHDirectives &LOHs =
const_cast<const ARM64FunctionInfo *>(ARM64FI)->getLOHContainer().
getDirectives();
SmallVector<MCSymbol *, 3> MCArgs;
for (ARM64FunctionInfo::MILOHDirectives::const_iterator It = LOHs.begin(),
EndIt = LOHs.end(); It != EndIt; ++It) {
const ARM64FunctionInfo::MILOHArgs &MIArgs = It->getArgs();
for (ARM64FunctionInfo::MILOHArgs::const_iterator MIArgsIt = MIArgs.begin(),
EndMIArgsIt = MIArgs.end(); MIArgsIt != EndMIArgsIt; ++MIArgsIt) {
MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(*MIArgsIt);
assert(LabelIt != LOHInstToLabel.end() &&
"Label hasn't been inserted for LOH related instruction");
MCArgs.push_back(LabelIt->second);
}
OutStreamer.EmitLOHDirective(It->getKind(), MCArgs);
MCArgs.clear();
}
}
void ARM64AsmPrinter::EmitFunctionBodyEnd() {
if (!ARM64FI->getLOHRelated().empty())
EmitLOHs();
}
MCSymbol *ARM64AsmPrinter::GetCPISymbol(unsigned CPID) const {
if (getDataLayout().getLinkerPrivateGlobalPrefix()[0])
return OutContext.GetOrCreateSymbol
(Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
Twine(getFunctionNumber()) + "_" + Twine(CPID));
return OutContext.GetOrCreateSymbol
(Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" +
Twine(getFunctionNumber()) + "_" + Twine(CPID));
}
void ARM64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNum);
switch (MO.getType()) {
default:
assert(0 && "<unknown operand type>");
case MachineOperand::MO_Register: {
unsigned Reg = MO.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
assert(!MO.getSubReg() && "Subregs should be eliminated!");
O << ARM64InstPrinter::getRegisterName(Reg);
break;
}
case MachineOperand::MO_Immediate: {
int64_t Imm = MO.getImm();
O << '#' << Imm;
break;
}
}
}
bool ARM64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
raw_ostream &O) {
unsigned Reg = MO.getReg();
switch (Mode) {
default: return true; case 'w':
Reg = getWRegFromXReg(Reg);
break;
case 'x':
Reg = getXRegFromWReg(Reg);
break;
}
O << ARM64InstPrinter::getRegisterName(Reg);
return false;
}
bool ARM64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
const TargetRegisterClass *RC,
bool isVector,
raw_ostream &O) {
assert(MO.isReg() && "Should only get here with a register!");
const ARM64RegisterInfo *RI =
static_cast<const ARM64RegisterInfo*>(TM.getRegisterInfo());
unsigned Reg = MO.getReg();
unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
assert(RI->regsOverlap(RegToPrint, Reg));
O << ARM64InstPrinter::getRegisterName(RegToPrint, isVector ? ARM64::vreg :
ARM64::NoRegAltName);
return false;
}
bool ARM64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant,
const char *ExtraCode, raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNum);
if (ExtraCode && ExtraCode[0]) {
if (ExtraCode[1] != 0) return true;
switch (ExtraCode[0]) {
default: return true; case 'w': case 'x': if (MO.isReg())
return printAsmMRegister(MO, ExtraCode[0], O);
if (MO.isImm() && MO.getImm() == 0) {
unsigned Reg = ExtraCode[0] == 'w' ? ARM64::WZR :
ARM64::XZR;
O << ARM64InstPrinter::getRegisterName(Reg);
return false;
}
printOperand(MI, OpNum, O);
return false;
case 'b': case 'h': case 's': case 'd': case 'q': if (MO.isReg()) {
const TargetRegisterClass *RC;
switch (ExtraCode[0]) {
case 'b': RC = &ARM64::FPR8RegClass; break;
case 'h': RC = &ARM64::FPR16RegClass; break;
case 's': RC = &ARM64::FPR32RegClass; break;
case 'd': RC = &ARM64::FPR64RegClass; break;
case 'q': RC = &ARM64::FPR128RegClass; break;
default: return true;
}
return printAsmRegInClass(MO, RC, false , O);
}
printOperand(MI, OpNum, O);
return false;
}
}
if (MO.isReg()) {
unsigned Reg = MO.getReg();
if (ARM64::GPR32allRegClass.contains(Reg) ||
ARM64::GPR64allRegClass.contains(Reg))
return printAsmMRegister(MO, 'x', O);
return printAsmRegInClass(MO, &ARM64::FPR128RegClass, true , O);
}
printOperand(MI, OpNum, O);
return false;
}
bool ARM64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
unsigned OpNum, unsigned AsmVariant,
const char *ExtraCode,
raw_ostream &O) {
if (ExtraCode && ExtraCode[0])
return true;
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isReg() && "unexpected inline asm memory operand");
O << "[" << ARM64InstPrinter::getRegisterName(MO.getReg()) << "]";
return false;
}
void ARM64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
raw_ostream &OS) {
unsigned NOps = MI->getNumOperands();
assert(NOps==4);
OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
OS << V.getName();
OS << " <- ";
assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
OS << ']';
OS << "+";
printOperand(MI, NOps-2, OS);
}
static void LowerSTACKMAP(MCStreamer &OutStreamer,
StackMaps &SM,
const MachineInstr &MI)
{
unsigned NumNOPBytes = MI.getOperand(1).getImm();
SM.recordStackMap(MI);
assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
for (unsigned i = 0; i < NumNOPBytes; i += 4)
OutStreamer.EmitInstruction(MCInstBuilder(ARM64::HINT).addImm(0));
}
static void LowerPATCHPOINT(MCStreamer &OutStreamer,
StackMaps &SM,
const MachineInstr &MI) {
SM.recordPatchPoint(MI);
PatchPointOpers Opers(&MI);
int64_t CallTarget = Opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
unsigned EncodedBytes = 0;
if (CallTarget) {
assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
"High 16 bits of call target should be zero.");
unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
EncodedBytes = 16;
OutStreamer.EmitInstruction(MCInstBuilder(ARM64::MOVZWi)
.addReg(ScratchReg)
.addImm((CallTarget >> 32) & 0xFFFF)
.addImm(32));
OutStreamer.EmitInstruction(MCInstBuilder(ARM64::MOVKWi)
.addReg(ScratchReg)
.addReg(ScratchReg)
.addImm((CallTarget >> 16) & 0xFFFF)
.addImm(16));
OutStreamer.EmitInstruction(MCInstBuilder(ARM64::MOVKWi)
.addReg(ScratchReg)
.addReg(ScratchReg)
.addImm(CallTarget & 0xFFFF)
.addImm(0));
OutStreamer.EmitInstruction(MCInstBuilder(ARM64::BLR)
.addReg(ScratchReg));
}
unsigned NumBytes = Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
assert(NumBytes >= EncodedBytes &&
"Patchpoint can't request size less than the length of a call.");
assert((NumBytes - EncodedBytes) % 4 == 0 &&
"Invalid number of NOP bytes requested!");
for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
OutStreamer.EmitInstruction(MCInstBuilder(ARM64::HINT).addImm(0));
}
#include "ARM64GenMCPseudoLowering.inc"
static unsigned getRealIndexedOpcode(unsigned Opc) {
switch (Opc) {
case ARM64::LDRXpre_isel: return ARM64::LDRXpre;
case ARM64::LDRWpre_isel: return ARM64::LDRWpre;
case ARM64::LDRDpre_isel: return ARM64::LDRDpre;
case ARM64::LDRSpre_isel: return ARM64::LDRSpre;
case ARM64::LDRBBpre_isel: return ARM64::LDRBBpre;
case ARM64::LDRHHpre_isel: return ARM64::LDRHHpre;
case ARM64::LDRSBWpre_isel: return ARM64::LDRSBWpre;
case ARM64::LDRSBXpre_isel: return ARM64::LDRSBXpre;
case ARM64::LDRSHWpre_isel: return ARM64::LDRSHWpre;
case ARM64::LDRSHXpre_isel: return ARM64::LDRSHXpre;
case ARM64::LDRSWpre_isel: return ARM64::LDRSWpre;
case ARM64::LDRDpost_isel: return ARM64::LDRDpost;
case ARM64::LDRSpost_isel: return ARM64::LDRSpost;
case ARM64::LDRXpost_isel: return ARM64::LDRXpost;
case ARM64::LDRWpost_isel: return ARM64::LDRWpost;
case ARM64::LDRHHpost_isel: return ARM64::LDRHHpost;
case ARM64::LDRBBpost_isel: return ARM64::LDRBBpost;
case ARM64::LDRSWpost_isel: return ARM64::LDRSWpost;
case ARM64::LDRSHWpost_isel: return ARM64::LDRSHWpost;
case ARM64::LDRSHXpost_isel: return ARM64::LDRSHXpost;
case ARM64::LDRSBWpost_isel: return ARM64::LDRSBWpost;
case ARM64::LDRSBXpost_isel: return ARM64::LDRSBXpost;
case ARM64::STRXpre_isel: return ARM64::STRXpre;
case ARM64::STRWpre_isel: return ARM64::STRWpre;
case ARM64::STRHHpre_isel: return ARM64::STRHHpre;
case ARM64::STRBBpre_isel: return ARM64::STRBBpre;
case ARM64::STRDpre_isel: return ARM64::STRDpre;
case ARM64::STRSpre_isel: return ARM64::STRSpre;
}
llvm_unreachable("Unexpected pre-indexed opcode!");
}
void ARM64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
if (emitPseudoExpansionLowering(OutStreamer, MI))
return;
if (ARM64FI->getLOHRelated().count(MI)) {
MCSymbol *LOHLabel = GetTempSymbol("loh", LOHLabelCounter++);
LOHInstToLabel[MI] = LOHLabel;
OutStreamer.EmitLabel(LOHLabel);
}
switch (MI->getOpcode()) {
default: break;
case ARM64::DBG_VALUE: {
if (isVerbose() && OutStreamer.hasRawTextSupport()) {
SmallString<128> TmpStr;
raw_svector_ostream OS(TmpStr);
PrintDebugValueComment(MI, OS);
OutStreamer.EmitRawText(StringRef(OS.str()));
}
return;
}
case ARM64::LDRHHpre_isel:
case ARM64::LDRBBpre_isel:
case ARM64::LDRXpre_isel:
case ARM64::LDRWpre_isel:
case ARM64::LDRDpre_isel:
case ARM64::LDRSpre_isel:
case ARM64::LDRSBWpre_isel:
case ARM64::LDRSBXpre_isel:
case ARM64::LDRSHWpre_isel:
case ARM64::LDRSHXpre_isel:
case ARM64::LDRSWpre_isel:
case ARM64::LDRDpost_isel:
case ARM64::LDRSpost_isel:
case ARM64::LDRXpost_isel:
case ARM64::LDRWpost_isel:
case ARM64::LDRHHpost_isel:
case ARM64::LDRBBpost_isel:
case ARM64::LDRSWpost_isel:
case ARM64::LDRSHWpost_isel:
case ARM64::LDRSHXpost_isel:
case ARM64::LDRSBWpost_isel:
case ARM64::LDRSBXpost_isel: {
MCInst TmpInst;
TmpInst.setOpcode(getRealIndexedOpcode(MI->getOpcode()));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(2).getReg()));
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM64::STRXpre_isel:
case ARM64::STRWpre_isel:
case ARM64::STRHHpre_isel:
case ARM64::STRBBpre_isel:
case ARM64::STRDpre_isel:
case ARM64::STRSpre_isel: {
MCInst TmpInst;
TmpInst.setOpcode(getRealIndexedOpcode(MI->getOpcode()));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(2).getReg()));
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM64::TCRETURNri: {
MCInst TmpInst;
TmpInst.setOpcode(ARM64::BR);
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM64::TCRETURNdi: {
MCOperand Dest;
MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
MCInst TmpInst;
TmpInst.setOpcode(ARM64::B);
TmpInst.addOperand(Dest);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case ARM64::TLSDESC_BLR: {
MCOperand Callee, Sym;
MCInstLowering.lowerOperand(MI->getOperand(0), Callee);
MCInstLowering.lowerOperand(MI->getOperand(1), Sym);
MCInst TLSDescCall;
TLSDescCall.setOpcode(ARM64::TLSDESCCALL);
TLSDescCall.addOperand(Sym);
OutStreamer.EmitInstruction(TLSDescCall);
MCInst BLR;
BLR.setOpcode(ARM64::BLR);
BLR.addOperand(Callee);
OutStreamer.EmitInstruction(BLR);
return;
}
case TargetOpcode::STACKMAP:
return LowerSTACKMAP(OutStreamer, SM, *MI);
case TargetOpcode::PATCHPOINT:
return LowerPATCHPOINT(OutStreamer, SM, *MI);
}
MCInst TmpInst;
MCInstLowering.Lower(MI, TmpInst);
OutStreamer.EmitInstruction(TmpInst);
}
extern "C" void LLVMInitializeARM64AsmPrinter() {
RegisterAsmPrinter<ARM64AsmPrinter> X(TheARM64Target);
}