LiveDebugVariables.cpp [plain text]
#define DEBUG_TYPE "livedebug"
#include "LiveDebugVariables.h"
#include "llvm/ADT/IntervalMap.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LexicalScopes.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/DebugInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Metadata.h"
#include "llvm/IR/Value.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
static cl::opt<bool>
EnableLDV("live-debug-variables", cl::init(true),
cl::desc("Enable the live debug variables pass"), cl::Hidden);
STATISTIC(NumInsertedDebugValues, "Number of DBG_VALUEs inserted");
char LiveDebugVariables::ID = 0;
INITIALIZE_PASS_BEGIN(LiveDebugVariables, "livedebugvars",
"Debug Variable Analysis", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
INITIALIZE_PASS_END(LiveDebugVariables, "livedebugvars",
"Debug Variable Analysis", false, false)
void LiveDebugVariables::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<MachineDominatorTree>();
AU.addRequiredTransitive<LiveIntervals>();
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
LiveDebugVariables::LiveDebugVariables() : MachineFunctionPass(ID), pImpl(0),
EmitDone(false), ModifiedMF(false) {
initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
}
typedef IntervalMap<SlotIndex, unsigned, 4> LocMap;
namespace {
class UserValueScopes {
DebugLoc DL;
LexicalScopes &LS;
SmallPtrSet<const MachineBasicBlock *, 4> LBlocks;
public:
UserValueScopes(DebugLoc D, LexicalScopes &L) : DL(D), LS(L) {}
bool dominates(MachineBasicBlock *MBB) {
if (LBlocks.empty())
LS.getMachineBasicBlocks(DL, LBlocks);
if (LBlocks.count(MBB) != 0 || LS.dominates(DL, MBB))
return true;
return false;
}
};
}
namespace {
class LDVImpl;
class UserValue {
const MDNode *variable; unsigned offset; DebugLoc dl; UserValue *leader; UserValue *next;
SmallVector<MachineOperand, 4> locations;
LocMap locInts;
void coalesceLocation(unsigned LocNo);
void insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo,
LiveIntervals &LIS, const TargetInstrInfo &TII);
bool splitLocation(unsigned OldLocNo, ArrayRef<LiveInterval*> NewRegs);
public:
UserValue(const MDNode *var, unsigned o, DebugLoc L,
LocMap::Allocator &alloc)
: variable(var), offset(o), dl(L), leader(this), next(0), locInts(alloc)
{}
UserValue *getLeader() {
UserValue *l = leader;
while (l != l->leader)
l = l->leader;
return leader = l;
}
UserValue *getNext() const { return next; }
bool match(const MDNode *Var, unsigned Offset) const {
return Var == variable && Offset == offset;
}
static UserValue *merge(UserValue *L1, UserValue *L2) {
L2 = L2->getLeader();
if (!L1)
return L2;
L1 = L1->getLeader();
if (L1 == L2)
return L1;
UserValue *End = L2;
while (End->next)
End->leader = L1, End = End->next;
End->leader = L1;
End->next = L1->next;
L1->next = L2;
return L1;
}
unsigned getLocationNo(const MachineOperand &LocMO) {
if (LocMO.isReg()) {
if (LocMO.getReg() == 0)
return ~0u;
for (unsigned i = 0, e = locations.size(); i != e; ++i)
if (locations[i].isReg() &&
locations[i].getReg() == LocMO.getReg() &&
locations[i].getSubReg() == LocMO.getSubReg())
return i;
} else
for (unsigned i = 0, e = locations.size(); i != e; ++i)
if (LocMO.isIdenticalTo(locations[i]))
return i;
locations.push_back(LocMO);
locations.back().clearParent();
if (locations.back().isReg())
locations.back().setIsUse();
return locations.size() - 1;
}
void mapVirtRegs(LDVImpl *LDV);
void addDef(SlotIndex Idx, const MachineOperand &LocMO) {
LocMap::iterator I = locInts.find(Idx);
if (!I.valid() || I.start() != Idx)
I.insert(Idx, Idx.getNextSlot(), getLocationNo(LocMO));
else
I.setValue(getLocationNo(LocMO));
}
void extendDef(SlotIndex Idx, unsigned LocNo,
LiveInterval *LI, const VNInfo *VNI,
SmallVectorImpl<SlotIndex> *Kills,
LiveIntervals &LIS, MachineDominatorTree &MDT,
UserValueScopes &UVS);
void addDefsFromCopies(LiveInterval *LI, unsigned LocNo,
const SmallVectorImpl<SlotIndex> &Kills,
SmallVectorImpl<std::pair<SlotIndex, unsigned> > &NewDefs,
MachineRegisterInfo &MRI,
LiveIntervals &LIS);
void computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
LiveIntervals &LIS, MachineDominatorTree &MDT,
UserValueScopes &UVS);
void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx,
const TargetRegisterInfo *TRI);
bool splitRegister(unsigned OldLocNo, ArrayRef<LiveInterval*> NewRegs);
void rewriteLocations(VirtRegMap &VRM, const TargetRegisterInfo &TRI);
void emitDebugValues(VirtRegMap *VRM,
LiveIntervals &LIS, const TargetInstrInfo &TRI);
DebugLoc findDebugLoc();
DebugLoc getDebugLoc() { return dl;}
void print(raw_ostream&, const TargetMachine*);
};
}
namespace {
class LDVImpl {
LiveDebugVariables &pass;
LocMap::Allocator allocator;
MachineFunction *MF;
LiveIntervals *LIS;
LexicalScopes LS;
MachineDominatorTree *MDT;
const TargetRegisterInfo *TRI;
SmallVector<UserValue*, 8> userValues;
typedef DenseMap<unsigned, UserValue*> VRMap;
VRMap virtRegToEqClass;
typedef DenseMap<const MDNode *, UserValue*> UVMap;
UVMap userVarMap;
UserValue *getUserValue(const MDNode *Var, unsigned Offset, DebugLoc DL);
UserValue *lookupVirtReg(unsigned VirtReg);
bool handleDebugValue(MachineInstr *MI, SlotIndex Idx);
bool collectDebugValues(MachineFunction &mf);
void computeIntervals();
public:
LDVImpl(LiveDebugVariables *ps) : pass(*ps) {}
bool runOnMachineFunction(MachineFunction &mf);
void clear() {
DeleteContainerPointers(userValues);
userValues.clear();
virtRegToEqClass.clear();
userVarMap.clear();
}
void mapVirtReg(unsigned VirtReg, UserValue *EC);
void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
void splitRegister(unsigned OldReg, ArrayRef<LiveInterval*> NewRegs);
void emitDebugValues(VirtRegMap *VRM);
void print(raw_ostream&);
};
}
void UserValue::print(raw_ostream &OS, const TargetMachine *TM) {
DIVariable DV(variable);
OS << "!\"";
DV.printExtendedName(OS);
OS << "\"\t";
if (offset)
OS << '+' << offset;
for (LocMap::const_iterator I = locInts.begin(); I.valid(); ++I) {
OS << " [" << I.start() << ';' << I.stop() << "):";
if (I.value() == ~0u)
OS << "undef";
else
OS << I.value();
}
for (unsigned i = 0, e = locations.size(); i != e; ++i) {
OS << " Loc" << i << '=';
locations[i].print(OS, TM);
}
OS << '\n';
}
void LDVImpl::print(raw_ostream &OS) {
OS << "********** DEBUG VARIABLES **********\n";
for (unsigned i = 0, e = userValues.size(); i != e; ++i)
userValues[i]->print(OS, &MF->getTarget());
}
void UserValue::coalesceLocation(unsigned LocNo) {
unsigned KeepLoc = 0;
for (unsigned e = locations.size(); KeepLoc != e; ++KeepLoc) {
if (KeepLoc == LocNo)
continue;
if (locations[KeepLoc].isIdenticalTo(locations[LocNo]))
break;
}
if (KeepLoc == locations.size())
return;
unsigned EraseLoc = LocNo;
if (KeepLoc > EraseLoc)
std::swap(KeepLoc, EraseLoc);
locations.erase(locations.begin() + EraseLoc);
for (LocMap::iterator I = locInts.begin(); I.valid(); ++I) {
unsigned v = I.value();
if (v == EraseLoc)
I.setValue(KeepLoc); else if (v > EraseLoc)
I.setValueUnchecked(v-1); }
}
void UserValue::mapVirtRegs(LDVImpl *LDV) {
for (unsigned i = 0, e = locations.size(); i != e; ++i)
if (locations[i].isReg() &&
TargetRegisterInfo::isVirtualRegister(locations[i].getReg()))
LDV->mapVirtReg(locations[i].getReg(), this);
}
UserValue *LDVImpl::getUserValue(const MDNode *Var, unsigned Offset,
DebugLoc DL) {
UserValue *&Leader = userVarMap[Var];
if (Leader) {
UserValue *UV = Leader->getLeader();
Leader = UV;
for (; UV; UV = UV->getNext())
if (UV->match(Var, Offset))
return UV;
}
UserValue *UV = new UserValue(Var, Offset, DL, allocator);
userValues.push_back(UV);
Leader = UserValue::merge(Leader, UV);
return UV;
}
void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) {
assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
UserValue *&Leader = virtRegToEqClass[VirtReg];
Leader = UserValue::merge(Leader, EC);
}
UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) {
if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
return UV->getLeader();
return 0;
}
bool LDVImpl::handleDebugValue(MachineInstr *MI, SlotIndex Idx) {
if (MI->getNumOperands() != 3 ||
!MI->getOperand(1).isImm() || !MI->getOperand(2).isMetadata()) {
DEBUG(dbgs() << "Can't handle " << *MI);
return false;
}
unsigned Offset = MI->getOperand(1).getImm();
const MDNode *Var = MI->getOperand(2).getMetadata();
UserValue *UV = getUserValue(Var, Offset, MI->getDebugLoc());
UV->addDef(Idx, MI->getOperand(0));
return true;
}
bool LDVImpl::collectDebugValues(MachineFunction &mf) {
bool Changed = false;
for (MachineFunction::iterator MFI = mf.begin(), MFE = mf.end(); MFI != MFE;
++MFI) {
MachineBasicBlock *MBB = MFI;
for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
MBBI != MBBE;) {
if (!MBBI->isDebugValue()) {
++MBBI;
continue;
}
SlotIndex Idx = MBBI == MBB->begin() ?
LIS->getMBBStartIdx(MBB) :
LIS->getInstructionIndex(llvm::prior(MBBI)).getRegSlot();
do {
if (handleDebugValue(MBBI, Idx)) {
MBBI = MBB->erase(MBBI);
Changed = true;
} else
++MBBI;
} while (MBBI != MBBE && MBBI->isDebugValue());
}
}
return Changed;
}
void UserValue::extendDef(SlotIndex Idx, unsigned LocNo,
LiveInterval *LI, const VNInfo *VNI,
SmallVectorImpl<SlotIndex> *Kills,
LiveIntervals &LIS, MachineDominatorTree &MDT,
UserValueScopes &UVS) {
SmallVector<SlotIndex, 16> Todo;
Todo.push_back(Idx);
do {
SlotIndex Start = Todo.pop_back_val();
MachineBasicBlock *MBB = LIS.getMBBFromIndex(Start);
SlotIndex Stop = LIS.getMBBEndIdx(MBB);
LocMap::iterator I = locInts.find(Start);
bool ToEnd = true;
if (LI && VNI) {
LiveRange *Range = LI->getLiveRangeContaining(Start);
if (!Range || Range->valno != VNI) {
if (Kills)
Kills->push_back(Start);
continue;
}
if (Range->end < Stop)
Stop = Range->end, ToEnd = false;
}
if (I.valid() && I.start() <= Start) {
Start = Start.getNextSlot();
if (I.value() != LocNo || I.stop() != Start)
continue;
++I;
}
if (I.valid() && I.start() < Stop)
Stop = I.start(), ToEnd = false;
else if (!ToEnd && Kills)
Kills->push_back(Stop);
if (Start >= Stop)
continue;
I.insert(Start, Stop, LocNo);
if (!ToEnd)
continue;
const std::vector<MachineDomTreeNode*> &Children =
MDT.getNode(MBB)->getChildren();
for (unsigned i = 0, e = Children.size(); i != e; ++i) {
MachineBasicBlock *MBB = Children[i]->getBlock();
if (UVS.dominates(MBB))
Todo.push_back(LIS.getMBBStartIdx(MBB));
}
} while (!Todo.empty());
}
void
UserValue::addDefsFromCopies(LiveInterval *LI, unsigned LocNo,
const SmallVectorImpl<SlotIndex> &Kills,
SmallVectorImpl<std::pair<SlotIndex, unsigned> > &NewDefs,
MachineRegisterInfo &MRI, LiveIntervals &LIS) {
if (Kills.empty())
return;
if (!TargetRegisterInfo::isVirtualRegister(LI->reg))
return;
SmallVector<std::pair<LiveInterval*, const VNInfo*>, 8> CopyValues;
for (MachineRegisterInfo::use_nodbg_iterator
UI = MRI.use_nodbg_begin(LI->reg),
UE = MRI.use_nodbg_end(); UI != UE; ++UI) {
if (UI.getOperand().getSubReg() || !UI->isCopy())
continue;
MachineInstr *MI = &*UI;
unsigned DstReg = MI->getOperand(0).getReg();
if (!TargetRegisterInfo::isVirtualRegister(DstReg))
continue;
SlotIndex Idx = LIS.getInstructionIndex(MI);
LocMap::iterator I = locInts.find(Idx.getRegSlot(true));
if (!I.valid() || I.value() != LocNo)
continue;
if (!LIS.hasInterval(DstReg))
continue;
LiveInterval *DstLI = &LIS.getInterval(DstReg);
const VNInfo *DstVNI = DstLI->getVNInfoAt(Idx.getRegSlot());
assert(DstVNI && DstVNI->def == Idx.getRegSlot() && "Bad copy value");
CopyValues.push_back(std::make_pair(DstLI, DstVNI));
}
if (CopyValues.empty())
return;
DEBUG(dbgs() << "Got " << CopyValues.size() << " copies of " << *LI << '\n');
for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
SlotIndex Idx = Kills[i];
for (unsigned j = 0, e = CopyValues.size(); j != e; ++j) {
LiveInterval *DstLI = CopyValues[j].first;
const VNInfo *DstVNI = CopyValues[j].second;
if (DstLI->getVNInfoAt(Idx) != DstVNI)
continue;
LocMap::iterator I = locInts.find(Idx);
if (I.valid() && I.start() <= Idx)
continue;
DEBUG(dbgs() << "Kill at " << Idx << " covered by valno #"
<< DstVNI->id << " in " << *DstLI << '\n');
MachineInstr *CopyMI = LIS.getInstructionFromIndex(DstVNI->def);
assert(CopyMI && CopyMI->isCopy() && "Bad copy value");
unsigned LocNo = getLocationNo(CopyMI->getOperand(0));
I.insert(Idx, Idx.getNextSlot(), LocNo);
NewDefs.push_back(std::make_pair(Idx, LocNo));
break;
}
}
}
void
UserValue::computeIntervals(MachineRegisterInfo &MRI,
const TargetRegisterInfo &TRI,
LiveIntervals &LIS,
MachineDominatorTree &MDT,
UserValueScopes &UVS) {
SmallVector<std::pair<SlotIndex, unsigned>, 16> Defs;
for (LocMap::const_iterator I = locInts.begin(); I.valid(); ++I)
if (I.value() != ~0u)
Defs.push_back(std::make_pair(I.start(), I.value()));
for (unsigned i = 0; i != Defs.size(); ++i) {
SlotIndex Idx = Defs[i].first;
unsigned LocNo = Defs[i].second;
const MachineOperand &Loc = locations[LocNo];
if (!Loc.isReg()) {
extendDef(Idx, LocNo, 0, 0, 0, LIS, MDT, UVS);
continue;
}
if (TargetRegisterInfo::isVirtualRegister(Loc.getReg())) {
LiveInterval *LI = 0;
const VNInfo *VNI = 0;
if (LIS.hasInterval(Loc.getReg())) {
LI = &LIS.getInterval(Loc.getReg());
VNI = LI->getVNInfoAt(Idx);
}
SmallVector<SlotIndex, 16> Kills;
extendDef(Idx, LocNo, LI, VNI, &Kills, LIS, MDT, UVS);
if (LI)
addDefsFromCopies(LI, LocNo, Kills, Defs, MRI, LIS);
continue;
}
unsigned Unit = *MCRegUnitIterator(Loc.getReg(), &TRI);
LiveInterval *LI = &LIS.getRegUnit(Unit);
const VNInfo *VNI = LI->getVNInfoAt(Idx);
extendDef(Idx, LocNo, LI, VNI, 0, LIS, MDT, UVS);
}
for (LocMap::iterator I = locInts.begin(); I.valid();)
if (I.value() == ~0u)
I.erase();
else
++I;
}
void LDVImpl::computeIntervals() {
for (unsigned i = 0, e = userValues.size(); i != e; ++i) {
UserValueScopes UVS(userValues[i]->getDebugLoc(), LS);
userValues[i]->computeIntervals(MF->getRegInfo(), *TRI, *LIS, *MDT, UVS);
userValues[i]->mapVirtRegs(this);
}
}
bool LDVImpl::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
LIS = &pass.getAnalysis<LiveIntervals>();
MDT = &pass.getAnalysis<MachineDominatorTree>();
TRI = mf.getTarget().getRegisterInfo();
clear();
LS.initialize(mf);
DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: "
<< mf.getName() << " **********\n");
bool Changed = collectDebugValues(mf);
computeIntervals();
DEBUG(print(dbgs()));
LS.releaseMemory();
return Changed;
}
bool LiveDebugVariables::runOnMachineFunction(MachineFunction &mf) {
if (!EnableLDV)
return false;
if (!pImpl)
pImpl = new LDVImpl(this);
ModifiedMF = static_cast<LDVImpl*>(pImpl)->runOnMachineFunction(mf);
return ModifiedMF;
}
void LiveDebugVariables::releaseMemory() {
if (pImpl) {
static_cast<LDVImpl*>(pImpl)->clear();
assert((!ModifiedMF || EmitDone) &&
"Dbg values are not emitted in LDV");
}
}
LiveDebugVariables::~LiveDebugVariables() {
if (pImpl)
delete static_cast<LDVImpl*>(pImpl);
}
void UserValue::
renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx,
const TargetRegisterInfo *TRI) {
for (unsigned i = locations.size(); i; --i) {
unsigned LocNo = i - 1;
MachineOperand &Loc = locations[LocNo];
if (!Loc.isReg() || Loc.getReg() != OldReg)
continue;
if (TargetRegisterInfo::isPhysicalRegister(NewReg))
Loc.substPhysReg(NewReg, *TRI);
else
Loc.substVirtReg(NewReg, SubIdx, *TRI);
coalesceLocation(LocNo);
}
}
void LDVImpl::
renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) {
UserValue *UV = lookupVirtReg(OldReg);
if (!UV)
return;
if (TargetRegisterInfo::isVirtualRegister(NewReg))
mapVirtReg(NewReg, UV);
if (OldReg != NewReg)
virtRegToEqClass.erase(OldReg);
do {
UV->renameRegister(OldReg, NewReg, SubIdx, TRI);
UV = UV->getNext();
} while (UV);
}
void LiveDebugVariables::
renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) {
if (pImpl)
static_cast<LDVImpl*>(pImpl)->renameRegister(OldReg, NewReg, SubIdx);
}
bool
UserValue::splitLocation(unsigned OldLocNo, ArrayRef<LiveInterval*> NewRegs) {
DEBUG({
dbgs() << "Splitting Loc" << OldLocNo << '\t';
print(dbgs(), 0);
});
bool DidChange = false;
LocMap::iterator LocMapI;
LocMapI.setMap(locInts);
for (unsigned i = 0; i != NewRegs.size(); ++i) {
LiveInterval *LI = NewRegs[i];
if (LI->empty())
continue;
unsigned NewLocNo = ~0u;
LocMapI.find(LI->beginIndex());
if (!LocMapI.valid())
continue;
LiveInterval::iterator LII = LI->advanceTo(LI->begin(), LocMapI.start());
LiveInterval::iterator LIE = LI->end();
while (LocMapI.valid() && LII != LIE) {
LII = LI->advanceTo(LII, LocMapI.start());
if (LII == LIE)
break;
if (LocMapI.value() == OldLocNo && LII->start < LocMapI.stop()) {
if (NewLocNo == ~0u) {
MachineOperand MO = MachineOperand::CreateReg(LI->reg, false);
MO.setSubReg(locations[OldLocNo].getSubReg());
NewLocNo = getLocationNo(MO);
DidChange = true;
}
SlotIndex LStart = LocMapI.start();
SlotIndex LStop = LocMapI.stop();
if (LStart < LII->start)
LocMapI.setStartUnchecked(LII->start);
if (LStop > LII->end)
LocMapI.setStopUnchecked(LII->end);
LocMapI.setValue(NewLocNo);
if (LStart < LocMapI.start()) {
LocMapI.insert(LStart, LocMapI.start(), OldLocNo);
++LocMapI;
assert(LocMapI.valid() && "Unexpected coalescing");
}
if (LStop > LocMapI.stop()) {
++LocMapI;
LocMapI.insert(LII->end, LStop, OldLocNo);
--LocMapI;
}
}
if (LII->end < LocMapI.stop()) {
if (++LII == LIE)
break;
LocMapI.advanceTo(LII->start);
} else {
++LocMapI;
if (!LocMapI.valid())
break;
LII = LI->advanceTo(LII, LocMapI.start());
}
}
}
locations.erase(locations.begin() + OldLocNo);
LocMapI.goToBegin();
while (LocMapI.valid()) {
unsigned v = LocMapI.value();
if (v == OldLocNo) {
DEBUG(dbgs() << "Erasing [" << LocMapI.start() << ';'
<< LocMapI.stop() << ")\n");
LocMapI.erase();
} else {
if (v > OldLocNo)
LocMapI.setValueUnchecked(v-1);
++LocMapI;
}
}
DEBUG({dbgs() << "Split result: \t"; print(dbgs(), 0);});
return DidChange;
}
bool
UserValue::splitRegister(unsigned OldReg, ArrayRef<LiveInterval*> NewRegs) {
bool DidChange = false;
for (unsigned i = locations.size(); i ; --i) {
unsigned LocNo = i-1;
const MachineOperand *Loc = &locations[LocNo];
if (!Loc->isReg() || Loc->getReg() != OldReg)
continue;
DidChange |= splitLocation(LocNo, NewRegs);
}
return DidChange;
}
void LDVImpl::splitRegister(unsigned OldReg, ArrayRef<LiveInterval*> NewRegs) {
bool DidChange = false;
for (UserValue *UV = lookupVirtReg(OldReg); UV; UV = UV->getNext())
DidChange |= UV->splitRegister(OldReg, NewRegs);
if (!DidChange)
return;
UserValue *UV = lookupVirtReg(OldReg);
for (unsigned i = 0; i != NewRegs.size(); ++i)
mapVirtReg(NewRegs[i]->reg, UV);
}
void LiveDebugVariables::
splitRegister(unsigned OldReg, ArrayRef<LiveInterval*> NewRegs) {
if (pImpl)
static_cast<LDVImpl*>(pImpl)->splitRegister(OldReg, NewRegs);
}
void
UserValue::rewriteLocations(VirtRegMap &VRM, const TargetRegisterInfo &TRI) {
for (unsigned i = locations.size(); i ; --i) {
unsigned LocNo = i-1;
MachineOperand &Loc = locations[LocNo];
if (!Loc.isReg() || !Loc.getReg() ||
!TargetRegisterInfo::isVirtualRegister(Loc.getReg()))
continue;
unsigned VirtReg = Loc.getReg();
if (VRM.isAssignedReg(VirtReg) &&
TargetRegisterInfo::isPhysicalRegister(VRM.getPhys(VirtReg))) {
Loc.substPhysReg(VRM.getPhys(VirtReg), TRI);
} else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT) {
Loc = MachineOperand::CreateFI(VRM.getStackSlot(VirtReg));
} else {
Loc.setReg(0);
Loc.setSubReg(0);
}
coalesceLocation(LocNo);
}
}
static MachineBasicBlock::iterator
findInsertLocation(MachineBasicBlock *MBB, SlotIndex Idx,
LiveIntervals &LIS) {
SlotIndex Start = LIS.getMBBStartIdx(MBB);
Idx = Idx.getBaseIndex();
MachineInstr *MI;
while (!(MI = LIS.getInstructionFromIndex(Idx))) {
if (Idx == Start) {
MachineBasicBlock::iterator I = MBB->SkipPHIsAndLabels(MBB->begin());
return I;
}
Idx = Idx.getPrevIndex();
}
return MI->isTerminator() ? MBB->getFirstTerminator() :
llvm::next(MachineBasicBlock::iterator(MI));
}
DebugLoc UserValue::findDebugLoc() {
DebugLoc D = dl;
dl = DebugLoc();
return D;
}
void UserValue::insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx,
unsigned LocNo,
LiveIntervals &LIS,
const TargetInstrInfo &TII) {
MachineBasicBlock::iterator I = findInsertLocation(MBB, Idx, LIS);
MachineOperand &Loc = locations[LocNo];
++NumInsertedDebugValues;
if (Loc.isFI()) {
MachineInstr *MI = TII.emitFrameIndexDebugValue(*MBB->getParent(),
Loc.getIndex(), offset, variable,
findDebugLoc());
if (MI) {
MBB->insert(I, MI);
return;
}
}
BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))
.addOperand(Loc).addImm(offset).addMetadata(variable);
}
void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
const TargetInstrInfo &TII) {
MachineFunction::iterator MFEnd = VRM->getMachineFunction().end();
for (LocMap::const_iterator I = locInts.begin(); I.valid();) {
SlotIndex Start = I.start();
SlotIndex Stop = I.stop();
unsigned LocNo = I.value();
DEBUG(dbgs() << "\t[" << Start << ';' << Stop << "):" << LocNo);
MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB);
DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd);
insertDebugValue(MBB, Start, LocNo, LIS, TII);
while(Stop > MBBEnd) {
Start = MBBEnd;
if (++MBB == MFEnd)
break;
MBBEnd = LIS.getMBBEndIdx(MBB);
DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd);
insertDebugValue(MBB, Start, LocNo, LIS, TII);
}
DEBUG(dbgs() << '\n');
if (MBB == MFEnd)
break;
++I;
}
}
void LDVImpl::emitDebugValues(VirtRegMap *VRM) {
DEBUG(dbgs() << "********** EMITTING LIVE DEBUG VARIABLES **********\n");
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
for (unsigned i = 0, e = userValues.size(); i != e; ++i) {
DEBUG(userValues[i]->print(dbgs(), &MF->getTarget()));
userValues[i]->rewriteLocations(*VRM, *TRI);
userValues[i]->emitDebugValues(VRM, *LIS, *TII);
}
}
void LiveDebugVariables::emitDebugValues(VirtRegMap *VRM) {
if (pImpl) {
static_cast<LDVImpl*>(pImpl)->emitDebugValues(VRM);
EmitDone = true;
}
}
#ifndef NDEBUG
void LiveDebugVariables::dump() {
if (pImpl)
static_cast<LDVImpl*>(pImpl)->print(dbgs());
}
#endif