#ifndef ARMSUBTARGET_H
#define ARMSUBTARGET_H
#include "MCTargetDesc/ARMMCTargetDesc.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/ADT/Triple.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
#include "ARMGenSubtargetInfo.inc"
namespace llvm {
class GlobalValue;
class StringRef;
class ARMSubtarget : public ARMGenSubtargetInfo {
protected:
enum ARMProcFamilyEnum {
Others, CortexA8, CortexA9, CortexA15, Swift
};
ARMProcFamilyEnum ARMProcFamily;
bool HasV4TOps;
bool HasV5TOps;
bool HasV5TEOps;
bool HasV6Ops;
bool HasV6T2Ops;
bool HasV7Ops;
bool HasVFPv2;
bool HasVFPv3;
bool HasVFPv4;
bool HasNEON;
bool UseNEONForSinglePrecisionFP;
bool UseMulOps;
bool SlowFPVMLx;
bool HasVMLxForwarding;
bool SlowFPBrcc;
bool InThumbMode;
bool HasThumb2;
bool IsMClass;
bool NoARM;
bool PostRAScheduler;
bool IsR9Reserved;
bool UseMovt;
bool SupportsTailCall;
bool HasFP16;
bool HasD16;
bool HasHardwareDivide;
bool HasHardwareDivideInARM;
bool HasT2ExtractPack;
bool HasDataBarrier;
bool Pref32BitThumb;
bool AvoidCPSRPartialUpdate;
bool HasRAS;
bool HasMPExtension;
bool FPOnlySP;
bool AllowsUnalignedMem;
bool Thumb2DSP;
unsigned stackAlignment;
std::string CPUString;
Triple TargetTriple;
const MCSchedModel *SchedModel;
InstrItineraryData InstrItins;
public:
enum {
isELF, isDarwin
} TargetType;
enum {
ARM_ABI_APCS,
ARM_ABI_AAPCS } TargetABI;
ARMSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS);
unsigned getMaxInlineSizeThreshold() const {
return isThumb1Only() ? 0 : 64;
}
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void computeIssueWidth();
bool hasV4TOps() const { return HasV4TOps; }
bool hasV5TOps() const { return HasV5TOps; }
bool hasV5TEOps() const { return HasV5TEOps; }
bool hasV6Ops() const { return HasV6Ops; }
bool hasV6T2Ops() const { return HasV6T2Ops; }
bool hasV7Ops() const { return HasV7Ops; }
bool isCortexA7() const { return CPUString == "cortex-a7"; }
bool isCortexA8() const { return ARMProcFamily == CortexA8; }
bool isCortexA9() const { return ARMProcFamily == CortexA9; }
bool isCortexA15() const { return ARMProcFamily == CortexA15; }
bool isSwift() const { return ARMProcFamily == Swift; }
bool isCortexM3() const { return CPUString == "cortex-m3"; }
bool isLikeA9() const { return isCortexA9() || isCortexA15(); }
bool hasARMOps() const { return !NoARM; }
bool hasVFP2() const { return HasVFPv2; }
bool hasVFP3() const { return HasVFPv3; }
bool hasVFP4() const { return HasVFPv4; }
bool hasNEON() const { return HasNEON; }
bool useNEONForSinglePrecisionFP() const {
return hasNEON() && UseNEONForSinglePrecisionFP; }
bool hasDivide() const { return HasHardwareDivide; }
bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
bool hasT2ExtractPack() const { return HasT2ExtractPack; }
bool hasDataBarrier() const { return HasDataBarrier; }
bool useMulOps() const { return UseMulOps; }
bool useFPVMLx() const { return !SlowFPVMLx; }
bool hasVMLxForwarding() const { return HasVMLxForwarding; }
bool isFPBrccSlow() const { return SlowFPBrcc; }
bool isFPOnlySP() const { return FPOnlySP; }
bool prefers32BitThumb() const { return Pref32BitThumb; }
bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
bool hasRAS() const { return HasRAS; }
bool hasMPExtension() const { return HasMPExtension; }
bool hasThumb2DSP() const { return Thumb2DSP; }
bool hasFP16() const { return HasFP16; }
bool hasD16() const { return HasD16; }
const Triple &getTargetTriple() const { return TargetTriple; }
bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; }
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
bool isTargetNaCl() const {
return TargetTriple.getOS() == Triple::NativeClient;
}
bool isTargetELF() const { return !isTargetDarwin(); }
bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
bool isThumb() const { return InThumbMode; }
bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
bool isThumb2() const { return InThumbMode && HasThumb2; }
bool hasThumb2() const { return HasThumb2; }
bool isMClass() const { return IsMClass; }
bool isARClass() const { return !IsMClass; }
bool isR9Reserved() const { return IsR9Reserved; }
bool useMovt() const { return UseMovt && hasV6T2Ops(); }
bool supportsTailCall() const { return SupportsTailCall; }
bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
const std::string & getCPUString() const { return CPUString; }
unsigned getMispredictionPenalty() const;
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const;
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
unsigned getStackAlignment() const { return stackAlignment; }
bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
};
}
#endif // ARMSUBTARGET_H