#include "llvm/Analysis/Passes.h"
#include "llvm/Analysis/Verifier.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/PassManager.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Assembly/PrintModulePass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
using namespace llvm;
static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
cl::desc("Disable Post Regalloc"));
static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
cl::desc("Disable branch folding"));
static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
cl::desc("Disable tail duplication"));
static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
cl::desc("Disable pre-register allocation tail duplication"));
static cl::opt<bool> EnableBlockPlacement("enable-block-placement",
cl::Hidden, cl::desc("Enable probability-driven block placement"));
static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
cl::desc("Disable code placement"));
static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
cl::desc("Disable Stack Slot Coloring"));
static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
cl::desc("Disable Machine Dead Code Elimination"));
static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
cl::desc("Disable Machine LICM"));
static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
cl::desc("Disable Machine Common Subexpression Elimination"));
static cl::opt<cl::boolOrDefault>
OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
cl::desc("Enable optimized register allocation compilation path."));
static cl::opt<cl::boolOrDefault>
EnableMachineSched("enable-misched", cl::Hidden,
cl::desc("Enable the machine instruction scheduling pass."));
static cl::opt<bool> EnableStrongPHIElim("strong-phi-elim", cl::Hidden,
cl::desc("Use strong PHI elimination."));
static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
cl::Hidden,
cl::desc("Disable Machine LICM"));
static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
cl::desc("Disable Machine Sinking"));
static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
cl::desc("Disable Loop Strength Reduction Pass"));
static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
cl::desc("Disable Codegen Prepare"));
static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
cl::desc("Disable Copy Propagation pass"));
static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
cl::desc("Print LLVM IR produced by the loop-reduce pass"));
static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
cl::desc("Print LLVM IR input to isel pass"));
static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
cl::desc("Dump garbage collector data"));
static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
cl::desc("Verify generated machine code"),
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
static AnalysisID applyDisable(AnalysisID ID, bool Override) {
if (Override)
return &NoPassID;
return ID;
}
static AnalysisID applyOverride(AnalysisID TargetID, cl::boolOrDefault Override,
AnalysisID StandardID) {
switch (Override) {
case cl::BOU_UNSET:
return TargetID;
case cl::BOU_TRUE:
if (TargetID != &NoPassID)
return TargetID;
if (StandardID == &NoPassID)
report_fatal_error("Target cannot enable pass");
return StandardID;
case cl::BOU_FALSE:
return &NoPassID;
}
llvm_unreachable("Invalid command line option state");
}
static AnalysisID overridePass(AnalysisID StandardID, AnalysisID TargetID) {
if (StandardID == &PostRASchedulerID)
return applyDisable(TargetID, DisablePostRA);
if (StandardID == &BranchFolderPassID)
return applyDisable(TargetID, DisableBranchFold);
if (StandardID == &TailDuplicateID)
return applyDisable(TargetID, DisableTailDuplicate);
if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
return applyDisable(TargetID, DisableEarlyTailDup);
if (StandardID == &MachineBlockPlacementID)
return applyDisable(TargetID, DisableCodePlace);
if (StandardID == &CodePlacementOptID)
return applyDisable(TargetID, DisableCodePlace);
if (StandardID == &StackSlotColoringID)
return applyDisable(TargetID, DisableSSC);
if (StandardID == &DeadMachineInstructionElimID)
return applyDisable(TargetID, DisableMachineDCE);
if (StandardID == &MachineLICMID)
return applyDisable(TargetID, DisableMachineLICM);
if (StandardID == &MachineCSEID)
return applyDisable(TargetID, DisableMachineCSE);
if (StandardID == &MachineSchedulerID)
return applyOverride(TargetID, EnableMachineSched, StandardID);
if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
return applyDisable(TargetID, DisablePostRAMachineLICM);
if (StandardID == &MachineSinkingID)
return applyDisable(TargetID, DisableMachineSink);
if (StandardID == &MachineCopyPropagationID)
return applyDisable(TargetID, DisableCopyProp);
return TargetID;
}
INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
"Target Pass Configuration", false, false)
char TargetPassConfig::ID = 0;
static char NoPassIDAnchor = 0;
char &llvm::NoPassID = NoPassIDAnchor;
char TargetPassConfig::EarlyTailDuplicateID = 0;
char TargetPassConfig::PostRAMachineLICMID = 0;
namespace llvm {
class PassConfigImpl {
public:
DenseMap<AnalysisID,AnalysisID> TargetPasses;
};
}
TargetPassConfig::~TargetPassConfig() {
delete Impl;
}
TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
: ImmutablePass(ID), TM(tm), PM(pm), Impl(0), Initialized(false),
DisableVerify(false),
EnableTailMerge(true) {
Impl = new PassConfigImpl();
initializeCodeGen(*PassRegistry::getPassRegistry());
substitutePass(EarlyTailDuplicateID, TailDuplicateID);
substitutePass(PostRAMachineLICMID, MachineLICMID);
substitutePass(MachineSchedulerID, NoPassID);
}
TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
return new TargetPassConfig(this, PM);
}
TargetPassConfig::TargetPassConfig()
: ImmutablePass(ID), PM(*(PassManagerBase*)0) {
llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
}
void TargetPassConfig::setOpt(bool &Opt, bool Val) {
assert(!Initialized && "PassConfig is immutable");
Opt = Val;
}
void TargetPassConfig::substitutePass(char &StandardID, char &TargetID) {
Impl->TargetPasses[&StandardID] = &TargetID;
}
AnalysisID TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
DenseMap<AnalysisID, AnalysisID>::const_iterator
I = Impl->TargetPasses.find(ID);
if (I == Impl->TargetPasses.end())
return ID;
return I->second;
}
AnalysisID TargetPassConfig::addPass(char &ID) {
assert(!Initialized && "PassConfig is immutable");
AnalysisID TargetID = getPassSubstitution(&ID);
AnalysisID FinalID = overridePass(&ID, TargetID);
if (FinalID == &NoPassID)
return FinalID;
Pass *P = Pass::createPass(FinalID);
if (!P)
llvm_unreachable("Pass ID not registered");
PM.add(P);
return FinalID;
}
void TargetPassConfig::printNoVerify(const char *Banner) const {
if (TM->shouldPrintMachineCode())
PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
}
void TargetPassConfig::printAndVerify(const char *Banner) const {
if (TM->shouldPrintMachineCode())
PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
if (VerifyMachineCode)
PM.add(createMachineVerifierPass(Banner));
}
void TargetPassConfig::addIRPasses() {
PM.add(createTypeBasedAliasAnalysisPass());
PM.add(createBasicAliasAnalysisPass());
if (!DisableVerify)
PM.add(createVerifierPass());
if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
}
PM.add(createGCLoweringPass());
PM.add(createUnreachableBlockEliminationPass());
}
void TargetPassConfig::addISelPrepare() {
if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering()));
addPreISel();
if (PrintISelInput)
PM.add(createPrintFunctionPass("\n\n"
"*** Final LLVM Code input to ISel ***\n",
&dbgs()));
if (!DisableVerify)
PM.add(createVerifierPass());
}
void TargetPassConfig::addMachinePasses() {
printAndVerify("After Instruction Selection");
addPass(ExpandISelPseudosID);
if (getOptLevel() != CodeGenOpt::None) {
addMachineSSAOptimization();
}
else {
addPass(LocalStackSlotAllocationID);
}
if (addPreRegAlloc())
printAndVerify("After PreRegAlloc passes");
if (getOptimizeRegAlloc())
addOptimizedRegAlloc(createRegAllocPass(true));
else
addFastRegAlloc(createRegAllocPass(false));
if (addPostRegAlloc())
printAndVerify("After PostRegAlloc passes");
addPass(PrologEpilogCodeInserterID);
printAndVerify("After PrologEpilogCodeInserter");
if (getOptLevel() != CodeGenOpt::None)
addMachineLateOptimization();
addPass(ExpandPostRAPseudosID);
printNoVerify("After ExpandPostRAPseudos");
if (addPreSched2())
printNoVerify("After PreSched2 passes");
if (getOptLevel() != CodeGenOpt::None) {
addPass(PostRASchedulerID);
printNoVerify("After PostRAScheduler");
}
addPass(GCMachineCodeAnalysisID);
if (PrintGCInfo)
PM.add(createGCInfoPrinter(dbgs()));
if (getOptLevel() != CodeGenOpt::None)
addBlockPlacement();
if (addPreEmitPass())
printNoVerify("After PreEmit passes");
}
void TargetPassConfig::addMachineSSAOptimization() {
if (addPass(EarlyTailDuplicateID) != &NoPassID)
printAndVerify("After Pre-RegAlloc TailDuplicate");
addPass(OptimizePHIsID);
addPass(LocalStackSlotAllocationID);
addPass(DeadMachineInstructionElimID);
printAndVerify("After codegen DCE pass");
addPass(MachineLICMID);
addPass(MachineCSEID);
addPass(MachineSinkingID);
printAndVerify("After Machine LICM, CSE and Sinking passes");
addPass(PeepholeOptimizerID);
printAndVerify("After codegen peephole optimization pass");
}
bool TargetPassConfig::getOptimizeRegAlloc() const {
switch (OptimizeRegAlloc) {
case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
case cl::BOU_TRUE: return true;
case cl::BOU_FALSE: return false;
}
llvm_unreachable("Invalid optimize-regalloc state");
}
MachinePassRegistry RegisterRegAlloc::Registry;
static FunctionPass *useDefaultRegisterAllocator() { return 0; }
static RegisterRegAlloc
defaultRegAlloc("default",
"pick register allocator based on -O option",
useDefaultRegisterAllocator);
static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
RegisterPassParser<RegisterRegAlloc> >
RegAlloc("regalloc",
cl::init(&useDefaultRegisterAllocator),
cl::desc("Register allocator to use"));
FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
if (Optimized)
return createGreedyRegisterAllocator();
else
return createFastRegisterAllocator();
}
FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
if (!Ctor) {
Ctor = RegAlloc;
RegisterRegAlloc::setDefault(RegAlloc);
}
if (Ctor != useDefaultRegisterAllocator)
return Ctor();
return createTargetRegisterAllocator(Optimized);
}
void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
addPass(PHIEliminationID);
addPass(TwoAddressInstructionPassID);
PM.add(RegAllocPass);
printAndVerify("After Register Allocation");
}
void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
addPass(LiveVariablesID);
if (!EnableStrongPHIElim) {
addPass(MachineLoopInfoID);
addPass(PHIEliminationID);
}
addPass(TwoAddressInstructionPassID);
addPass(ProcessImplicitDefsID);
if (EnableStrongPHIElim)
addPass(StrongPHIEliminationID);
addPass(RegisterCoalescerID);
addPass(MachineSchedulerID);
PM.add(RegAllocPass);
printAndVerify("After Register Allocation");
if (addFinalizeRegAlloc())
printAndVerify("After RegAlloc finalization");
addPass(StackSlotColoringID);
addPass(PostRAMachineLICMID);
printAndVerify("After StackSlotColoring and postra Machine LICM");
}
void TargetPassConfig::addMachineLateOptimization() {
if (addPass(BranchFolderPassID) != &NoPassID)
printNoVerify("After BranchFolding");
if (addPass(TailDuplicateID) != &NoPassID)
printNoVerify("After TailDuplicate");
if (addPass(MachineCopyPropagationID) != &NoPassID)
printNoVerify("After copy propagation pass");
}
void TargetPassConfig::addBlockPlacement() {
AnalysisID ID = &NoPassID;
if (EnableBlockPlacement) {
ID = addPass(MachineBlockPlacementID);
} else {
ID = addPass(CodePlacementOptID);
}
if (ID != &NoPassID) {
if (EnableBlockPlacementStats)
addPass(MachineBlockPlacementStatsID);
printNoVerify("After machine block placement.");
}
}