#ifndef X86SUBTARGET_H
#define X86SUBTARGET_H
#include "llvm/ADT/Triple.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/CallingConv.h"
#include <string>
#define GET_SUBTARGETINFO_HEADER
#include "X86GenSubtargetInfo.inc"
namespace llvm {
class GlobalValue;
class StringRef;
class TargetMachine;
namespace PICStyles {
enum Style {
StubPIC, StubDynamicNoPIC, GOT, RIPRel, None };
}
class X86Subtarget : public X86GenSubtargetInfo {
protected:
enum X86SSEEnum {
NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
};
enum X863DNowEnum {
NoThreeDNow, ThreeDNow, ThreeDNowA
};
enum X86ProcFamilyEnum {
Others, IntelAtom
};
X86ProcFamilyEnum X86ProcFamily;
PICStyles::Style PICStyle;
X86SSEEnum X86SSELevel;
X863DNowEnum X863DNowLevel;
bool HasCMov;
bool HasX86_64;
bool HasPOPCNT;
bool HasSSE4A;
bool HasAES;
bool HasCLMUL;
bool HasFMA3;
bool HasFMA4;
bool HasXOP;
bool HasMOVBE;
bool HasRDRAND;
bool HasF16C;
bool HasFSGSBase;
bool HasLZCNT;
bool HasBMI;
bool HasBMI2;
bool IsBTMemSlow;
bool IsUAMemFast;
bool HasVectorUAMem;
bool HasCmpxchg16b;
bool UseLeaForSP;
bool PostRAScheduler;
unsigned stackAlignment;
unsigned MaxInlineSizeThreshold;
Triple TargetTriple;
InstrItineraryData InstrItins;
private:
bool In64BitMode;
public:
X86Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS,
unsigned StackAlignOverride, bool is64Bit);
unsigned getStackAlignment() const { return stackAlignment; }
unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void AutoDetectSubtargetFeatures();
bool is64Bit() const { return In64BitMode; }
PICStyles::Style getPICStyle() const { return PICStyle; }
void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
bool hasCMov() const { return HasCMov; }
bool hasMMX() const { return X86SSELevel >= MMX; }
bool hasSSE1() const { return X86SSELevel >= SSE1; }
bool hasSSE2() const { return X86SSELevel >= SSE2; }
bool hasSSE3() const { return X86SSELevel >= SSE3; }
bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
bool hasSSE41() const { return X86SSELevel >= SSE41; }
bool hasSSE42() const { return X86SSELevel >= SSE42; }
bool hasAVX() const { return X86SSELevel >= AVX; }
bool hasAVX2() const { return X86SSELevel >= AVX2; }
bool hasSSE4A() const { return HasSSE4A; }
bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
bool hasPOPCNT() const { return HasPOPCNT; }
bool hasAES() const { return HasAES; }
bool hasCLMUL() const { return HasCLMUL; }
bool hasFMA3() const { return HasFMA3; }
bool hasFMA4() const { return HasFMA4; }
bool hasXOP() const { return HasXOP; }
bool hasMOVBE() const { return HasMOVBE; }
bool hasRDRAND() const { return HasRDRAND; }
bool hasF16C() const { return HasF16C; }
bool hasFSGSBase() const { return HasFSGSBase; }
bool hasLZCNT() const { return HasLZCNT; }
bool hasBMI() const { return HasBMI; }
bool hasBMI2() const { return HasBMI2; }
bool isBTMemSlow() const { return IsBTMemSlow; }
bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
bool hasVectorUAMem() const { return HasVectorUAMem; }
bool hasCmpxchg16b() const { return HasCmpxchg16b; }
bool useLeaForSP() const { return UseLeaForSP; }
bool isAtom() const { return X86ProcFamily == IntelAtom; }
const Triple &getTargetTriple() const { return TargetTriple; }
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
bool isTargetFreeBSD() const {
return TargetTriple.getOS() == Triple::FreeBSD;
}
bool isTargetSolaris() const {
return TargetTriple.getOS() == Triple::Solaris;
}
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
bool isTargetNaCl() const {
return TargetTriple.getOS() == Triple::NativeClient;
}
bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
bool isTargetWin64() const {
return In64BitMode && TargetTriple.isOSWindows();
}
bool isTargetWin32() const {
return !In64BitMode && (isTargetMingw() || isTargetWindows());
}
bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
bool isPICStyleStubPIC() const {
return PICStyle == PICStyles::StubPIC;
}
bool isPICStyleStubNoDynamic() const {
return PICStyle == PICStyles::StubDynamicNoPIC;
}
bool isPICStyleStubAny() const {
return PICStyle == PICStyles::StubDynamicNoPIC ||
PICStyle == PICStyles::StubPIC; }
unsigned char ClassifyGlobalReference(const GlobalValue *GV,
const TargetMachine &TM)const;
unsigned char ClassifyBlockAddressReference() const;
bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
const char *getBZeroEntry() const;
unsigned getSpecialAddressLatency() const;
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const;
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
};
}
#endif